2 * Copyright (c) 2011-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 * Definition of the Packet Class, a packet is a transaction occuring
48 * between a single level of the memory heirarchy (ie L1->L2).
51 #include "mem/packet.hh"
59 #include "base/cprintf.hh"
60 #include "base/logging.hh"
61 #include "base/trace.hh"
62 #include "mem/packet_access.hh"
64 // The one downside to bitsets is that static initializers can get ugly.
65 #define SET1(a1) (1 << (a1))
66 #define SET2(a1, a2) (SET1(a1) | SET1(a2))
67 #define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3))
68 #define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4))
69 #define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5))
70 #define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6))
71 #define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \
74 const MemCmd::CommandInfo
75 MemCmd::commandInfo
[] =
78 { 0, InvalidCmd
, "InvalidCmd" },
79 /* ReadReq - Read issued by a non-caching agent such as a CPU or
80 * device, with no restrictions on alignment. */
81 { SET3(IsRead
, IsRequest
, NeedsResponse
), ReadResp
, "ReadReq" },
83 { SET3(IsRead
, IsResponse
, HasData
), InvalidCmd
, "ReadResp" },
84 /* ReadRespWithInvalidate */
85 { SET4(IsRead
, IsResponse
, HasData
, IsInvalidate
),
86 InvalidCmd
, "ReadRespWithInvalidate" },
88 { SET5(IsWrite
, NeedsWritable
, IsRequest
, NeedsResponse
, HasData
),
89 WriteResp
, "WriteReq" },
91 { SET2(IsWrite
, IsResponse
), InvalidCmd
, "WriteResp" },
93 { SET5(IsWrite
, IsRequest
, IsEviction
, HasData
, FromCache
),
94 InvalidCmd
, "WritebackDirty" },
95 /* WritebackClean - This allows the upstream cache to writeback a
96 * line to the downstream cache without it being considered
98 { SET5(IsWrite
, IsRequest
, IsEviction
, HasData
, FromCache
),
99 InvalidCmd
, "WritebackClean" },
100 /* WriteClean - This allows a cache to write a dirty block to a memory
101 below without evicting its copy. */
102 { SET4(IsWrite
, IsRequest
, HasData
, FromCache
), InvalidCmd
, "WriteClean" },
104 { SET3(IsRequest
, IsEviction
, FromCache
), InvalidCmd
, "CleanEvict" },
106 { SET4(IsRead
, IsRequest
, IsSWPrefetch
, NeedsResponse
),
107 SoftPFResp
, "SoftPFReq" },
109 { SET6(IsRead
, NeedsWritable
, IsInvalidate
, IsRequest
,
110 IsSWPrefetch
, NeedsResponse
), SoftPFResp
, "SoftPFExReq" },
112 { SET5(IsRead
, IsRequest
, IsHWPrefetch
, NeedsResponse
, FromCache
),
113 HardPFResp
, "HardPFReq" },
115 { SET4(IsRead
, IsResponse
, IsSWPrefetch
, HasData
),
116 InvalidCmd
, "SoftPFResp" },
118 { SET4(IsRead
, IsResponse
, IsHWPrefetch
, HasData
),
119 InvalidCmd
, "HardPFResp" },
121 { SET5(IsWrite
, NeedsWritable
, IsRequest
, NeedsResponse
, HasData
),
122 WriteResp
, "WriteLineReq" },
124 { SET6(IsInvalidate
, NeedsWritable
, IsUpgrade
, IsRequest
, NeedsResponse
,
126 UpgradeResp
, "UpgradeReq" },
127 /* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */
128 { SET7(IsInvalidate
, NeedsWritable
, IsUpgrade
, IsLlsc
,
129 IsRequest
, NeedsResponse
, FromCache
),
130 UpgradeResp
, "SCUpgradeReq" },
132 { SET2(IsUpgrade
, IsResponse
),
133 InvalidCmd
, "UpgradeResp" },
134 /* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */
135 { SET7(IsRead
, NeedsWritable
, IsInvalidate
,
136 IsLlsc
, IsRequest
, NeedsResponse
, FromCache
),
137 UpgradeFailResp
, "SCUpgradeFailReq" },
138 /* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC
139 * that it has failed, acquires line as Dirty*/
140 { SET3(IsRead
, IsResponse
, HasData
),
141 InvalidCmd
, "UpgradeFailResp" },
142 /* ReadExReq - Read issues by a cache, always cache-line aligned,
143 * and the response is guaranteed to be writeable (exclusive or
145 { SET6(IsRead
, NeedsWritable
, IsInvalidate
, IsRequest
, NeedsResponse
,
147 ReadExResp
, "ReadExReq" },
148 /* ReadExResp - Response matching a read exclusive, as we check
149 * the need for exclusive also on responses */
150 { SET3(IsRead
, IsResponse
, HasData
),
151 InvalidCmd
, "ReadExResp" },
152 /* ReadCleanReq - Read issued by a cache, always cache-line
153 * aligned, and the response is guaranteed to not contain dirty data
154 * (exclusive or shared).*/
155 { SET4(IsRead
, IsRequest
, NeedsResponse
, FromCache
),
156 ReadResp
, "ReadCleanReq" },
157 /* ReadSharedReq - Read issued by a cache, always cache-line
158 * aligned, response is shared, possibly exclusive, owned or even
160 { SET4(IsRead
, IsRequest
, NeedsResponse
, FromCache
),
161 ReadResp
, "ReadSharedReq" },
162 /* LoadLockedReq: note that we use plain ReadResp as response, so that
163 * we can also use ReadRespWithInvalidate when needed */
164 { SET4(IsRead
, IsLlsc
, IsRequest
, NeedsResponse
),
165 ReadResp
, "LoadLockedReq" },
167 { SET6(IsWrite
, NeedsWritable
, IsLlsc
,
168 IsRequest
, NeedsResponse
, HasData
),
169 StoreCondResp
, "StoreCondReq" },
170 /* StoreCondFailReq: generates failing StoreCondResp */
171 { SET6(IsWrite
, NeedsWritable
, IsLlsc
,
172 IsRequest
, NeedsResponse
, HasData
),
173 StoreCondResp
, "StoreCondFailReq" },
175 { SET3(IsWrite
, IsLlsc
, IsResponse
),
176 InvalidCmd
, "StoreCondResp" },
177 /* SwapReq -- for Swap ldstub type operations */
178 { SET6(IsRead
, IsWrite
, NeedsWritable
, IsRequest
, HasData
, NeedsResponse
),
179 SwapResp
, "SwapReq" },
180 /* SwapResp -- for Swap ldstub type operations */
181 { SET4(IsRead
, IsWrite
, IsResponse
, HasData
),
182 InvalidCmd
, "SwapResp" },
183 { 0, InvalidCmd
, "Deprecated_MessageReq" },
184 { 0, InvalidCmd
, "Deprecated_MessageResp" },
185 /* MemFenceReq -- for synchronization requests */
186 {SET2(IsRequest
, NeedsResponse
), MemFenceResp
, "MemFenceReq"},
187 /* MemFenceResp -- for synchronization responses */
188 {SET1(IsResponse
), InvalidCmd
, "MemFenceResp"},
189 /* Cache Clean Request -- Update with the latest data all existing
190 copies of the block down to the point indicated by the
192 { SET4(IsRequest
, IsClean
, NeedsResponse
, FromCache
),
193 CleanSharedResp
, "CleanSharedReq" },
194 /* Cache Clean Response - Indicates that all caches up to the
195 specified point of reference have a up-to-date copy of the
196 cache block or no copy at all */
197 { SET2(IsResponse
, IsClean
), InvalidCmd
, "CleanSharedResp" },
198 /* Cache Clean and Invalidate Request -- Invalidate all existing
199 copies down to the point indicated by the request */
200 { SET5(IsRequest
, IsInvalidate
, IsClean
, NeedsResponse
, FromCache
),
201 CleanInvalidResp
, "CleanInvalidReq" },
202 /* Cache Clean and Invalidate Respose -- Indicates that no cache
203 above the specified point holds the block and that the block
204 was written to a memory below the specified point. */
205 { SET3(IsResponse
, IsInvalidate
, IsClean
),
206 InvalidCmd
, "CleanInvalidResp" },
207 /* InvalidDestError -- packet dest field invalid */
208 { SET2(IsResponse
, IsError
), InvalidCmd
, "InvalidDestError" },
209 /* BadAddressError -- memory address invalid */
210 { SET2(IsResponse
, IsError
), InvalidCmd
, "BadAddressError" },
211 /* FunctionalReadError */
212 { SET3(IsRead
, IsResponse
, IsError
), InvalidCmd
, "FunctionalReadError" },
213 /* FunctionalWriteError */
214 { SET3(IsWrite
, IsResponse
, IsError
), InvalidCmd
, "FunctionalWriteError" },
216 { SET2(IsRequest
, IsPrint
), InvalidCmd
, "PrintReq" },
218 { SET3(IsRequest
, IsFlush
, NeedsWritable
), InvalidCmd
, "FlushReq" },
219 /* Invalidation Request */
220 { SET5(IsInvalidate
, IsRequest
, NeedsWritable
, NeedsResponse
, FromCache
),
221 InvalidateResp
, "InvalidateReq" },
222 /* Invalidation Response */
223 { SET2(IsInvalidate
, IsResponse
),
224 InvalidCmd
, "InvalidateResp" }
228 Packet::getAddrRange() const
230 return RangeSize(getAddr(), getSize());
234 Packet::trySatisfyFunctional(Printable
*obj
, Addr addr
, bool is_secure
, int size
,
237 const Addr func_start
= getAddr();
238 const Addr func_end
= getAddr() + getSize() - 1;
239 const Addr val_start
= addr
;
240 const Addr val_end
= val_start
+ size
- 1;
242 if (is_secure
!= _isSecure
|| func_start
> val_end
||
243 val_start
> func_end
) {
248 // check print first since it doesn't require data
251 safe_cast
<PrintReqState
*>(senderState
)->printObj(obj
);
255 // we allow the caller to pass NULL to signify the other packet
261 const Addr val_offset
= func_start
> val_start
?
262 func_start
- val_start
: 0;
263 const Addr func_offset
= func_start
< val_start
?
264 val_start
- func_start
: 0;
265 const Addr overlap_size
= std::min(val_end
, func_end
)+1 -
266 std::max(val_start
, func_start
);
269 std::memcpy(getPtr
<uint8_t>() + func_offset
,
273 // initialise the tracking of valid bytes if we have not
275 if (bytesValid
.empty())
276 bytesValid
.resize(getSize(), false);
278 // track if we are done filling the functional access
279 bool all_bytes_valid
= true;
283 // check up to func_offset
284 for (; all_bytes_valid
&& i
< func_offset
; ++i
)
285 all_bytes_valid
&= bytesValid
[i
];
287 // update the valid bytes
288 for (i
= func_offset
; i
< func_offset
+ overlap_size
; ++i
)
289 bytesValid
[i
] = true;
291 // check the bit after the update we just made
292 for (; all_bytes_valid
&& i
< getSize(); ++i
)
293 all_bytes_valid
&= bytesValid
[i
];
295 return all_bytes_valid
;
296 } else if (isWrite()) {
297 std::memcpy(_data
+ val_offset
,
298 getConstPtr
<uint8_t>() + func_offset
,
301 panic("Don't know how to handle command %s\n", cmdString());
304 // keep going with request by default
309 Packet::copyResponderFlags(const PacketPtr pkt
)
312 // If we have already found a responder, no other cache should
313 // commit to responding
314 assert(!pkt
->cacheResponding() || !cacheResponding());
315 flags
.set(pkt
->flags
& RESPONDER_FLAGS
);
319 Packet::pushSenderState(Packet::SenderState
*sender_state
)
321 assert(sender_state
!= NULL
);
322 sender_state
->predecessor
= senderState
;
323 senderState
= sender_state
;
326 Packet::SenderState
*
327 Packet::popSenderState()
329 assert(senderState
!= NULL
);
330 SenderState
*sender_state
= senderState
;
331 senderState
= sender_state
->predecessor
;
332 sender_state
->predecessor
= NULL
;
337 Packet::getUintX(ByteOrder endian
) const
341 return (uint64_t)get
<uint8_t>(endian
);
343 return (uint64_t)get
<uint16_t>(endian
);
345 return (uint64_t)get
<uint32_t>(endian
);
347 return (uint64_t)get
<uint64_t>(endian
);
349 panic("%i isn't a supported word size.\n", getSize());
354 Packet::setUintX(uint64_t w
, ByteOrder endian
)
358 set
<uint8_t>((uint8_t)w
, endian
);
361 set
<uint16_t>((uint16_t)w
, endian
);
364 set
<uint32_t>((uint32_t)w
, endian
);
367 set
<uint64_t>((uint64_t)w
, endian
);
370 panic("%i isn't a supported word size.\n", getSize());
376 Packet::print(std::ostream
&o
, const int verbosity
,
377 const std::string
&prefix
) const
379 ccprintf(o
, "%s%s [%x:%x]%s%s%s%s%s%s", prefix
, cmdString(),
380 getAddr(), getAddr() + getSize() - 1,
381 req
->isSecure() ? " (s)" : "",
382 req
->isInstFetch() ? " IF" : "",
383 req
->isUncacheable() ? " UC" : "",
384 isExpressSnoop() ? " ES" : "",
385 req
->isToPOC() ? " PoC" : "",
386 req
->isToPOU() ? " PoU" : "");
390 Packet::print() const {
391 std::ostringstream str
;
397 Packet::matchBlockAddr(const Addr addr
, const bool is_secure
,
398 const int blk_size
) const
400 return (getBlockAddr(blk_size
) == addr
) && (isSecure() == is_secure
);
404 Packet::matchBlockAddr(const PacketPtr pkt
, const int blk_size
) const
406 return matchBlockAddr(pkt
->getBlockAddr(blk_size
), pkt
->isSecure(),
411 Packet::matchAddr(const Addr addr
, const bool is_secure
) const
413 return (getAddr() == addr
) && (isSecure() == is_secure
);
417 Packet::matchAddr(const PacketPtr pkt
) const
419 return matchAddr(pkt
->getAddr(), pkt
->isSecure());
422 Packet::PrintReqState::PrintReqState(std::ostream
&_os
, int _verbosity
)
423 : curPrefixPtr(new std::string("")), os(_os
), verbosity(_verbosity
)
425 labelStack
.push_back(LabelStackEntry("", curPrefixPtr
));
428 Packet::PrintReqState::~PrintReqState()
430 labelStack
.pop_back();
431 assert(labelStack
.empty());
435 Packet::PrintReqState::
436 LabelStackEntry::LabelStackEntry(const std::string
&_label
,
437 std::string
*_prefix
)
438 : label(_label
), prefix(_prefix
), labelPrinted(false)
443 Packet::PrintReqState::pushLabel(const std::string
&lbl
,
444 const std::string
&prefix
)
446 labelStack
.push_back(LabelStackEntry(lbl
, curPrefixPtr
));
447 curPrefixPtr
= new std::string(*curPrefixPtr
);
448 *curPrefixPtr
+= prefix
;
452 Packet::PrintReqState::popLabel()
455 curPrefixPtr
= labelStack
.back().prefix
;
456 labelStack
.pop_back();
457 assert(!labelStack
.empty());
461 Packet::PrintReqState::printLabels()
463 if (!labelStack
.back().labelPrinted
) {
464 LabelStack::iterator i
= labelStack
.begin();
465 LabelStack::iterator end
= labelStack
.end();
467 if (!i
->labelPrinted
) {
468 ccprintf(os
, "%s%s\n", *(i
->prefix
), i
->label
);
469 i
->labelPrinted
= true;
478 Packet::PrintReqState::printObj(Printable
*obj
)
481 obj
->print(os
, verbosity
, curPrefix());