src/mem/packet_access.hh

   1 /*
   2  * Copyright (c) 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  *          Nathan Binkert
  42  *          Andreas Sandberg
  43  */
  44
  45 #include "arch/isa_traits.hh"
  46 #include "mem/packet.hh"
  47 #include "sim/byteswap.hh"
  48
  49 #ifndef __MEM_PACKET_ACCESS_HH__
  50 #define __MEM_PACKET_ACCESS_HH__
  51
  52 template <typename T>
  53 inline T
  54 Packet::getRaw() const
  55 {
  56     assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
  57     assert(sizeof(T) <= size);
  58     return *(T*)data;
  59 }
  60
  61 template <typename T>
  62 inline void
  63 Packet::setRaw(T v)
  64 {
  65     assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
  66     assert(sizeof(T) <= size);
  67     *(T*)data = v;
  68 }
  69
  70
  71 template <typename T>
  72 inline T
  73 Packet::getBE() const
  74 {
  75     return betoh(getRaw<T>());
  76 }
  77
  78 template <typename T>
  79 inline T
  80 Packet::getLE() const
  81 {
  82     return letoh(getRaw<T>());
  83 }
  84
  85 template <typename T>
  86 inline T
  87 Packet::get(ByteOrder endian) const
  88 {
  89     switch (endian) {
  90       case BigEndianByteOrder:
  91         return getBE<T>();
  92
  93       case LittleEndianByteOrder:
  94         return getLE<T>();
  95
  96       default:
  97         panic("Illegal byte order in Packet::get()\n");
  98     };
  99 }
 100
 101 #if THE_ISA != NULL_ISA
 102 template <typename T>
 103 inline T
 104 Packet::get() const
 105 {
 106     return TheISA::gtoh(getRaw<T>());
 107 }
 108 #endif
 109
 110 template <typename T>
 111 inline void
 112 Packet::setBE(T v)
 113 {
 114     setRaw(htobe(v));
 115 }
 116
 117 template <typename T>
 118 inline void
 119 Packet::setLE(T v)
 120 {
 121     setRaw(htole(v));
 122 }
 123
 124 template <typename T>
 125 inline void
 126 Packet::set(T v, ByteOrder endian)
 127 {
 128     switch (endian) {
 129       case BigEndianByteOrder:
 130         return setBE<T>(v);
 131
 132       case LittleEndianByteOrder:
 133         return setLE<T>(v);
 134
 135       default:
 136         panic("Illegal byte order in Packet::set()\n");
 137     };
 138 }
 139
 140 #if THE_ISA != NULL_ISA
 141 template <typename T>
 142 inline void
 143 Packet::set(T v)
 144 {
 145     setRaw(TheISA::htog(v));
 146 }
 147 #endif
 148
 149 #endif //__MEM_PACKET_ACCESS_HH__