2 * Copyright (c) 2003 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
34 * Definitions of page table.
40 #include "arch/faults.hh"
41 #include "base/bitfield.hh"
42 #include "base/intmath.hh"
43 #include "base/trace.hh"
44 #include "mem/page_table.hh"
45 #include "sim/builder.hh"
46 #include "sim/sim_object.hh"
47 #include "sim/system.hh"
50 using namespace TheISA
;
52 PageTable::PageTable(System
*_system
, Addr _pageSize
)
53 : pageSize(_pageSize
), offsetMask(mask(floorLog2(_pageSize
))),
56 assert(isPowerOf2(pageSize
));
57 pTableCache
[0].vaddr
= 0;
58 pTableCache
[1].vaddr
= 0;
59 pTableCache
[2].vaddr
= 0;
62 PageTable::~PageTable()
67 PageTable::page_check(Addr addr
, int64_t size
) const
69 if (size
< sizeof(uint64_t)) {
70 if (!isPowerOf2(size
)) {
71 panic("Invalid request size!\n");
72 return genMachineCheckFault();
75 if ((size
- 1) & addr
)
76 return genAlignmentFault();
79 if ((addr
& (VMPageSize
- 1)) + size
> VMPageSize
) {
80 panic("Invalid request size!\n");
81 return genMachineCheckFault();
84 if ((sizeof(uint64_t) - 1) & addr
)
85 return genAlignmentFault();
95 PageTable::allocate(Addr vaddr
, int64_t size
)
97 // starting address must be page aligned
98 assert(pageOffset(vaddr
) == 0);
100 for (; size
> 0; size
-= pageSize
, vaddr
+= pageSize
) {
101 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(vaddr
);
103 if (iter
!= pTable
.end()) {
105 fatal("PageTable::allocate: address 0x%x already mapped", vaddr
);
108 pTable
[vaddr
] = system
->new_page();
109 pTableCache
[2].paddr
= pTableCache
[1].paddr
;
110 pTableCache
[2].vaddr
= pTableCache
[1].vaddr
;
111 pTableCache
[1].paddr
= pTableCache
[0].paddr
;
112 pTableCache
[1].vaddr
= pTableCache
[0].vaddr
;
113 pTableCache
[0].paddr
= pTable
[vaddr
];
114 pTableCache
[0].vaddr
= vaddr
;
121 PageTable::translate(Addr vaddr
, Addr
&paddr
)
123 Addr page_addr
= pageAlign(vaddr
);
126 if (pTableCache
[0].vaddr
== vaddr
) {
127 paddr
= pTableCache
[0].paddr
;
130 if (pTableCache
[1].vaddr
== vaddr
) {
131 paddr
= pTableCache
[1].paddr
;
134 if (pTableCache
[2].vaddr
== vaddr
) {
135 paddr
= pTableCache
[2].paddr
;
139 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(page_addr
);
141 if (iter
== pTable
.end()) {
145 paddr
= iter
->second
+ pageOffset(vaddr
);
151 PageTable::translate(RequestPtr
&req
)
154 assert(pageAlign(req
->getVaddr() + req
->getSize() - 1)
155 == pageAlign(req
->getVaddr()));
156 if (!translate(req
->getVaddr(), paddr
)) {
157 return genPageTableFault(req
->getVaddr());
159 req
->setPaddr(paddr
);
160 return page_check(req
->getPaddr(), req
->getSize());