src/mem/page_table.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Ron Dreslinski
  30  *          Ali Saidi
  31  */
  32
  33 /**
  34  * @file
  35  * Definitions of page table.
  36  */
  37 #include <fstream>
  38 #include <map>
  39 #include <string>
  40
  41 #include "base/bitfield.hh"
  42 #include "base/intmath.hh"
  43 #include "base/trace.hh"
  44 #include "config/the_isa.hh"
  45 #include "debug/MMU.hh"
  46 #include "mem/page_table.hh"
  47 #include "sim/faults.hh"
  48 #include "sim/process.hh"
  49 #include "sim/sim_object.hh"
  50 #include "sim/system.hh"
  51
  52 using namespace std;
  53 using namespace TheISA;
  54
  55 PageTable::PageTable(Process *_process, Addr _pageSize)
  56     : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
  57       process(_process)
  58 {
  59     assert(isPowerOf2(pageSize));
  60     pTableCache[0].vaddr = 0;
  61     pTableCache[1].vaddr = 0;
  62     pTableCache[2].vaddr = 0;
  63 }
  64
  65 PageTable::~PageTable()
  66 {
  67 }
  68
  69 void
  70 PageTable::allocate(Addr vaddr, int64_t size)
  71 {
  72     // starting address must be page aligned
  73     assert(pageOffset(vaddr) == 0);
  74
  75     DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
  76
  77     for (; size > 0; size -= pageSize, vaddr += pageSize) {
  78         PTableItr iter = pTable.find(vaddr);
  79
  80         if (iter != pTable.end()) {
  81             // already mapped
  82             fatal("PageTable::allocate: address 0x%x already mapped",
  83                     vaddr);
  84         }
  85
  86         pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
  87                 process->system->new_page());
  88         updateCache(vaddr, pTable[vaddr]);
  89     }
  90 }
  91
  92 void
  93 PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
  94 {
  95     assert(pageOffset(vaddr) == 0);
  96     assert(pageOffset(new_vaddr) == 0);
  97
  98     DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
  99             new_vaddr, size);
 100
 101     for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
 102         PTableItr iter = pTable.find(vaddr);
 103
 104         assert(iter != pTable.end());
 105
 106         pTable[new_vaddr] = pTable[vaddr];
 107         pTable.erase(vaddr);
 108         pTable[new_vaddr].updateVaddr(new_vaddr);
 109         updateCache(new_vaddr, pTable[new_vaddr]);
 110     }
 111 }
 112
 113 void
 114 PageTable::deallocate(Addr vaddr, int64_t size)
 115 {
 116     assert(pageOffset(vaddr) == 0);
 117
 118     DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
 119
 120     for (; size > 0; size -= pageSize, vaddr += pageSize) {
 121         PTableItr iter = pTable.find(vaddr);
 122
 123         assert(iter != pTable.end());
 124
 125         pTable.erase(vaddr);
 126     }
 127
 128 }
 129
 130 bool
 131 PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
 132 {
 133     Addr page_addr = pageAlign(vaddr);
 134
 135     if (pTableCache[0].vaddr == page_addr) {
 136         entry = pTableCache[0].entry;
 137         return true;
 138     }
 139     if (pTableCache[1].vaddr == page_addr) {
 140         entry = pTableCache[1].entry;
 141         return true;
 142     }
 143     if (pTableCache[2].vaddr == page_addr) {
 144         entry = pTableCache[2].entry;
 145         return true;
 146     }
 147
 148     PTableItr iter = pTable.find(page_addr);
 149
 150     if (iter == pTable.end()) {
 151         return false;
 152     }
 153
 154     updateCache(page_addr, iter->second);
 155     entry = iter->second;
 156     return true;
 157 }
 158
 159 bool
 160 PageTable::translate(Addr vaddr, Addr &paddr)
 161 {
 162     TheISA::TlbEntry entry;
 163     if (!lookup(vaddr, entry)) {
 164         DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
 165         return false;
 166     }
 167     paddr = pageOffset(vaddr) + entry.pageStart();
 168     DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
 169     return true;
 170 }
 171
 172 Fault
 173 PageTable::translate(RequestPtr req)
 174 {
 175     Addr paddr;
 176     assert(pageAlign(req->getVaddr() + req->getSize() - 1)
 177            == pageAlign(req->getVaddr()));
 178     if (!translate(req->getVaddr(), paddr)) {
 179         return Fault(new GenericPageTableFault(req->getVaddr()));
 180     }
 181     req->setPaddr(paddr);
 182     if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
 183         panic("Request spans page boundaries!\n");
 184         return NoFault;
 185     }
 186     return NoFault;
 187 }
 188
 189 void
 190 PageTable::serialize(std::ostream &os)
 191 {
 192     paramOut(os, "ptable.size", pTable.size());
 193
 194     PTable::size_type count = 0;
 195
 196     PTableItr iter = pTable.begin();
 197     PTableItr end = pTable.end();
 198     while (iter != end) {
 199         os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
 200
 201         paramOut(os, "vaddr", iter->first);
 202         iter->second.serialize(os);
 203
 204         ++iter;
 205         ++count;
 206     }
 207     assert(count == pTable.size());
 208 }
 209
 210 void
 211 PageTable::unserialize(Checkpoint *cp, const std::string &section)
 212 {
 213     int i = 0, count;
 214     paramIn(cp, section, "ptable.size", count);
 215     Addr vaddr;
 216     TheISA::TlbEntry *entry;
 217
 218     pTable.clear();
 219
 220     while(i < count) {
 221         paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
 222         entry = new TheISA::TlbEntry();
 223         entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
 224         pTable[vaddr] = *entry;
 225         ++i;
 226     }
 227 }
 228