src/mem/page_table.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Ron Dreslinski
  30  *          Ali Saidi
  31  */
  32
  33 /**
  34  * @file
  35  * Definitions of page table.
  36  */
  37 #include <fstream>
  38 #include <map>
  39 #include <string>
  40
  41 #include "base/bitfield.hh"
  42 #include "base/intmath.hh"
  43 #include "base/trace.hh"
  44 #include "config/the_isa.hh"
  45 #include "debug/MMU.hh"
  46 #include "mem/page_table.hh"
  47 #include "sim/faults.hh"
  48 #include "sim/sim_object.hh"
  49
  50 using namespace std;
  51 using namespace TheISA;
  52
  53 PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
  54     : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
  55       pid(_pid), _name(__name)
  56 {
  57     assert(isPowerOf2(pageSize));
  58     pTableCache[0].valid = false;
  59     pTableCache[1].valid = false;
  60     pTableCache[2].valid = false;
  61 }
  62
  63 PageTable::~PageTable()
  64 {
  65 }
  66
  67 void
  68 PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
  69 {
  70     // starting address must be page aligned
  71     assert(pageOffset(vaddr) == 0);
  72
  73     DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
  74
  75     for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
  76         if (!clobber && (pTable.find(vaddr) != pTable.end())) {
  77             // already mapped
  78             fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
  79         }
  80
  81         pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
  82         eraseCacheEntry(vaddr);
  83         updateCache(vaddr, pTable[vaddr]);
  84     }
  85 }
  86
  87 void
  88 PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
  89 {
  90     assert(pageOffset(vaddr) == 0);
  91     assert(pageOffset(new_vaddr) == 0);
  92
  93     DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
  94             new_vaddr, size);
  95
  96     for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
  97         assert(pTable.find(vaddr) != pTable.end());
  98
  99         pTable[new_vaddr] = pTable[vaddr];
 100         pTable.erase(vaddr);
 101         eraseCacheEntry(vaddr);
 102         pTable[new_vaddr].updateVaddr(new_vaddr);
 103         updateCache(new_vaddr, pTable[new_vaddr]);
 104     }
 105 }
 106
 107 void
 108 PageTable::unmap(Addr vaddr, int64_t size)
 109 {
 110     assert(pageOffset(vaddr) == 0);
 111
 112     DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
 113
 114     for (; size > 0; size -= pageSize, vaddr += pageSize) {
 115         assert(pTable.find(vaddr) != pTable.end());
 116         pTable.erase(vaddr);
 117         eraseCacheEntry(vaddr);
 118     }
 119
 120 }
 121
 122 bool
 123 PageTable::isUnmapped(Addr vaddr, int64_t size)
 124 {
 125     // starting address must be page aligned
 126     assert(pageOffset(vaddr) == 0);
 127
 128     for (; size > 0; size -= pageSize, vaddr += pageSize) {
 129         if (pTable.find(vaddr) != pTable.end()) {
 130             return false;
 131         }
 132     }
 133
 134     return true;
 135 }
 136
 137 bool
 138 PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
 139 {
 140     Addr page_addr = pageAlign(vaddr);
 141
 142     if (pTableCache[0].valid && pTableCache[0].vaddr == page_addr) {
 143         entry = pTableCache[0].entry;
 144         return true;
 145     }
 146     if (pTableCache[1].valid && pTableCache[1].vaddr == page_addr) {
 147         entry = pTableCache[1].entry;
 148         return true;
 149     }
 150     if (pTableCache[2].valid && pTableCache[2].vaddr == page_addr) {
 151         entry = pTableCache[2].entry;
 152         return true;
 153     }
 154
 155     PTableItr iter = pTable.find(page_addr);
 156
 157     if (iter == pTable.end()) {
 158         return false;
 159     }
 160
 161     updateCache(page_addr, iter->second);
 162     entry = iter->second;
 163     return true;
 164 }
 165
 166 bool
 167 PageTable::translate(Addr vaddr, Addr &paddr)
 168 {
 169     TheISA::TlbEntry entry;
 170     if (!lookup(vaddr, entry)) {
 171         DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
 172         return false;
 173     }
 174     paddr = pageOffset(vaddr) + entry.pageStart();
 175     DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
 176     return true;
 177 }
 178
 179 Fault
 180 PageTable::translate(RequestPtr req)
 181 {
 182     Addr paddr;
 183     assert(pageAlign(req->getVaddr() + req->getSize() - 1)
 184            == pageAlign(req->getVaddr()));
 185     if (!translate(req->getVaddr(), paddr)) {
 186         return Fault(new GenericPageTableFault(req->getVaddr()));
 187     }
 188     req->setPaddr(paddr);
 189     if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
 190         panic("Request spans page boundaries!\n");
 191         return NoFault;
 192     }
 193     return NoFault;
 194 }
 195
 196 void
 197 PageTable::serialize(std::ostream &os)
 198 {
 199     paramOut(os, "ptable.size", pTable.size());
 200
 201     PTable::size_type count = 0;
 202
 203     PTableItr iter = pTable.begin();
 204     PTableItr end = pTable.end();
 205     while (iter != end) {
 206         os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
 207
 208         paramOut(os, "vaddr", iter->first);
 209         iter->second.serialize(os);
 210
 211         ++iter;
 212         ++count;
 213     }
 214     assert(count == pTable.size());
 215 }
 216
 217 void
 218 PageTable::unserialize(Checkpoint *cp, const std::string &section)
 219 {
 220     int i = 0, count;
 221     paramIn(cp, section, "ptable.size", count);
 222
 223     pTable.clear();
 224
 225     while (i < count) {
 226         TheISA::TlbEntry *entry;
 227         Addr vaddr;
 228
 229         paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
 230         entry = new TheISA::TlbEntry();
 231         entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
 232         pTable[vaddr] = *entry;
 233         delete entry;
 234         ++i;
 235     }
 236 }
 237