src/mem/page_table.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Ron Dreslinski
  30  *          Ali Saidi
  31  */
  32
  33 /**
  34  * @file
  35  * Definitions of page table.
  36  */
  37 #include <string>
  38 #include <map>
  39 #include <fstream>
  40
  41 #include "arch/faults.hh"
  42 #include "base/bitfield.hh"
  43 #include "base/intmath.hh"
  44 #include "base/trace.hh"
  45 #include "mem/page_table.hh"
  46 #include "sim/process.hh"
  47 #include "sim/sim_object.hh"
  48 #include "sim/system.hh"
  49
  50 using namespace std;
  51 using namespace TheISA;
  52
  53 PageTable::PageTable(Process *_process, Addr _pageSize)
  54     : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
  55       process(_process)
  56 {
  57     assert(isPowerOf2(pageSize));
  58     pTableCache[0].vaddr = 0;
  59     pTableCache[1].vaddr = 0;
  60     pTableCache[2].vaddr = 0;
  61 }
  62
  63 PageTable::~PageTable()
  64 {
  65 }
  66
  67 void
  68 PageTable::allocate(Addr vaddr, int64_t size)
  69 {
  70     // starting address must be page aligned
  71     assert(pageOffset(vaddr) == 0);
  72
  73     DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
  74
  75     for (; size > 0; size -= pageSize, vaddr += pageSize) {
  76         PTableItr iter = pTable.find(vaddr);
  77
  78         if (iter != pTable.end()) {
  79             // already mapped
  80             fatal("PageTable::allocate: address 0x%x already mapped",
  81                     vaddr);
  82         }
  83
  84         pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
  85                 process->system->new_page());
  86         updateCache(vaddr, pTable[vaddr]);
  87     }
  88 }
  89
  90 void
  91 PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
  92 {
  93     assert(pageOffset(vaddr) == 0);
  94     assert(pageOffset(new_vaddr) == 0);
  95
  96     DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
  97             new_vaddr, size);
  98
  99     for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
 100         PTableItr iter = pTable.find(vaddr);
 101
 102         assert(iter != pTable.end());
 103
 104         pTable[new_vaddr] = pTable[vaddr];
 105         pTable.erase(vaddr);
 106         pTable[new_vaddr].updateVaddr(new_vaddr);
 107         updateCache(new_vaddr, pTable[new_vaddr]);
 108     }
 109 }
 110
 111 void
 112 PageTable::deallocate(Addr vaddr, int64_t size)
 113 {
 114     assert(pageOffset(vaddr) == 0);
 115
 116     DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
 117
 118     for (; size > 0; size -= pageSize, vaddr += pageSize) {
 119         PTableItr iter = pTable.find(vaddr);
 120
 121         assert(iter != pTable.end());
 122
 123         pTable.erase(vaddr);
 124     }
 125
 126 }
 127
 128 bool
 129 PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
 130 {
 131     Addr page_addr = pageAlign(vaddr);
 132
 133     if (pTableCache[0].vaddr == page_addr) {
 134         entry = pTableCache[0].entry;
 135         return true;
 136     }
 137     if (pTableCache[1].vaddr == page_addr) {
 138         entry = pTableCache[1].entry;
 139         return true;
 140     }
 141     if (pTableCache[2].vaddr == page_addr) {
 142         entry = pTableCache[2].entry;
 143         return true;
 144     }
 145
 146     PTableItr iter = pTable.find(page_addr);
 147
 148     if (iter == pTable.end()) {
 149         return false;
 150     }
 151
 152     updateCache(page_addr, iter->second);
 153     entry = iter->second;
 154     return true;
 155 }
 156
 157 bool
 158 PageTable::translate(Addr vaddr, Addr &paddr)
 159 {
 160     TheISA::TlbEntry entry;
 161     if (!lookup(vaddr, entry)) {
 162         DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
 163         return false;
 164     }
 165     paddr = pageOffset(vaddr) + entry.pageStart();
 166     DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
 167     return true;
 168 }
 169
 170 Fault
 171 PageTable::translate(RequestPtr req)
 172 {
 173     Addr paddr;
 174     assert(pageAlign(req->getVaddr() + req->getSize() - 1)
 175            == pageAlign(req->getVaddr()));
 176     if (!translate(req->getVaddr(), paddr)) {
 177         return Fault(new GenericPageTableFault(req->getVaddr()));
 178     }
 179     req->setPaddr(paddr);
 180     if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
 181         panic("Request spans page boundaries!\n");
 182         return NoFault;
 183     }
 184     return NoFault;
 185 }
 186
 187 void
 188 PageTable::serialize(std::ostream &os)
 189 {
 190     paramOut(os, "ptable.size", pTable.size());
 191
 192     int count = 0;
 193
 194     PTableItr iter = pTable.begin();
 195     PTableItr end = pTable.end();
 196     while (iter != end) {
 197         os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
 198
 199         paramOut(os, "vaddr", iter->first);
 200         iter->second.serialize(os);
 201
 202         ++iter;
 203         ++count;
 204     }
 205     assert(count == pTable.size());
 206 }
 207
 208 void
 209 PageTable::unserialize(Checkpoint *cp, const std::string &section)
 210 {
 211     int i = 0, count;
 212     paramIn(cp, section, "ptable.size", count);
 213     Addr vaddr;
 214     TheISA::TlbEntry *entry;
 215
 216     pTable.clear();
 217
 218     while(i < count) {
 219         paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
 220         entry = new TheISA::TlbEntry();
 221         entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
 222         pTable[vaddr] = *entry;
 223         ++i;
 224    }
 225 }
 226