2 * Copyright (c) 2003 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
35 * Definitions of page table.
41 #include "arch/faults.hh"
42 #include "base/bitfield.hh"
43 #include "base/intmath.hh"
44 #include "base/trace.hh"
45 #include "mem/page_table.hh"
46 #include "sim/builder.hh"
47 #include "sim/sim_object.hh"
48 #include "sim/system.hh"
51 using namespace TheISA
;
53 PageTable::PageTable(System
*_system
, Addr _pageSize
)
54 : pageSize(_pageSize
), offsetMask(mask(floorLog2(_pageSize
))),
57 assert(isPowerOf2(pageSize
));
58 pTableCache
[0].vaddr
= 0;
59 pTableCache
[1].vaddr
= 0;
60 pTableCache
[2].vaddr
= 0;
63 PageTable::~PageTable()
68 PageTable::page_check(Addr addr
, int64_t size
) const
70 if (size
< sizeof(uint64_t)) {
71 if (!isPowerOf2(size
)) {
72 panic("Invalid request size!\n");
73 return genMachineCheckFault();
76 if ((size
- 1) & addr
)
77 return genAlignmentFault();
80 if ((addr
& (VMPageSize
- 1)) + size
> VMPageSize
) {
81 panic("Invalid request size!\n");
82 return genMachineCheckFault();
85 if ((sizeof(uint64_t) - 1) & addr
)
86 return genAlignmentFault();
94 PageTable::allocate(Addr vaddr
, int64_t size
)
96 // starting address must be page aligned
97 assert(pageOffset(vaddr
) == 0);
99 DPRINTF(MMU
, "Allocating Page: %#x-%#x\n", vaddr
, vaddr
+ size
);
101 for (; size
> 0; size
-= pageSize
, vaddr
+= pageSize
) {
102 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(vaddr
);
104 if (iter
!= pTable
.end()) {
106 fatal("PageTable::allocate: address 0x%x already mapped", vaddr
);
109 pTable
[vaddr
] = system
->new_page();
110 updateCache(vaddr
, pTable
[vaddr
]);
117 PageTable::translate(Addr vaddr
, Addr
&paddr
)
119 Addr page_addr
= pageAlign(vaddr
);
122 if (pTableCache
[0].vaddr
== page_addr
) {
123 paddr
= pTableCache
[0].paddr
+ pageOffset(vaddr
);
126 if (pTableCache
[1].vaddr
== page_addr
) {
127 paddr
= pTableCache
[1].paddr
+ pageOffset(vaddr
);
130 if (pTableCache
[2].vaddr
== page_addr
) {
131 paddr
= pTableCache
[2].paddr
+ pageOffset(vaddr
);
135 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(page_addr
);
137 if (iter
== pTable
.end()) {
141 updateCache(page_addr
, iter
->second
);
142 paddr
= iter
->second
+ pageOffset(vaddr
);
148 PageTable::translate(RequestPtr
&req
)
151 assert(pageAlign(req
->getVaddr() + req
->getSize() - 1)
152 == pageAlign(req
->getVaddr()));
153 if (!translate(req
->getVaddr(), paddr
)) {
154 return Fault(new PageTableFault(req
->getVaddr()));
156 req
->setPaddr(paddr
);
157 return page_check(req
->getPaddr(), req
->getSize());
161 PageTable::serialize(std::ostream
&os
)
163 paramOut(os
, "ptable.size", pTable
.size());
167 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.begin();
168 m5::hash_map
<Addr
,Addr
>::iterator end
= pTable
.end();
169 while (iter
!= end
) {
170 paramOut(os
, csprintf("ptable.entry%dvaddr", count
), iter
->first
);
171 paramOut(os
, csprintf("ptable.entry%dpaddr", count
), iter
->second
);
176 assert(count
== pTable
.size());
180 PageTable::unserialize(Checkpoint
*cp
, const std::string
§ion
)
183 paramIn(cp
, section
, "ptable.size", count
);
189 paramIn(cp
, section
, csprintf("ptable.entry%dvaddr", i
), vaddr
);
190 paramIn(cp
, section
, csprintf("ptable.entry%dpaddr", i
), paddr
);
191 pTable
[vaddr
] = paddr
;