2 * Copyright (c) 2003 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
35 * Definitions of page table.
41 #include "arch/faults.hh"
42 #include "base/bitfield.hh"
43 #include "base/intmath.hh"
44 #include "base/trace.hh"
45 #include "mem/page_table.hh"
46 #include "sim/builder.hh"
47 #include "sim/sim_object.hh"
48 #include "sim/system.hh"
51 using namespace TheISA
;
53 PageTable::PageTable(System
*_system
, Addr _pageSize
)
54 : pageSize(_pageSize
), offsetMask(mask(floorLog2(_pageSize
))),
57 assert(isPowerOf2(pageSize
));
58 pTableCache
[0].vaddr
= 0;
59 pTableCache
[1].vaddr
= 0;
60 pTableCache
[2].vaddr
= 0;
63 PageTable::~PageTable()
68 PageTable::page_check(Addr addr
, int64_t size
) const
70 if (size
< sizeof(uint64_t)) {
71 if (!isPowerOf2(size
)) {
72 panic("Invalid request size!\n");
73 return genMachineCheckFault();
76 if ((size
- 1) & addr
)
77 return genAlignmentFault();
80 if ((addr
& (VMPageSize
- 1)) + size
> VMPageSize
) {
81 panic("Invalid request size!\n");
82 return genMachineCheckFault();
85 if ((sizeof(uint64_t) - 1) & addr
)
86 return genAlignmentFault();
96 PageTable::allocate(Addr vaddr
, int64_t size
)
98 // starting address must be page aligned
99 assert(pageOffset(vaddr
) == 0);
101 DPRINTF(MMU
, "Allocating Page: %#x-%#x\n", vaddr
, vaddr
+ size
);
103 for (; size
> 0; size
-= pageSize
, vaddr
+= pageSize
) {
104 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(vaddr
);
106 if (iter
!= pTable
.end()) {
108 fatal("PageTable::allocate: address 0x%x already mapped", vaddr
);
111 pTable
[vaddr
] = system
->new_page();
112 pTableCache
[2].paddr
= pTableCache
[1].paddr
;
113 pTableCache
[2].vaddr
= pTableCache
[1].vaddr
;
114 pTableCache
[1].paddr
= pTableCache
[0].paddr
;
115 pTableCache
[1].vaddr
= pTableCache
[0].vaddr
;
116 pTableCache
[0].paddr
= pTable
[vaddr
];
117 pTableCache
[0].vaddr
= vaddr
;
124 PageTable::translate(Addr vaddr
, Addr
&paddr
)
126 Addr page_addr
= pageAlign(vaddr
);
129 if (pTableCache
[0].vaddr
== vaddr
) {
130 paddr
= pTableCache
[0].paddr
;
133 if (pTableCache
[1].vaddr
== vaddr
) {
134 paddr
= pTableCache
[1].paddr
;
137 if (pTableCache
[2].vaddr
== vaddr
) {
138 paddr
= pTableCache
[2].paddr
;
142 m5::hash_map
<Addr
,Addr
>::iterator iter
= pTable
.find(page_addr
);
144 if (iter
== pTable
.end()) {
148 paddr
= iter
->second
+ pageOffset(vaddr
);
154 PageTable::translate(RequestPtr
&req
)
157 assert(pageAlign(req
->getVaddr() + req
->getSize() - 1)
158 == pageAlign(req
->getVaddr()));
159 if (!translate(req
->getVaddr(), paddr
)) {
160 return genPageTableFault(req
->getVaddr());
162 req
->setPaddr(paddr
);
163 return page_check(req
->getPaddr(), req
->getSize());
167 PageTable::serialize(std::ostream
&os
)
169 paramOut(os
, "ptable.size", pTable
.size());
172 m5::hash_map
<Addr
,Addr
>::iterator iter
;
173 while (iter
!= pTable
.end()) {
174 paramOut(os
, csprintf("ptable.entry%dvaddr", count
),iter
->first
);
175 paramOut(os
, csprintf("ptable.entry%dpaddr", count
),iter
->second
);
178 assert(count
== pTable
.size());
182 PageTable::unserialize(Checkpoint
*cp
, const std::string
§ion
)
185 paramIn(cp
, section
, "ptable.size", count
);
191 paramIn(cp
, section
, csprintf("ptable.entry%dvaddr", i
), vaddr
);
192 paramIn(cp
, section
, csprintf("ptable.entry%dpaddr", i
), paddr
);
193 pTable
[vaddr
] = paddr
;