2 * Copyright (c) 2003 The Regents of The University of Michigan
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28 * Authors: Steve Reinhardt
33 * Declaration of a non-full system Page Table.
36 #ifndef __PAGE_TABLE__
37 #define __PAGE_TABLE__
41 #include "sim/faults.hh"
42 #include "arch/isa_traits.hh"
43 #include "arch/tlb.hh"
44 #include "base/hashmap.hh"
45 #include "mem/request.hh"
46 #include "sim/host.hh"
47 #include "sim/serialize.hh"
52 * Page Table Declaration.
57 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
58 typedef PTable::iterator PTableItr;
63 TheISA::TlbEntry entry;
66 struct cacheElement pTableCache[3];
69 const Addr offsetMask;
75 PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
79 Addr pageAlign(Addr a) { return (a & ~offsetMask); }
80 Addr pageOffset(Addr a) { return (a & offsetMask); }
82 void allocate(Addr vaddr, int64_t size);
86 * @param vaddr The virtual address.
87 * @return entry The page table entry corresponding to vaddr.
89 bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
93 * @param vaddr The virtual address.
94 * @return Physical address from translation.
96 bool translate(Addr vaddr, Addr &paddr);
99 * Perform a translation on the memory request, fills in paddr
101 * @param req The memory request.
103 Fault translate(RequestPtr req);
106 * Update the page table cache.
107 * @param vaddr virtual address (page aligned) to check
108 * @param pte page table entry to return
110 inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
112 pTableCache[2].entry = pTableCache[1].entry;
113 pTableCache[2].vaddr = pTableCache[1].vaddr;
114 pTableCache[1].entry = pTableCache[0].entry;
115 pTableCache[1].vaddr = pTableCache[0].vaddr;
116 pTableCache[0].entry = entry;
117 pTableCache[0].vaddr = vaddr;
121 void serialize(std::ostream &os);
123 void unserialize(Checkpoint *cp, const std::string §ion);