src/mem/page_table.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 /**
  32  * @file
  33  * Declaration of a non-full system Page Table.
  34  */
  35
  36 #ifndef __MEM_PAGE_TABLE_HH__
  37 #define __MEM_PAGE_TABLE_HH__
  38
  39 #include <string>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/tlb.hh"
  43 #include "base/hashmap.hh"
  44 #include "base/types.hh"
  45 #include "config/full_system.hh"
  46 #include "config/the_isa.hh"
  47 #include "mem/request.hh"
  48 #include "sim/serialize.hh"
  49
  50 #if !FULL_SYSTEM
  51 class Process;
  52 #endif
  53
  54 /**
  55  * Page Table Declaration.
  56  */
  57 class PageTable
  58 {
  59   protected:
  60     typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
  61     typedef PTable::iterator PTableItr;
  62     PTable pTable;
  63
  64     struct cacheElement {
  65         Addr vaddr;
  66         TheISA::TlbEntry entry;
  67     };
  68
  69     struct cacheElement pTableCache[3];
  70
  71     const Addr pageSize;
  72     const Addr offsetMask;
  73
  74 #if !FULL_SYSTEM
  75     Process *process;
  76 #endif
  77
  78   public:
  79
  80     PageTable(
  81 #if !FULL_SYSTEM
  82             Process *_process,
  83 #endif
  84             Addr _pageSize = TheISA::VMPageSize);
  85
  86     ~PageTable();
  87
  88     Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
  89     Addr pageOffset(Addr a) { return (a &  offsetMask); }
  90
  91     void allocate(Addr vaddr, int64_t size);
  92     void remap(Addr vaddr, int64_t size, Addr new_vaddr);
  93     void deallocate(Addr vaddr, int64_t size);
  94
  95     /**
  96      * Lookup function
  97      * @param vaddr The virtual address.
  98      * @return entry The page table entry corresponding to vaddr.
  99      */
 100     bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
 101
 102     /**
 103      * Translate function
 104      * @param vaddr The virtual address.
 105      * @param paddr Physical address from translation.
 106      * @return True if translation exists
 107      */
 108     bool translate(Addr vaddr, Addr &paddr);
 109
 110     /**
 111      * Simplified translate function (just check for translation)
 112      * @param vaddr The virtual address.
 113      * @return True if translation exists
 114      */
 115     bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
 116
 117     /**
 118      * Perform a translation on the memory request, fills in paddr
 119      * field of req.
 120      * @param req The memory request.
 121      */
 122     Fault translate(RequestPtr req);
 123
 124     /**
 125      * Update the page table cache.
 126      * @param vaddr virtual address (page aligned) to check
 127      * @param pte page table entry to return
 128      */
 129     inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
 130     {
 131         pTableCache[2].entry = pTableCache[1].entry;
 132         pTableCache[2].vaddr = pTableCache[1].vaddr;
 133         pTableCache[1].entry = pTableCache[0].entry;
 134         pTableCache[1].vaddr = pTableCache[0].vaddr;
 135         pTableCache[0].entry = entry;
 136         pTableCache[0].vaddr = vaddr;
 137     }
 138
 139
 140     void serialize(std::ostream &os);
 141
 142     void unserialize(Checkpoint *cp, const std::string &section);
 143 };
 144
 145 #endif // __MEM_PAGE_TABLE_HH__