src/mem/port.cc

   1 /*
   2  * Copyright (c) 2012,2015,2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Port object definitions.
  44  */
  45 #include "mem/port.hh"
  46
  47 #include "base/trace.hh"
  48 #include "sim/sim_object.hh"
  49
  50 /**
  51  * Master port
  52  */
  53 MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
  54     : Port(name, _id), _slavePort(NULL), owner(*_owner)
  55 {
  56 }
  57
  58 MasterPort::~MasterPort()
  59 {
  60 }
  61
  62 void
  63 MasterPort::bind(Port &peer)
  64 {
  65     auto *slave_port = dynamic_cast<SlavePort *>(&peer);
  66     if (!slave_port) {
  67         fatal("Attempt to bind port %s to non-slave port %s.",
  68                 name(), peer.name());
  69     }
  70     // master port keeps track of the slave port
  71     _slavePort = slave_port;
  72     Port::bind(peer);
  73     // slave port also keeps track of master port
  74     _slavePort->slaveBind(*this);
  75 }
  76
  77 void
  78 MasterPort::unbind()
  79 {
  80     if (_slavePort == NULL)
  81         panic("Attempting to unbind master port %s that is not connected\n",
  82               name());
  83     _slavePort->slaveUnbind();
  84     _slavePort = nullptr;
  85     Port::unbind();
  86 }
  87
  88 AddrRangeList
  89 MasterPort::getAddrRanges() const
  90 {
  91     return _slavePort->getAddrRanges();
  92 }
  93
  94 void
  95 MasterPort::printAddr(Addr a)
  96 {
  97     auto req = std::make_shared<Request>(
  98         a, 1, 0, Request::funcMasterId);
  99
 100     Packet pkt(req, MemCmd::PrintReq);
 101     Packet::PrintReqState prs(std::cerr);
 102     pkt.senderState = &prs;
 103
 104     sendFunctional(&pkt);
 105 }
 106
 107 /**
 108  * Slave port
 109  */
 110 SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
 111     : Port(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
 112     owner(*_owner)
 113 {
 114 }
 115
 116 SlavePort::~SlavePort()
 117 {
 118 }
 119
 120 void
 121 SlavePort::slaveUnbind()
 122 {
 123     _masterPort = NULL;
 124     Port::unbind();
 125 }
 126
 127 void
 128 SlavePort::slaveBind(MasterPort& master_port)
 129 {
 130     _masterPort = &master_port;
 131     Port::bind(master_port);
 132 }
 133
 134 Tick
 135 SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
 136 {
 137     if (!defaultBackdoorWarned) {
 138         warn("Port %s doesn't support requesting a back door.", name());
 139         defaultBackdoorWarned = true;
 140     }
 141     return recvAtomic(pkt);
 142 }