src/mem/port.cc

   1 /*
   2  * Copyright (c) 2012,2015,2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  *          Andreas Hansson
  42  *          William Wang
  43  */
  44
  45 /**
  46  * @file
  47  * Port object definitions.
  48  */
  49 #include "mem/port.hh"
  50
  51 #include "base/trace.hh"
  52 #include "mem/mem_object.hh"
  53
  54 Port::Port(const std::string &_name, PortID _id)
  55     : portName(_name), id(_id)
  56 {
  57 }
  58
  59 Port::~Port()
  60 {
  61 }
  62
  63 BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
  64     : Port(name, _id), _baseSlavePort(NULL)
  65 {
  66 }
  67
  68 BaseMasterPort::~BaseMasterPort()
  69 {
  70 }
  71
  72 BaseSlavePort&
  73 BaseMasterPort::getSlavePort() const
  74 {
  75     if (_baseSlavePort == NULL)
  76         panic("Cannot getSlavePort on master port %s that is not connected\n",
  77               name());
  78
  79     return *_baseSlavePort;
  80 }
  81
  82 bool
  83 BaseMasterPort::isConnected() const
  84 {
  85     return _baseSlavePort != NULL;
  86 }
  87
  88 BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
  89     : Port(name, _id), _baseMasterPort(NULL)
  90 {
  91 }
  92
  93 BaseSlavePort::~BaseSlavePort()
  94 {
  95 }
  96
  97 BaseMasterPort&
  98 BaseSlavePort::getMasterPort() const
  99 {
 100     if (_baseMasterPort == NULL)
 101         panic("Cannot getMasterPort on slave port %s that is not connected\n",
 102               name());
 103
 104     return *_baseMasterPort;
 105 }
 106
 107 bool
 108 BaseSlavePort::isConnected() const
 109 {
 110     return _baseMasterPort != NULL;
 111 }
 112
 113 /**
 114  * Master port
 115  */
 116 MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
 117     : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
 118 {
 119 }
 120
 121 MasterPort::~MasterPort()
 122 {
 123 }
 124
 125 void
 126 MasterPort::bind(BaseSlavePort& slave_port)
 127 {
 128     // bind on the level of the base ports
 129     _baseSlavePort = &slave_port;
 130
 131     // also attempt to base the slave to the appropriate type
 132     SlavePort* cast_slave_port = dynamic_cast<SlavePort*>(&slave_port);
 133
 134     // if this port is compatible, then proceed with the binding
 135     if (cast_slave_port != NULL) {
 136         // master port keeps track of the slave port
 137         _slavePort = cast_slave_port;
 138         // slave port also keeps track of master port
 139         _slavePort->bind(*this);
 140     } else {
 141         fatal("Master port %s cannot bind to %s\n", name(),
 142               slave_port.name());
 143     }
 144 }
 145
 146 void
 147 MasterPort::unbind()
 148 {
 149     if (_slavePort == NULL)
 150         panic("Attempting to unbind master port %s that is not connected\n",
 151               name());
 152     _slavePort->unbind();
 153     _slavePort = NULL;
 154     _baseSlavePort = NULL;
 155 }
 156
 157 AddrRangeList
 158 MasterPort::getAddrRanges() const
 159 {
 160     return _slavePort->getAddrRanges();
 161 }
 162
 163 Tick
 164 MasterPort::sendAtomic(PacketPtr pkt)
 165 {
 166     assert(pkt->isRequest());
 167     return _slavePort->recvAtomic(pkt);
 168 }
 169
 170 void
 171 MasterPort::sendFunctional(PacketPtr pkt)
 172 {
 173     assert(pkt->isRequest());
 174     return _slavePort->recvFunctional(pkt);
 175 }
 176
 177 bool
 178 MasterPort::sendTimingReq(PacketPtr pkt)
 179 {
 180     assert(pkt->isRequest());
 181     return _slavePort->recvTimingReq(pkt);
 182 }
 183
 184 bool
 185 MasterPort::tryTiming(PacketPtr pkt) const
 186 {
 187   assert(pkt->isRequest());
 188   return _slavePort->tryTiming(pkt);
 189 }
 190
 191 bool
 192 MasterPort::sendTimingSnoopResp(PacketPtr pkt)
 193 {
 194     assert(pkt->isResponse());
 195     return _slavePort->recvTimingSnoopResp(pkt);
 196 }
 197
 198 void
 199 MasterPort::sendRetryResp()
 200 {
 201     _slavePort->recvRespRetry();
 202 }
 203
 204 void
 205 MasterPort::printAddr(Addr a)
 206 {
 207     auto req = std::make_shared<Request>(
 208         a, 1, 0, Request::funcMasterId);
 209
 210     Packet pkt(req, MemCmd::PrintReq);
 211     Packet::PrintReqState prs(std::cerr);
 212     pkt.senderState = &prs;
 213
 214     sendFunctional(&pkt);
 215 }
 216
 217 /**
 218  * Slave port
 219  */
 220 SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
 221     : BaseSlavePort(name, id), _masterPort(NULL), owner(*_owner)
 222 {
 223 }
 224
 225 SlavePort::~SlavePort()
 226 {
 227 }
 228
 229 void
 230 SlavePort::unbind()
 231 {
 232     _baseMasterPort = NULL;
 233     _masterPort = NULL;
 234 }
 235
 236 void
 237 SlavePort::bind(MasterPort& master_port)
 238 {
 239     _baseMasterPort = &master_port;
 240     _masterPort = &master_port;
 241 }
 242
 243 Tick
 244 SlavePort::sendAtomicSnoop(PacketPtr pkt)
 245 {
 246     assert(pkt->isRequest());
 247     return _masterPort->recvAtomicSnoop(pkt);
 248 }
 249
 250 void
 251 SlavePort::sendFunctionalSnoop(PacketPtr pkt)
 252 {
 253     assert(pkt->isRequest());
 254     return _masterPort->recvFunctionalSnoop(pkt);
 255 }
 256
 257 bool
 258 SlavePort::sendTimingResp(PacketPtr pkt)
 259 {
 260     assert(pkt->isResponse());
 261     return _masterPort->recvTimingResp(pkt);
 262 }
 263
 264 void
 265 SlavePort::sendTimingSnoopReq(PacketPtr pkt)
 266 {
 267     assert(pkt->isRequest());
 268     _masterPort->recvTimingSnoopReq(pkt);
 269 }
 270
 271 void
 272 SlavePort::sendRetryReq()
 273 {
 274     _masterPort->recvReqRetry();
 275 }
 276
 277 void
 278 SlavePort::sendRetrySnoopResp()
 279 {
 280     _masterPort->recvRetrySnoopResp();
 281 }