2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
47 * Port object definitions.
49 #include "base/trace.hh"
50 #include "mem/mem_object.hh"
51 #include "mem/port.hh"
53 Port::Port(const std::string
&_name
, MemObject
& _owner
, PortID _id
)
54 : portName(_name
), id(_id
), owner(_owner
)
62 BaseMasterPort::BaseMasterPort(const std::string
& name
, MemObject
* owner
,
64 : Port(name
, *owner
, _id
), _baseSlavePort(NULL
)
68 BaseMasterPort::~BaseMasterPort()
73 BaseMasterPort::getSlavePort() const
75 if(_baseSlavePort
== NULL
)
76 panic("Cannot getSlavePort on master port %s that is not connected\n",
79 return *_baseSlavePort
;
83 BaseMasterPort::isConnected() const
85 return _baseSlavePort
!= NULL
;
88 BaseSlavePort::BaseSlavePort(const std::string
& name
, MemObject
* owner
,
90 : Port(name
, *owner
, _id
), _baseMasterPort(NULL
)
94 BaseSlavePort::~BaseSlavePort()
99 BaseSlavePort::getMasterPort() const
101 if(_baseMasterPort
== NULL
)
102 panic("Cannot getMasterPort on slave port %s that is not connected\n",
105 return *_baseMasterPort
;
109 BaseSlavePort::isConnected() const
111 return _baseMasterPort
!= NULL
;
117 MasterPort::MasterPort(const std::string
& name
, MemObject
* owner
, PortID _id
)
118 : BaseMasterPort(name
, owner
, _id
), _slavePort(NULL
)
122 MasterPort::~MasterPort()
127 MasterPort::bind(BaseSlavePort
& slave_port
)
129 // bind on the level of the base ports
130 _baseSlavePort
= &slave_port
;
132 // also attempt to base the slave to the appropriate type
133 SlavePort
* cast_slave_port
= dynamic_cast<SlavePort
*>(&slave_port
);
135 // if this port is compatible, then proceed with the binding
136 if (cast_slave_port
!= NULL
) {
137 // master port keeps track of the slave port
138 _slavePort
= cast_slave_port
;
139 // slave port also keeps track of master port
140 _slavePort
->bind(*this);
142 fatal("Master port %s cannot bind to %s\n", name(),
150 if (_slavePort
== NULL
)
151 panic("Attempting to unbind master port %s that is not connected\n",
153 _slavePort
->unbind();
155 _baseSlavePort
= NULL
;
159 MasterPort::getAddrRanges() const
161 return _slavePort
->getAddrRanges();
165 MasterPort::sendAtomic(PacketPtr pkt
)
167 assert(pkt
->isRequest());
168 return _slavePort
->recvAtomic(pkt
);
172 MasterPort::sendFunctional(PacketPtr pkt
)
174 assert(pkt
->isRequest());
175 return _slavePort
->recvFunctional(pkt
);
179 MasterPort::sendTimingReq(PacketPtr pkt
)
181 assert(pkt
->isRequest());
182 return _slavePort
->recvTimingReq(pkt
);
186 MasterPort::sendTimingSnoopResp(PacketPtr pkt
)
188 assert(pkt
->isResponse());
189 return _slavePort
->recvTimingSnoopResp(pkt
);
193 MasterPort::sendRetry()
195 _slavePort
->recvRetry();
199 MasterPort::printAddr(Addr a
)
201 Request
req(a
, 1, 0, Request::funcMasterId
);
202 Packet
pkt(&req
, MemCmd::PrintReq
);
203 Packet::PrintReqState
prs(std::cerr
);
204 pkt
.senderState
= &prs
;
206 sendFunctional(&pkt
);
212 SlavePort::SlavePort(const std::string
& name
, MemObject
* owner
, PortID id
)
213 : BaseSlavePort(name
, owner
, id
), _masterPort(NULL
)
217 SlavePort::~SlavePort()
224 _baseMasterPort
= NULL
;
229 SlavePort::bind(MasterPort
& master_port
)
231 _baseMasterPort
= &master_port
;
232 _masterPort
= &master_port
;
236 SlavePort::sendAtomicSnoop(PacketPtr pkt
)
238 assert(pkt
->isRequest());
239 return _masterPort
->recvAtomicSnoop(pkt
);
243 SlavePort::sendFunctionalSnoop(PacketPtr pkt
)
245 assert(pkt
->isRequest());
246 return _masterPort
->recvFunctionalSnoop(pkt
);
250 SlavePort::sendTimingResp(PacketPtr pkt
)
252 assert(pkt
->isResponse());
253 return _masterPort
->recvTimingResp(pkt
);
257 SlavePort::sendTimingSnoopReq(PacketPtr pkt
)
259 assert(pkt
->isRequest());
260 _masterPort
->recvTimingSnoopReq(pkt
);
264 SlavePort::sendRetry()
266 _masterPort
->recvRetry();