src/mem/protocol/MESI_CMP_directory-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 machine(L1Cache, "MSI Directory L1 Cache CMP")
  31  : Sequencer * sequencer,
  32    CacheMemory * L1IcacheMemory,
  33    CacheMemory * L1DcacheMemory,
  34    int l2_select_num_bits,
  35    int l1_request_latency = 2,
  36    int l1_response_latency = 2,
  37    int to_l2_latency = 1
  38 {
  39   // NODE L1 CACHE
  40   // From this node's L1 cache TO the network
  41   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  42   MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
  43   // a local L1 -> this L2 bank
  44   MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false";
  45   MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false";
  46
  47
  48   // To this node's L1 cache FROM the network
  49   // a L2 bank -> this L1
  50   MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
  51   // a L2 bank -> this L1
  52   MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false";
  53
  54   // STATES
  55   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  56     // Base states
  57     NP, desc="Not present in either cache";
  58     I, desc="a L1 cache entry Idle";
  59     S, desc="a L1 cache entry Shared";
  60     E, desc="a L1 cache entry Exclusive";
  61     M, desc="a L1 cache entry Modified", format="!b";
  62
  63     // Transient States
  64     IS, desc="L1 idle, issued GETS, have not seen response yet";
  65     IM, desc="L1 idle, issued GETX, have not seen response yet";
  66     SM, desc="L1 idle, issued GETX, have not seen response yet";
  67     IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
  68
  69     M_I, desc="L1 replacing, waiting for ACK";
  70     E_I, desc="L1 replacing, waiting for ACK";
  71     SINK_WB_ACK, desc="This is to sink WB_Acks from L2";
  72
  73   }
  74
  75   // EVENTS
  76   enumeration(Event, desc="Cache events") {
  77     // L1 events
  78     Load,            desc="Load request from the home processor";
  79     Ifetch,          desc="I-fetch request from the home processor";
  80     Store,           desc="Store request from the home processor";
  81
  82     Inv,           desc="Invalidate request from L2 bank";
  83
  84     // internal generated request
  85     L1_Replacement,  desc="L1 Replacement", format="!r";
  86
  87     // other requests
  88     Fwd_GETX,   desc="GETX from other processor";
  89     Fwd_GETS,   desc="GETS from other processor";
  90     Fwd_GET_INSTR,   desc="GET_INSTR from other processor";
  91
  92     Data,       desc="Data for processor";
  93     Data_Exclusive,       desc="Data for processor";
  94     DataS_fromL1,       desc="data for GETS request, need to unblock directory";
  95     Data_all_Acks,       desc="Data for processor, all acks";
  96
  97     Ack,        desc="Ack for processor";
  98     Ack_all,      desc="Last ack for processor";
  99
 100     WB_Ack,        desc="Ack for replacement";
 101   }
 102
 103   // TYPES
 104
 105   // CacheEntry
 106   structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
 107     State CacheState,        desc="cache state";
 108     DataBlock DataBlk,       desc="data for the block";
 109     bool Dirty, default="false",   desc="data is dirty";
 110   }
 111
 112   // TBE fields
 113   structure(TBE, desc="...") {
 114     Address Address,              desc="Physical address for this TBE";
 115     State TBEState,        desc="Transient state";
 116     DataBlock DataBlk,                desc="Buffer for the data block";
 117     bool Dirty, default="false",   desc="data is dirty";
 118     bool isPrefetch,       desc="Set if this was caused by a prefetch";
 119     int pendingAcks, default="0", desc="number of pending acks";
 120   }
 121
 122   external_type(TBETable) {
 123     TBE lookup(Address);
 124     void allocate(Address);
 125     void deallocate(Address);
 126     bool isPresent(Address);
 127   }
 128
 129   TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
 130
 131   MessageBuffer mandatoryQueue, ordered="false";
 132
 133   int cache_state_to_int(State state);
 134   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 135
 136   void set_cache_entry(AbstractCacheEntry a);
 137   void unset_cache_entry();
 138   void set_tbe(TBE a);
 139   void unset_tbe();
 140
 141   // inclusive cache returns L1 entries only
 142   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 143     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
 144     if(is_valid(L1Dcache_entry)) {
 145       return L1Dcache_entry;
 146     }
 147
 148     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
 149     return L1Icache_entry;
 150   }
 151
 152   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 153     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
 154     return L1Dcache_entry;
 155   }
 156
 157   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 158     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
 159     return L1Icache_entry;
 160   }
 161
 162   State getState(TBE tbe, Entry cache_entry, Address addr) {
 163     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 164
 165     if(is_valid(tbe)) {
 166       return tbe.TBEState;
 167     } else if (is_valid(cache_entry)) {
 168       return cache_entry.CacheState;
 169     }
 170     return State:NP;
 171   }
 172
 173   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 174     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 175
 176     // MUST CHANGE
 177     if(is_valid(tbe)) {
 178       tbe.TBEState := state;
 179     }
 180
 181     if (is_valid(cache_entry)) {
 182       cache_entry.CacheState := state;
 183
 184       // Set permission
 185       if (state == State:I) {
 186         cache_entry.changePermission(AccessPermission:Invalid);
 187       } else if (state == State:S || state == State:E) {
 188         cache_entry.changePermission(AccessPermission:Read_Only);
 189       } else if (state == State:M) {
 190         cache_entry.changePermission(AccessPermission:Read_Write);
 191       } else {
 192         cache_entry.changePermission(AccessPermission:Busy);
 193       }
 194     }
 195   }
 196
 197   Event mandatory_request_type_to_event(CacheRequestType type) {
 198     if (type == CacheRequestType:LD) {
 199       return Event:Load;
 200     } else if (type == CacheRequestType:IFETCH) {
 201       return Event:Ifetch;
 202     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 203       return Event:Store;
 204     } else {
 205       error("Invalid CacheRequestType");
 206     }
 207   }
 208
 209   int getPendingAcks(TBE tbe) {
 210     return tbe.pendingAcks;
 211   }
 212
 213   out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
 214   out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
 215   out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
 216
 217   // Response IntraChip L1 Network - response msg to this L1 cache
 218   in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
 219     if (responseIntraChipL1Network_in.isReady()) {
 220       peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
 221         assert(in_msg.Destination.isElement(machineID));
 222
 223         Entry cache_entry := getCacheEntry(in_msg.Address);
 224         TBE tbe := L1_TBEs[in_msg.Address];
 225
 226         if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 227           trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
 228         } else if(in_msg.Type == CoherenceResponseType:DATA) {
 229           if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
 230                getState(tbe, cache_entry, in_msg.Address) == State:IS_I) &&
 231               machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 232
 233               trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
 234
 235           } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
 236             trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
 237           } else {
 238             trigger(Event:Data, in_msg.Address, cache_entry, tbe);
 239           }
 240         } else if (in_msg.Type == CoherenceResponseType:ACK) {
 241           if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
 242             trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
 243           } else {
 244             trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
 245           }
 246         } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
 247           trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
 248         } else {
 249           error("Invalid L1 response type");
 250         }
 251       }
 252     }
 253   }
 254
 255   // Request InterChip network - request from this L1 cache to the shared L2
 256   in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
 257     if(requestIntraChipL1Network_in.isReady()) {
 258       peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
 259         assert(in_msg.Destination.isElement(machineID));
 260
 261         Entry cache_entry := getCacheEntry(in_msg.Address);
 262         TBE tbe := L1_TBEs[in_msg.Address];
 263
 264         if (in_msg.Type == CoherenceRequestType:INV) {
 265           trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
 266         } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
 267           // upgrade transforms to GETX due to race
 268           trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
 269         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 270           trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
 271         } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
 272           trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
 273         } else {
 274           error("Invalid forwarded request type");
 275         }
 276       }
 277     }
 278   }
 279
 280   // Mandatory Queue betweens Node's CPU and it's L1 caches
 281   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 282     if (mandatoryQueue_in.isReady()) {
 283       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 284
 285         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 286
 287         if (in_msg.Type == CacheRequestType:IFETCH) {
 288           // ** INSTRUCTION ACCESS ***
 289
 290           // Check to see if it is in the OTHER L1
 291           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 292           if (is_valid(L1Dcache_entry)) {
 293             // The block is in the wrong L1, put the request on the queue to the shared L2
 294             trigger(Event:L1_Replacement, in_msg.LineAddress,
 295                     L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
 296           }
 297
 298           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 299           if (is_valid(L1Icache_entry)) {
 300             // The tag matches for the L1, so the L1 asks the L2 for it.
 301             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 302                     L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
 303           } else {
 304             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 305               // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
 306               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 307                       L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
 308             } else {
 309               // No room in the L1, so we need to make room in the L1
 310               trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 311                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 312                       L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 313             }
 314           }
 315         } else {
 316           // *** DATA ACCESS ***
 317           // Check to see if it is in the OTHER L1
 318           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 319           if (is_valid(L1Icache_entry)) {
 320             // The block is in the wrong L1, put the request on the queue to the shared L2
 321             trigger(Event:L1_Replacement, in_msg.LineAddress,
 322                     L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
 323           }
 324
 325           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 326           if (is_valid(L1Dcache_entry)) {
 327             // The tag matches for the L1, so the L1 ask the L2 for it
 328             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 329                     L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
 330           } else {
 331             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 332               // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
 333               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 334                       L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
 335             } else {
 336               // No room in the L1, so we need to make room in the L1
 337               trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 338                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 339                       L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 340             }
 341           }
 342         }
 343       }
 344     }
 345   }
 346
 347   // ACTIONS
 348   action(a_issueGETS, "a", desc="Issue GETS") {
 349     peek(mandatoryQueue_in, CacheMsg) {
 350       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
 351         out_msg.Address := address;
 352         out_msg.Type := CoherenceRequestType:GETS;
 353         out_msg.Requestor := machineID;
 354         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 355                                                   l2_select_low_bit, l2_select_num_bits));
 356         DPRINTF(RubySlicc, "address: %s, destination: %s\n",
 357                 address, out_msg.Destination);
 358         out_msg.MessageSize := MessageSizeType:Control;
 359         out_msg.Prefetch := in_msg.Prefetch;
 360         out_msg.AccessMode := in_msg.AccessMode;
 361       }
 362     }
 363   }
 364
 365   action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
 366     peek(mandatoryQueue_in, CacheMsg) {
 367       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
 368         out_msg.Address := address;
 369         out_msg.Type := CoherenceRequestType:GET_INSTR;
 370         out_msg.Requestor := machineID;
 371         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 372                                                   l2_select_low_bit, l2_select_num_bits));
 373         DPRINTF(RubySlicc, "address: %s, destination: %s\n",
 374                 address, out_msg.Destination);
 375         out_msg.MessageSize := MessageSizeType:Control;
 376         out_msg.Prefetch := in_msg.Prefetch;
 377         out_msg.AccessMode := in_msg.AccessMode;
 378       }
 379     }
 380   }
 381
 382
 383   action(b_issueGETX, "b", desc="Issue GETX") {
 384     peek(mandatoryQueue_in, CacheMsg) {
 385       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
 386         out_msg.Address := address;
 387         out_msg.Type := CoherenceRequestType:GETX;
 388         out_msg.Requestor := machineID;
 389         DPRINTF(RubySlicc, "%s\n", machineID);
 390         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 391                                                   l2_select_low_bit, l2_select_num_bits));
 392         DPRINTF(RubySlicc, "address: %s, destination: %s\n",
 393                 address, out_msg.Destination);
 394         out_msg.MessageSize := MessageSizeType:Control;
 395         out_msg.Prefetch := in_msg.Prefetch;
 396         out_msg.AccessMode := in_msg.AccessMode;
 397       }
 398     }
 399   }
 400
 401   action(c_issueUPGRADE, "c", desc="Issue GETX") {
 402     peek(mandatoryQueue_in, CacheMsg) {
 403       enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
 404         out_msg.Address := address;
 405         out_msg.Type := CoherenceRequestType:UPGRADE;
 406         out_msg.Requestor := machineID;
 407         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 408                                                   l2_select_low_bit, l2_select_num_bits));
 409         DPRINTF(RubySlicc, "address: %s, destination: %s\n",
 410                 address, out_msg.Destination);
 411         out_msg.MessageSize := MessageSizeType:Control;
 412         out_msg.Prefetch := in_msg.Prefetch;
 413         out_msg.AccessMode := in_msg.AccessMode;
 414       }
 415     }
 416   }
 417
 418   action(d_sendDataToRequestor, "d", desc="send data to requestor") {
 419     peek(requestIntraChipL1Network_in, RequestMsg) {
 420       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 421         assert(is_valid(cache_entry));
 422         out_msg.Address := address;
 423         out_msg.Type := CoherenceResponseType:DATA;
 424         out_msg.DataBlk := cache_entry.DataBlk;
 425         out_msg.Dirty := cache_entry.Dirty;
 426         out_msg.Sender := machineID;
 427         out_msg.Destination.add(in_msg.Requestor);
 428         out_msg.MessageSize := MessageSizeType:Response_Data;
 429       }
 430     }
 431   }
 432
 433   action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
 434     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 435       assert(is_valid(cache_entry));
 436       out_msg.Address := address;
 437       out_msg.Type := CoherenceResponseType:DATA;
 438       out_msg.DataBlk := cache_entry.DataBlk;
 439       out_msg.Dirty := cache_entry.Dirty;
 440       out_msg.Sender := machineID;
 441       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 442                                                   l2_select_low_bit, l2_select_num_bits));
 443       out_msg.MessageSize := MessageSizeType:Response_Data;
 444     }
 445   }
 446
 447   action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
 448     peek(requestIntraChipL1Network_in, RequestMsg) {
 449       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 450         assert(is_valid(tbe));
 451         out_msg.Address := address;
 452         out_msg.Type := CoherenceResponseType:DATA;
 453         out_msg.DataBlk := tbe.DataBlk;
 454         out_msg.Dirty := tbe.Dirty;
 455         out_msg.Sender := machineID;
 456         out_msg.Destination.add(in_msg.Requestor);
 457         out_msg.MessageSize := MessageSizeType:Response_Data;
 458       }
 459     }
 460   }
 461
 462   action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
 463     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 464       assert(is_valid(tbe));
 465       out_msg.Address := address;
 466       out_msg.Type := CoherenceResponseType:DATA;
 467       out_msg.DataBlk := tbe.DataBlk;
 468       out_msg.Dirty := tbe.Dirty;
 469       out_msg.Sender := machineID;
 470       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 471                                                   l2_select_low_bit, l2_select_num_bits));
 472       out_msg.MessageSize := MessageSizeType:Response_Data;
 473     }
 474   }
 475
 476   action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
 477     peek(requestIntraChipL1Network_in, RequestMsg) {
 478       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 479         out_msg.Address := address;
 480         out_msg.Type := CoherenceResponseType:ACK;
 481         out_msg.Sender := machineID;
 482         out_msg.Destination.add(in_msg.Requestor);
 483         out_msg.MessageSize := MessageSizeType:Response_Control;
 484       }
 485     }
 486   }
 487
 488   action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
 489     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 490       assert(is_valid(cache_entry));
 491       out_msg.Address := address;
 492       out_msg.Type := CoherenceResponseType:DATA;
 493       out_msg.DataBlk := cache_entry.DataBlk;
 494       out_msg.Dirty := cache_entry.Dirty;
 495       out_msg.Sender := machineID;
 496       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 497                                                   l2_select_low_bit, l2_select_num_bits));
 498       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 499     }
 500   }
 501
 502   action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
 503     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 504       assert(is_valid(tbe));
 505       out_msg.Address := address;
 506       out_msg.Type := CoherenceResponseType:DATA;
 507       out_msg.DataBlk := tbe.DataBlk;
 508       out_msg.Dirty := tbe.Dirty;
 509       out_msg.Sender := machineID;
 510       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 511                                                   l2_select_low_bit, l2_select_num_bits));
 512       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 513     }
 514   }
 515
 516   action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
 517     peek(requestIntraChipL1Network_in, RequestMsg) {
 518       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
 519         out_msg.Address := address;
 520         out_msg.Type := CoherenceResponseType:ACK;
 521         out_msg.Sender := machineID;
 522         out_msg.Destination.add(in_msg.Requestor);
 523         out_msg.MessageSize := MessageSizeType:Response_Control;
 524         out_msg.AckCount := 1;
 525       }
 526     }
 527   }
 528
 529
 530   action(g_issuePUTX, "g", desc="send data to the L2 cache") {
 531     enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
 532       assert(is_valid(cache_entry));
 533       out_msg.Address := address;
 534       out_msg.Type := CoherenceRequestType:PUTX;
 535       out_msg.DataBlk := cache_entry.DataBlk;
 536       out_msg.Dirty := cache_entry.Dirty;
 537       out_msg.Requestor:= machineID;
 538       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 539                                                   l2_select_low_bit, l2_select_num_bits));
 540       if (cache_entry.Dirty) {
 541         out_msg.MessageSize := MessageSizeType:Writeback_Data;
 542       } else {
 543         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 544       }
 545     }
 546   }
 547
 548   action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
 549     enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
 550       out_msg.Address := address;
 551       out_msg.Type := CoherenceResponseType:UNBLOCK;
 552       out_msg.Sender := machineID;
 553       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 554                                                   l2_select_low_bit, l2_select_num_bits));
 555       out_msg.MessageSize := MessageSizeType:Response_Control;
 556       DPRINTF(RubySlicc, "%s\n", address);
 557
 558     }
 559   }
 560
 561   action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
 562     enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
 563       out_msg.Address := address;
 564       out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
 565       out_msg.Sender := machineID;
 566       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 567                                                   l2_select_low_bit, l2_select_num_bits));
 568       out_msg.MessageSize := MessageSizeType:Response_Control;
 569       DPRINTF(RubySlicc, "%s\n", address);
 570
 571     }
 572   }
 573
 574   action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
 575     assert(is_valid(cache_entry));
 576     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 577     sequencer.readCallback(address, cache_entry.DataBlk);
 578   }
 579
 580   action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
 581     assert(is_valid(cache_entry));
 582     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 583     sequencer.writeCallback(address, cache_entry.DataBlk);
 584     cache_entry.Dirty := true;
 585   }
 586
 587   action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
 588     check_allocate(L1_TBEs);
 589     assert(is_valid(cache_entry));
 590     L1_TBEs.allocate(address);
 591     set_tbe(L1_TBEs[address]);
 592     tbe.isPrefetch := false;
 593     tbe.Dirty := cache_entry.Dirty;
 594     tbe.DataBlk := cache_entry.DataBlk;
 595   }
 596
 597   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 598     mandatoryQueue_in.dequeue();
 599   }
 600
 601   action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
 602     profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
 603   }
 604
 605   action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
 606     profileMsgDelay(3, responseIntraChipL1Network_in.dequeue_getDelayCycles());
 607   }
 608
 609   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 610     L1_TBEs.deallocate(address);
 611     unset_tbe();
 612   }
 613
 614   action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
 615     peek(responseIntraChipL1Network_in, ResponseMsg) {
 616       assert(is_valid(cache_entry));
 617       cache_entry.DataBlk := in_msg.DataBlk;
 618       cache_entry.Dirty := in_msg.Dirty;
 619     }
 620   }
 621
 622   action(q_updateAckCount, "q", desc="Update ack count") {
 623     peek(responseIntraChipL1Network_in, ResponseMsg) {
 624       assert(is_valid(tbe));
 625       tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
 626       APPEND_TRANSITION_COMMENT(in_msg.AckCount);
 627       APPEND_TRANSITION_COMMENT(" p: ");
 628       APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
 629     }
 630   }
 631
 632   action(z_stall, "z", desc="Stall") {
 633   }
 634
 635   action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 636     if (L1DcacheMemory.isTagPresent(address)) {
 637       L1DcacheMemory.deallocate(address);
 638     } else {
 639       L1IcacheMemory.deallocate(address);
 640     }
 641     unset_cache_entry();
 642   }
 643
 644   action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
 645     if (is_invalid(cache_entry)) {
 646       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
 647     }
 648   }
 649
 650   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
 651     if (is_invalid(cache_entry)) {
 652       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
 653     }
 654   }
 655
 656   action(zz_recycleRequestQueue, "zz", desc="recycle L1 request queue") {
 657     requestIntraChipL1Network_in.recycle();
 658   }
 659
 660   action(z_recycleMandatoryQueue, "\z", desc="recycle L1 request queue") {
 661     mandatoryQueue_in.recycle();
 662   }
 663
 664
 665   //*****************************************************
 666   // TRANSITIONS
 667   //*****************************************************
 668
 669   // Transitions for Load/Store/Replacement/WriteBack from transient states
 670   transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
 671     z_recycleMandatoryQueue;
 672   }
 673
 674   // Transitions from Idle
 675   transition({NP,I}, L1_Replacement) {
 676     ff_deallocateL1CacheBlock;
 677   }
 678
 679   transition({NP,I}, Load, IS) {
 680     oo_allocateL1DCacheBlock;
 681     i_allocateTBE;
 682     a_issueGETS;
 683     k_popMandatoryQueue;
 684   }
 685
 686   transition({NP,I}, Ifetch, IS) {
 687     pp_allocateL1ICacheBlock;
 688     i_allocateTBE;
 689     ai_issueGETINSTR;
 690     k_popMandatoryQueue;
 691   }
 692
 693   transition({NP,I}, Store, IM) {
 694     oo_allocateL1DCacheBlock;
 695     i_allocateTBE;
 696     b_issueGETX;
 697     k_popMandatoryQueue;
 698   }
 699
 700   transition({NP, I}, Inv) {
 701     fi_sendInvAck;
 702     l_popRequestQueue;
 703   }
 704
 705   // Transitions from Shared
 706   transition(S, {Load,Ifetch}) {
 707     h_load_hit;
 708     k_popMandatoryQueue;
 709   }
 710
 711   transition(S, Store, SM) {
 712     i_allocateTBE;
 713     c_issueUPGRADE;
 714     k_popMandatoryQueue;
 715   }
 716
 717   transition(S, L1_Replacement, I) {
 718     ff_deallocateL1CacheBlock;
 719   }
 720
 721   transition(S, Inv, I) {
 722     fi_sendInvAck;
 723     l_popRequestQueue;
 724   }
 725
 726   // Transitions from Exclusive
 727
 728   transition(E, {Load, Ifetch}) {
 729     h_load_hit;
 730     k_popMandatoryQueue;
 731   }
 732
 733   transition(E, Store, M) {
 734     hh_store_hit;
 735     k_popMandatoryQueue;
 736   }
 737
 738   transition(E, L1_Replacement, M_I) {
 739     // silent E replacement??
 740     i_allocateTBE;
 741     g_issuePUTX;   // send data, but hold in case forwarded request
 742     ff_deallocateL1CacheBlock;
 743   }
 744
 745   transition(E, Inv, I) {
 746     // don't send data
 747     fi_sendInvAck;
 748     l_popRequestQueue;
 749   }
 750
 751   transition(E, Fwd_GETX, I) {
 752     d_sendDataToRequestor;
 753     l_popRequestQueue;
 754   }
 755
 756   transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
 757     d_sendDataToRequestor;
 758     d2_sendDataToL2;
 759     l_popRequestQueue;
 760   }
 761
 762   // Transitions from Modified
 763   transition(M, {Load, Ifetch}) {
 764     h_load_hit;
 765     k_popMandatoryQueue;
 766   }
 767
 768   transition(M, Store) {
 769     hh_store_hit;
 770     k_popMandatoryQueue;
 771   }
 772
 773   transition(M, L1_Replacement, M_I) {
 774     i_allocateTBE;
 775     g_issuePUTX;   // send data, but hold in case forwarded request
 776     ff_deallocateL1CacheBlock;
 777   }
 778
 779   transition(M_I, WB_Ack, I) {
 780     s_deallocateTBE;
 781     o_popIncomingResponseQueue;
 782   }
 783
 784   transition(M, Inv, I) {
 785     f_sendDataToL2;
 786     l_popRequestQueue;
 787   }
 788
 789   transition(M_I, Inv, SINK_WB_ACK) {
 790     ft_sendDataToL2_fromTBE;
 791     l_popRequestQueue;
 792   }
 793
 794   transition(M, Fwd_GETX, I) {
 795     d_sendDataToRequestor;
 796     l_popRequestQueue;
 797   }
 798
 799   transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
 800     d_sendDataToRequestor;
 801     d2_sendDataToL2;
 802     l_popRequestQueue;
 803   }
 804
 805   transition(M_I, Fwd_GETX, SINK_WB_ACK) {
 806     dt_sendDataToRequestor_fromTBE;
 807     l_popRequestQueue;
 808   }
 809
 810   transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, SINK_WB_ACK) {
 811     dt_sendDataToRequestor_fromTBE;
 812     d2t_sendDataToL2_fromTBE;
 813     l_popRequestQueue;
 814   }
 815
 816   // Transitions from IS
 817   transition({IS, IS_I}, Inv, IS_I) {
 818     fi_sendInvAck;
 819     l_popRequestQueue;
 820   }
 821
 822   transition(IS, Data_all_Acks, S) {
 823     u_writeDataToL1Cache;
 824     h_load_hit;
 825     s_deallocateTBE;
 826     o_popIncomingResponseQueue;
 827   }
 828
 829   transition(IS_I, Data_all_Acks, I) {
 830     u_writeDataToL1Cache;
 831     h_load_hit;
 832     s_deallocateTBE;
 833     o_popIncomingResponseQueue;
 834   }
 835
 836
 837   transition(IS, DataS_fromL1, S) {
 838     u_writeDataToL1Cache;
 839     j_sendUnblock;
 840     h_load_hit;
 841     s_deallocateTBE;
 842     o_popIncomingResponseQueue;
 843   }
 844
 845   transition(IS_I, DataS_fromL1, I) {
 846     u_writeDataToL1Cache;
 847     j_sendUnblock;
 848     h_load_hit;
 849     s_deallocateTBE;
 850     o_popIncomingResponseQueue;
 851   }
 852
 853   // directory is blocked when sending exclusive data
 854   transition(IS_I, Data_Exclusive, E) {
 855     u_writeDataToL1Cache;
 856     h_load_hit;
 857     jj_sendExclusiveUnblock;
 858     s_deallocateTBE;
 859     o_popIncomingResponseQueue;
 860   }
 861
 862   transition(IS, Data_Exclusive, E) {
 863     u_writeDataToL1Cache;
 864     h_load_hit;
 865     jj_sendExclusiveUnblock;
 866     s_deallocateTBE;
 867     o_popIncomingResponseQueue;
 868   }
 869
 870   // Transitions from IM
 871   transition({IM, SM}, Inv, IM) {
 872     fi_sendInvAck;
 873     l_popRequestQueue;
 874   }
 875
 876   transition(IM, Data, SM) {
 877     u_writeDataToL1Cache;
 878     q_updateAckCount;
 879     o_popIncomingResponseQueue;
 880   }
 881
 882   transition(IM, Data_all_Acks, M) {
 883     u_writeDataToL1Cache;
 884     hh_store_hit;
 885     jj_sendExclusiveUnblock;
 886     s_deallocateTBE;
 887     o_popIncomingResponseQueue;
 888   }
 889
 890   // transitions from SM
 891   transition({SM, IM}, Ack) {
 892     q_updateAckCount;
 893     o_popIncomingResponseQueue;
 894   }
 895
 896   transition(SM, Ack_all, M) {
 897     jj_sendExclusiveUnblock;
 898     hh_store_hit;
 899     s_deallocateTBE;
 900     o_popIncomingResponseQueue;
 901   }
 902
 903   transition(SINK_WB_ACK, {Load, Store, Ifetch, L1_Replacement}){
 904       z_recycleMandatoryQueue;
 905
 906   }
 907
 908   transition(SINK_WB_ACK, Inv){
 909     fi_sendInvAck;
 910     l_popRequestQueue;
 911   }
 912
 913   transition(SINK_WB_ACK, WB_Ack){
 914     s_deallocateTBE;
 915     o_popIncomingResponseQueue;
 916   }
 917 }
 918
 919
 920