3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 machine(L1Cache, "MSI Directory L1 Cache CMP")
31 : Sequencer * sequencer,
32 CacheMemory * L1IcacheMemory,
33 CacheMemory * L1DcacheMemory,
34 int l2_select_num_bits,
35 int l1_request_latency = 2,
36 int l1_response_latency = 2,
40 // From this node's L1 cache TO the network
41 // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
42 MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
43 // a local L1 -> this L2 bank
44 MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false";
45 MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false";
48 // To this node's L1 cache FROM the network
49 // a L2 bank -> this L1
50 MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
51 // a L2 bank -> this L1
52 MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false";
55 enumeration(State, desc="Cache states", default="L1Cache_State_I") {
57 NP, desc="Not present in either cache";
58 I, desc="a L1 cache entry Idle";
59 S, desc="a L1 cache entry Shared";
60 E, desc="a L1 cache entry Exclusive";
61 M, desc="a L1 cache entry Modified", format="!b";
64 IS, desc="L1 idle, issued GETS, have not seen response yet";
65 IM, desc="L1 idle, issued GETX, have not seen response yet";
66 SM, desc="L1 idle, issued GETX, have not seen response yet";
67 IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
69 M_I, desc="L1 replacing, waiting for ACK";
70 E_I, desc="L1 replacing, waiting for ACK";
71 SINK_WB_ACK, desc="This is to sink WB_Acks from L2";
76 enumeration(Event, desc="Cache events") {
78 Load, desc="Load request from the home processor";
79 Ifetch, desc="I-fetch request from the home processor";
80 Store, desc="Store request from the home processor";
82 Inv, desc="Invalidate request from L2 bank";
84 // internal generated request
85 L1_Replacement, desc="L1 Replacement", format="!r";
88 Fwd_GETX, desc="GETX from other processor";
89 Fwd_GETS, desc="GETS from other processor";
90 Fwd_GET_INSTR, desc="GET_INSTR from other processor";
92 Data, desc="Data for processor";
93 Data_Exclusive, desc="Data for processor";
94 DataS_fromL1, desc="data for GETS request, need to unblock directory";
95 Data_all_Acks, desc="Data for processor, all acks";
97 Ack, desc="Ack for processor";
98 Ack_all, desc="Last ack for processor";
100 WB_Ack, desc="Ack for replacement";
106 structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
107 State CacheState, desc="cache state";
108 DataBlock DataBlk, desc="data for the block";
109 bool Dirty, default="false", desc="data is dirty";
113 structure(TBE, desc="...") {
114 Address Address, desc="Physical address for this TBE";
115 State TBEState, desc="Transient state";
116 DataBlock DataBlk, desc="Buffer for the data block";
117 bool Dirty, default="false", desc="data is dirty";
118 bool isPrefetch, desc="Set if this was caused by a prefetch";
119 int pendingAcks, default="0", desc="number of pending acks";
122 external_type(TBETable) {
124 void allocate(Address);
125 void deallocate(Address);
126 bool isPresent(Address);
129 TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
131 MessageBuffer mandatoryQueue, ordered="false";
133 int cache_state_to_int(State state);
134 int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
136 void set_cache_entry(AbstractCacheEntry a);
137 void unset_cache_entry();
141 // inclusive cache returns L1 entries only
142 Entry getCacheEntry(Address addr), return_by_pointer="yes" {
143 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
144 if(is_valid(L1Dcache_entry)) {
145 return L1Dcache_entry;
148 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
149 return L1Icache_entry;
152 Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
153 Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
154 return L1Dcache_entry;
157 Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
158 Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
159 return L1Icache_entry;
162 State getState(TBE tbe, Entry cache_entry, Address addr) {
163 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
167 } else if (is_valid(cache_entry)) {
168 return cache_entry.CacheState;
173 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
174 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
178 tbe.TBEState := state;
181 if (is_valid(cache_entry)) {
182 cache_entry.CacheState := state;
185 if (state == State:I) {
186 cache_entry.changePermission(AccessPermission:Invalid);
187 } else if (state == State:S || state == State:E) {
188 cache_entry.changePermission(AccessPermission:Read_Only);
189 } else if (state == State:M) {
190 cache_entry.changePermission(AccessPermission:Read_Write);
192 cache_entry.changePermission(AccessPermission:Busy);
197 Event mandatory_request_type_to_event(CacheRequestType type) {
198 if (type == CacheRequestType:LD) {
200 } else if (type == CacheRequestType:IFETCH) {
202 } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
205 error("Invalid CacheRequestType");
209 int getPendingAcks(TBE tbe) {
210 return tbe.pendingAcks;
213 out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
214 out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
215 out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
217 // Response IntraChip L1 Network - response msg to this L1 cache
218 in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
219 if (responseIntraChipL1Network_in.isReady()) {
220 peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
221 assert(in_msg.Destination.isElement(machineID));
223 Entry cache_entry := getCacheEntry(in_msg.Address);
224 TBE tbe := L1_TBEs[in_msg.Address];
226 if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
227 trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
228 } else if(in_msg.Type == CoherenceResponseType:DATA) {
229 if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
230 getState(tbe, cache_entry, in_msg.Address) == State:IS_I) &&
231 machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
233 trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
235 } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
236 trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
238 trigger(Event:Data, in_msg.Address, cache_entry, tbe);
240 } else if (in_msg.Type == CoherenceResponseType:ACK) {
241 if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
242 trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
244 trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
246 } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
247 trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
249 error("Invalid L1 response type");
255 // Request InterChip network - request from this L1 cache to the shared L2
256 in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
257 if(requestIntraChipL1Network_in.isReady()) {
258 peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
259 assert(in_msg.Destination.isElement(machineID));
261 Entry cache_entry := getCacheEntry(in_msg.Address);
262 TBE tbe := L1_TBEs[in_msg.Address];
264 if (in_msg.Type == CoherenceRequestType:INV) {
265 trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
266 } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
267 // upgrade transforms to GETX due to race
268 trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
269 } else if (in_msg.Type == CoherenceRequestType:GETS) {
270 trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
271 } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
272 trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
274 error("Invalid forwarded request type");
280 // Mandatory Queue betweens Node's CPU and it's L1 caches
281 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
282 if (mandatoryQueue_in.isReady()) {
283 peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
285 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
287 if (in_msg.Type == CacheRequestType:IFETCH) {
288 // ** INSTRUCTION ACCESS ***
290 // Check to see if it is in the OTHER L1
291 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
292 if (is_valid(L1Dcache_entry)) {
293 // The block is in the wrong L1, put the request on the queue to the shared L2
294 trigger(Event:L1_Replacement, in_msg.LineAddress,
295 L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
298 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
299 if (is_valid(L1Icache_entry)) {
300 // The tag matches for the L1, so the L1 asks the L2 for it.
301 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
302 L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
304 if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
305 // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
306 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
307 L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
309 // No room in the L1, so we need to make room in the L1
310 trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress),
311 getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
312 L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
316 // *** DATA ACCESS ***
317 // Check to see if it is in the OTHER L1
318 Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
319 if (is_valid(L1Icache_entry)) {
320 // The block is in the wrong L1, put the request on the queue to the shared L2
321 trigger(Event:L1_Replacement, in_msg.LineAddress,
322 L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
325 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
326 if (is_valid(L1Dcache_entry)) {
327 // The tag matches for the L1, so the L1 ask the L2 for it
328 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
329 L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
331 if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
332 // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
333 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
334 L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
336 // No room in the L1, so we need to make room in the L1
337 trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress),
338 getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
339 L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
348 action(a_issueGETS, "a", desc="Issue GETS") {
349 peek(mandatoryQueue_in, CacheMsg) {
350 enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
351 out_msg.Address := address;
352 out_msg.Type := CoherenceRequestType:GETS;
353 out_msg.Requestor := machineID;
354 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
355 l2_select_low_bit, l2_select_num_bits));
356 DPRINTF(RubySlicc, "address: %s, destination: %s\n",
357 address, out_msg.Destination);
358 out_msg.MessageSize := MessageSizeType:Control;
359 out_msg.Prefetch := in_msg.Prefetch;
360 out_msg.AccessMode := in_msg.AccessMode;
365 action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
366 peek(mandatoryQueue_in, CacheMsg) {
367 enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
368 out_msg.Address := address;
369 out_msg.Type := CoherenceRequestType:GET_INSTR;
370 out_msg.Requestor := machineID;
371 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
372 l2_select_low_bit, l2_select_num_bits));
373 DPRINTF(RubySlicc, "address: %s, destination: %s\n",
374 address, out_msg.Destination);
375 out_msg.MessageSize := MessageSizeType:Control;
376 out_msg.Prefetch := in_msg.Prefetch;
377 out_msg.AccessMode := in_msg.AccessMode;
383 action(b_issueGETX, "b", desc="Issue GETX") {
384 peek(mandatoryQueue_in, CacheMsg) {
385 enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
386 out_msg.Address := address;
387 out_msg.Type := CoherenceRequestType:GETX;
388 out_msg.Requestor := machineID;
389 DPRINTF(RubySlicc, "%s\n", machineID);
390 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
391 l2_select_low_bit, l2_select_num_bits));
392 DPRINTF(RubySlicc, "address: %s, destination: %s\n",
393 address, out_msg.Destination);
394 out_msg.MessageSize := MessageSizeType:Control;
395 out_msg.Prefetch := in_msg.Prefetch;
396 out_msg.AccessMode := in_msg.AccessMode;
401 action(c_issueUPGRADE, "c", desc="Issue GETX") {
402 peek(mandatoryQueue_in, CacheMsg) {
403 enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
404 out_msg.Address := address;
405 out_msg.Type := CoherenceRequestType:UPGRADE;
406 out_msg.Requestor := machineID;
407 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
408 l2_select_low_bit, l2_select_num_bits));
409 DPRINTF(RubySlicc, "address: %s, destination: %s\n",
410 address, out_msg.Destination);
411 out_msg.MessageSize := MessageSizeType:Control;
412 out_msg.Prefetch := in_msg.Prefetch;
413 out_msg.AccessMode := in_msg.AccessMode;
418 action(d_sendDataToRequestor, "d", desc="send data to requestor") {
419 peek(requestIntraChipL1Network_in, RequestMsg) {
420 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
421 assert(is_valid(cache_entry));
422 out_msg.Address := address;
423 out_msg.Type := CoherenceResponseType:DATA;
424 out_msg.DataBlk := cache_entry.DataBlk;
425 out_msg.Dirty := cache_entry.Dirty;
426 out_msg.Sender := machineID;
427 out_msg.Destination.add(in_msg.Requestor);
428 out_msg.MessageSize := MessageSizeType:Response_Data;
433 action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
434 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
435 assert(is_valid(cache_entry));
436 out_msg.Address := address;
437 out_msg.Type := CoherenceResponseType:DATA;
438 out_msg.DataBlk := cache_entry.DataBlk;
439 out_msg.Dirty := cache_entry.Dirty;
440 out_msg.Sender := machineID;
441 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
442 l2_select_low_bit, l2_select_num_bits));
443 out_msg.MessageSize := MessageSizeType:Response_Data;
447 action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
448 peek(requestIntraChipL1Network_in, RequestMsg) {
449 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
450 assert(is_valid(tbe));
451 out_msg.Address := address;
452 out_msg.Type := CoherenceResponseType:DATA;
453 out_msg.DataBlk := tbe.DataBlk;
454 out_msg.Dirty := tbe.Dirty;
455 out_msg.Sender := machineID;
456 out_msg.Destination.add(in_msg.Requestor);
457 out_msg.MessageSize := MessageSizeType:Response_Data;
462 action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
463 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
464 assert(is_valid(tbe));
465 out_msg.Address := address;
466 out_msg.Type := CoherenceResponseType:DATA;
467 out_msg.DataBlk := tbe.DataBlk;
468 out_msg.Dirty := tbe.Dirty;
469 out_msg.Sender := machineID;
470 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
471 l2_select_low_bit, l2_select_num_bits));
472 out_msg.MessageSize := MessageSizeType:Response_Data;
476 action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
477 peek(requestIntraChipL1Network_in, RequestMsg) {
478 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
479 out_msg.Address := address;
480 out_msg.Type := CoherenceResponseType:ACK;
481 out_msg.Sender := machineID;
482 out_msg.Destination.add(in_msg.Requestor);
483 out_msg.MessageSize := MessageSizeType:Response_Control;
488 action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
489 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
490 assert(is_valid(cache_entry));
491 out_msg.Address := address;
492 out_msg.Type := CoherenceResponseType:DATA;
493 out_msg.DataBlk := cache_entry.DataBlk;
494 out_msg.Dirty := cache_entry.Dirty;
495 out_msg.Sender := machineID;
496 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
497 l2_select_low_bit, l2_select_num_bits));
498 out_msg.MessageSize := MessageSizeType:Writeback_Data;
502 action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
503 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
504 assert(is_valid(tbe));
505 out_msg.Address := address;
506 out_msg.Type := CoherenceResponseType:DATA;
507 out_msg.DataBlk := tbe.DataBlk;
508 out_msg.Dirty := tbe.Dirty;
509 out_msg.Sender := machineID;
510 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
511 l2_select_low_bit, l2_select_num_bits));
512 out_msg.MessageSize := MessageSizeType:Writeback_Data;
516 action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
517 peek(requestIntraChipL1Network_in, RequestMsg) {
518 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
519 out_msg.Address := address;
520 out_msg.Type := CoherenceResponseType:ACK;
521 out_msg.Sender := machineID;
522 out_msg.Destination.add(in_msg.Requestor);
523 out_msg.MessageSize := MessageSizeType:Response_Control;
524 out_msg.AckCount := 1;
530 action(g_issuePUTX, "g", desc="send data to the L2 cache") {
531 enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
532 assert(is_valid(cache_entry));
533 out_msg.Address := address;
534 out_msg.Type := CoherenceRequestType:PUTX;
535 out_msg.DataBlk := cache_entry.DataBlk;
536 out_msg.Dirty := cache_entry.Dirty;
537 out_msg.Requestor:= machineID;
538 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
539 l2_select_low_bit, l2_select_num_bits));
540 if (cache_entry.Dirty) {
541 out_msg.MessageSize := MessageSizeType:Writeback_Data;
543 out_msg.MessageSize := MessageSizeType:Writeback_Control;
548 action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
549 enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
550 out_msg.Address := address;
551 out_msg.Type := CoherenceResponseType:UNBLOCK;
552 out_msg.Sender := machineID;
553 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
554 l2_select_low_bit, l2_select_num_bits));
555 out_msg.MessageSize := MessageSizeType:Response_Control;
556 DPRINTF(RubySlicc, "%s\n", address);
561 action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
562 enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
563 out_msg.Address := address;
564 out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
565 out_msg.Sender := machineID;
566 out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
567 l2_select_low_bit, l2_select_num_bits));
568 out_msg.MessageSize := MessageSizeType:Response_Control;
569 DPRINTF(RubySlicc, "%s\n", address);
574 action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
575 assert(is_valid(cache_entry));
576 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
577 sequencer.readCallback(address, cache_entry.DataBlk);
580 action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
581 assert(is_valid(cache_entry));
582 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
583 sequencer.writeCallback(address, cache_entry.DataBlk);
584 cache_entry.Dirty := true;
587 action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
588 check_allocate(L1_TBEs);
589 assert(is_valid(cache_entry));
590 L1_TBEs.allocate(address);
591 set_tbe(L1_TBEs[address]);
592 tbe.isPrefetch := false;
593 tbe.Dirty := cache_entry.Dirty;
594 tbe.DataBlk := cache_entry.DataBlk;
597 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
598 mandatoryQueue_in.dequeue();
601 action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
602 profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
605 action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
606 profileMsgDelay(3, responseIntraChipL1Network_in.dequeue_getDelayCycles());
609 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
610 L1_TBEs.deallocate(address);
614 action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
615 peek(responseIntraChipL1Network_in, ResponseMsg) {
616 assert(is_valid(cache_entry));
617 cache_entry.DataBlk := in_msg.DataBlk;
618 cache_entry.Dirty := in_msg.Dirty;
622 action(q_updateAckCount, "q", desc="Update ack count") {
623 peek(responseIntraChipL1Network_in, ResponseMsg) {
624 assert(is_valid(tbe));
625 tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
626 APPEND_TRANSITION_COMMENT(in_msg.AckCount);
627 APPEND_TRANSITION_COMMENT(" p: ");
628 APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
632 action(z_stall, "z", desc="Stall") {
635 action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
636 if (L1DcacheMemory.isTagPresent(address)) {
637 L1DcacheMemory.deallocate(address);
639 L1IcacheMemory.deallocate(address);
644 action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
645 if (is_invalid(cache_entry)) {
646 set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
650 action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
651 if (is_invalid(cache_entry)) {
652 set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
656 action(zz_recycleRequestQueue, "zz", desc="recycle L1 request queue") {
657 requestIntraChipL1Network_in.recycle();
660 action(z_recycleMandatoryQueue, "\z", desc="recycle L1 request queue") {
661 mandatoryQueue_in.recycle();
665 //*****************************************************
667 //*****************************************************
669 // Transitions for Load/Store/Replacement/WriteBack from transient states
670 transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
671 z_recycleMandatoryQueue;
674 // Transitions from Idle
675 transition({NP,I}, L1_Replacement) {
676 ff_deallocateL1CacheBlock;
679 transition({NP,I}, Load, IS) {
680 oo_allocateL1DCacheBlock;
686 transition({NP,I}, Ifetch, IS) {
687 pp_allocateL1ICacheBlock;
693 transition({NP,I}, Store, IM) {
694 oo_allocateL1DCacheBlock;
700 transition({NP, I}, Inv) {
705 // Transitions from Shared
706 transition(S, {Load,Ifetch}) {
711 transition(S, Store, SM) {
717 transition(S, L1_Replacement, I) {
718 ff_deallocateL1CacheBlock;
721 transition(S, Inv, I) {
726 // Transitions from Exclusive
728 transition(E, {Load, Ifetch}) {
733 transition(E, Store, M) {
738 transition(E, L1_Replacement, M_I) {
739 // silent E replacement??
741 g_issuePUTX; // send data, but hold in case forwarded request
742 ff_deallocateL1CacheBlock;
745 transition(E, Inv, I) {
751 transition(E, Fwd_GETX, I) {
752 d_sendDataToRequestor;
756 transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
757 d_sendDataToRequestor;
762 // Transitions from Modified
763 transition(M, {Load, Ifetch}) {
768 transition(M, Store) {
773 transition(M, L1_Replacement, M_I) {
775 g_issuePUTX; // send data, but hold in case forwarded request
776 ff_deallocateL1CacheBlock;
779 transition(M_I, WB_Ack, I) {
781 o_popIncomingResponseQueue;
784 transition(M, Inv, I) {
789 transition(M_I, Inv, SINK_WB_ACK) {
790 ft_sendDataToL2_fromTBE;
794 transition(M, Fwd_GETX, I) {
795 d_sendDataToRequestor;
799 transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
800 d_sendDataToRequestor;
805 transition(M_I, Fwd_GETX, SINK_WB_ACK) {
806 dt_sendDataToRequestor_fromTBE;
810 transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, SINK_WB_ACK) {
811 dt_sendDataToRequestor_fromTBE;
812 d2t_sendDataToL2_fromTBE;
816 // Transitions from IS
817 transition({IS, IS_I}, Inv, IS_I) {
822 transition(IS, Data_all_Acks, S) {
823 u_writeDataToL1Cache;
826 o_popIncomingResponseQueue;
829 transition(IS_I, Data_all_Acks, I) {
830 u_writeDataToL1Cache;
833 o_popIncomingResponseQueue;
837 transition(IS, DataS_fromL1, S) {
838 u_writeDataToL1Cache;
842 o_popIncomingResponseQueue;
845 transition(IS_I, DataS_fromL1, I) {
846 u_writeDataToL1Cache;
850 o_popIncomingResponseQueue;
853 // directory is blocked when sending exclusive data
854 transition(IS_I, Data_Exclusive, E) {
855 u_writeDataToL1Cache;
857 jj_sendExclusiveUnblock;
859 o_popIncomingResponseQueue;
862 transition(IS, Data_Exclusive, E) {
863 u_writeDataToL1Cache;
865 jj_sendExclusiveUnblock;
867 o_popIncomingResponseQueue;
870 // Transitions from IM
871 transition({IM, SM}, Inv, IM) {
876 transition(IM, Data, SM) {
877 u_writeDataToL1Cache;
879 o_popIncomingResponseQueue;
882 transition(IM, Data_all_Acks, M) {
883 u_writeDataToL1Cache;
885 jj_sendExclusiveUnblock;
887 o_popIncomingResponseQueue;
890 // transitions from SM
891 transition({SM, IM}, Ack) {
893 o_popIncomingResponseQueue;
896 transition(SM, Ack_all, M) {
897 jj_sendExclusiveUnblock;
900 o_popIncomingResponseQueue;
903 transition(SINK_WB_ACK, {Load, Store, Ifetch, L1_Replacement}){
904 z_recycleMandatoryQueue;
908 transition(SINK_WB_ACK, Inv){
913 transition(SINK_WB_ACK, WB_Ack){
915 o_popIncomingResponseQueue;