3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
35 machine(L2Cache, "MESI Directory L2 Cache CMP")
36 : CacheMemory * L2cacheMemory,
37 int l2_request_latency = 2,
38 int l2_response_latency = 2,
42 // From local bank of L2 cache TO the network
43 MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> Memory
44 MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> a local L1
45 MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 || Memory
47 // FROM the network to this local bank of L2 cache
48 MessageBuffer unblockToL2Cache, network="From", virtual_network="2", ordered="false"; // a local L1 || Memory -> this L2 bank
49 MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank
50 MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false"; // a local L1 || Memory -> this L2 bank
51 // MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank
54 state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
56 NP, AccessPermission:Invalid, desc="Not present in either cache";
57 SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
58 M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
59 MT, AccessPermission:Invalid, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
62 M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
63 MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
64 MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
65 I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
66 S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
68 // Transient States for fetching data from memory
69 ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
70 IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
71 IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
74 SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
75 MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
76 M_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from M";
78 MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
79 MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
80 MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
85 enumeration(Event, desc="L2 Cache events") {
88 // events initiated by the local L1s
89 L1_GET_INSTR, desc="a L1I GET INSTR request for a block maped to us";
90 L1_GETS, desc="a L1D GETS request for a block maped to us";
91 L1_GETX, desc="a L1D GETX request for a block maped to us";
92 L1_UPGRADE, desc="a L1D GETX request for a block maped to us";
94 L1_PUTX, desc="L1 replacing data";
95 L1_PUTX_old, desc="L1 replacing data, but no longer sharer";
97 Fwd_L1_GETX, desc="L1 did not have data, so we supply";
98 Fwd_L1_GETS, desc="L1 did not have data, so we supply";
99 Fwd_L1_GET_INSTR, desc="L1 did not have data, so we supply";
101 // events initiated by this L2
102 L2_Replacement, desc="L2 Replacement", format="!r";
103 L2_Replacement_clean, desc="L2 Replacement, but data is clean", format="!r";
105 // events from memory controller
106 Mem_Data, desc="data from memory", format="!r";
107 Mem_Ack, desc="ack from memory", format="!r";
109 // M->S data writeback
110 WB_Data, desc="data from L1";
111 WB_Data_clean, desc="clean data from L1";
112 Ack, desc="writeback ack";
113 Ack_all, desc="writeback ack";
115 Unblock, desc="Unblock from L1 requestor";
116 Unblock_Cancel, desc="Unblock from L1 requestor (FOR XACT MEMORY)";
117 Exclusive_Unblock, desc="Unblock from L1 requestor";
119 MEM_Inv, desc="Invalidation from directory";
126 structure(Entry, desc="...", interface="AbstractCacheEntry") {
127 State CacheState, desc="cache state";
128 NetDest Sharers, desc="tracks the L1 shares on-chip";
129 MachineID Exclusive, desc="Exclusive holder of block";
130 DataBlock DataBlk, desc="data for the block";
131 bool Dirty, default="false", desc="data is dirty";
135 structure(TBE, desc="...") {
136 Address Address, desc="Physical address for this TBE";
137 State TBEState, desc="Transient state";
138 DataBlock DataBlk, desc="Buffer for the data block";
139 bool Dirty, default="false", desc="Data is Dirty";
141 NetDest L1_GetS_IDs, desc="Set of the internal processors that want the block in shared state";
142 MachineID L1_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
143 bool isPrefetch, desc="Set if this was caused by a prefetch";
145 int pendingAcks, desc="number of pending acks for invalidates during writeback";
148 structure(TBETable, external="yes") {
150 void allocate(Address);
151 void deallocate(Address);
152 bool isPresent(Address);
155 TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
157 void set_cache_entry(AbstractCacheEntry a);
158 void unset_cache_entry();
162 // inclusive cache, returns L2 entries only
163 Entry getCacheEntry(Address addr), return_by_pointer="yes" {
164 return static_cast(Entry, "pointer", L2cacheMemory[addr]);
167 std::string getCoherenceRequestTypeStr(CoherenceRequestType type) {
168 return CoherenceRequestType_to_string(type);
171 bool isOneSharerLeft(Address addr, MachineID requestor, Entry cache_entry) {
172 assert(is_valid(cache_entry));
173 assert(cache_entry.Sharers.isElement(requestor));
174 return (cache_entry.Sharers.count() == 1);
177 bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
178 if (is_valid(cache_entry)) {
179 return cache_entry.Sharers.isElement(requestor);
185 void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
186 assert(is_valid(cache_entry));
187 DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
188 machineID, requestor, addr);
189 cache_entry.Sharers.add(requestor);
192 State getState(TBE tbe, Entry cache_entry, Address addr) {
195 } else if (is_valid(cache_entry)) {
196 return cache_entry.CacheState;
201 std::string getStateStr(TBE tbe, Entry cache_entry, Address addr) {
202 return L2Cache_State_to_string(getState(tbe, cache_entry, addr));
205 // when is this called
206 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
210 tbe.TBEState := state;
213 if (is_valid(cache_entry)) {
214 cache_entry.CacheState := state;
218 Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
219 MachineID requestor, Entry cache_entry) {
220 if(type == CoherenceRequestType:GETS) {
221 return Event:L1_GETS;
222 } else if(type == CoherenceRequestType:GET_INSTR) {
223 return Event:L1_GET_INSTR;
224 } else if (type == CoherenceRequestType:GETX) {
225 return Event:L1_GETX;
226 } else if (type == CoherenceRequestType:UPGRADE) {
227 if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
228 return Event:L1_UPGRADE;
230 return Event:L1_GETX;
232 } else if (type == CoherenceRequestType:PUTX) {
233 if (isSharer(addr, requestor, cache_entry)) {
234 return Event:L1_PUTX;
236 return Event:L1_PUTX_old;
239 DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
240 error("Invalid L1 forwarded request type");
244 int getPendingAcks(TBE tbe) {
245 return tbe.pendingAcks;
248 bool isDirty(Entry cache_entry) {
249 assert(is_valid(cache_entry));
250 return cache_entry.Dirty;
255 out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache);
256 out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache);
257 out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache);
260 in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache) {
261 if(L1unblockNetwork_in.isReady()) {
262 peek(L1unblockNetwork_in, ResponseMsg) {
263 Entry cache_entry := getCacheEntry(in_msg.Address);
264 TBE tbe := L2_TBEs[in_msg.Address];
265 DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
266 in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
267 in_msg.Sender, in_msg.Type, in_msg.Destination);
269 assert(in_msg.Destination.isElement(machineID));
270 if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
271 trigger(Event:Exclusive_Unblock, in_msg.Address, cache_entry, tbe);
272 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
273 trigger(Event:Unblock, in_msg.Address, cache_entry, tbe);
275 error("unknown unblock message");
281 // Response IntraChip L2 Network - response msg to this particular L2 bank
282 in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache) {
283 if (responseIntraChipL2Network_in.isReady()) {
284 peek(responseIntraChipL2Network_in, ResponseMsg) {
285 // test wether it's from a local L1 or an off chip source
286 assert(in_msg.Destination.isElement(machineID));
287 Entry cache_entry := getCacheEntry(in_msg.Address);
288 TBE tbe := L2_TBEs[in_msg.Address];
290 if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
291 if(in_msg.Type == CoherenceResponseType:DATA) {
293 trigger(Event:WB_Data, in_msg.Address, cache_entry, tbe);
295 trigger(Event:WB_Data_clean, in_msg.Address, cache_entry, tbe);
297 } else if (in_msg.Type == CoherenceResponseType:ACK) {
298 if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
299 trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
301 trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
304 error("unknown message type");
307 } else { // external message
308 if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
309 // L2 now has data and all off-chip acks
310 trigger(Event:Mem_Data, in_msg.Address, cache_entry, tbe);
311 } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
312 // L2 now has data and all off-chip acks
313 trigger(Event:Mem_Ack, in_msg.Address, cache_entry, tbe);
314 } else if(in_msg.Type == CoherenceResponseType:INV) {
315 // L2 now has data and all off-chip acks
316 trigger(Event:MEM_Inv, in_msg.Address, cache_entry, tbe);
318 error("unknown message type");
322 } // if not ready, do nothing
326 in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache) {
327 if(L1RequestIntraChipL2Network_in.isReady()) {
328 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
329 Entry cache_entry := getCacheEntry(in_msg.Address);
330 TBE tbe := L2_TBEs[in_msg.Address];
332 DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
333 in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
334 in_msg.Requestor, in_msg.Type, in_msg.Destination);
336 assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
337 assert(in_msg.Destination.isElement(machineID));
339 if (is_valid(cache_entry)) {
340 // The L2 contains the block, so proceeded with handling the request
341 trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
342 in_msg.Requestor, cache_entry),
343 in_msg.Address, cache_entry, tbe);
345 if (L2cacheMemory.cacheAvail(in_msg.Address)) {
346 // L2 does't have the line, but we have space for it in the L2
347 trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
348 in_msg.Requestor, cache_entry),
349 in_msg.Address, cache_entry, tbe);
351 // No room in the L2, so we need to make room before handling the request
352 Entry L2cache_entry := getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address));
353 if (isDirty(L2cache_entry)) {
354 trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address),
355 L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
357 trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address),
358 L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
369 action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
370 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
371 enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
372 out_msg.Address := address;
373 out_msg.Type := CoherenceRequestType:GETS;
374 out_msg.Requestor := machineID;
375 out_msg.Destination.add(map_Address_to_Directory(address));
376 out_msg.MessageSize := MessageSizeType:Control;
381 action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
382 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
383 enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
384 assert(is_valid(cache_entry));
385 out_msg.Address := address;
386 out_msg.Type := in_msg.Type;
387 out_msg.Requestor := in_msg.Requestor;
388 out_msg.Destination.add(cache_entry.Exclusive);
389 out_msg.MessageSize := MessageSizeType:Request_Control;
394 action(c_exclusiveReplacement, "c", desc="Send data to memory") {
395 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
396 assert(is_valid(cache_entry));
397 out_msg.Address := address;
398 out_msg.Type := CoherenceResponseType:MEMORY_DATA;
399 out_msg.Sender := machineID;
400 out_msg.Destination.add(map_Address_to_Directory(address));
401 out_msg.DataBlk := cache_entry.DataBlk;
402 out_msg.Dirty := cache_entry.Dirty;
403 out_msg.MessageSize := MessageSizeType:Response_Data;
407 action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
408 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
409 out_msg.Address := address;
410 out_msg.Type := CoherenceResponseType:ACK;
411 out_msg.Sender := machineID;
412 out_msg.Destination.add(map_Address_to_Directory(address));
413 out_msg.MessageSize := MessageSizeType:Response_Control;
417 action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
418 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
419 assert(is_valid(tbe));
420 out_msg.Address := address;
421 out_msg.Type := CoherenceResponseType:MEMORY_DATA;
422 out_msg.Sender := machineID;
423 out_msg.Destination.add(map_Address_to_Directory(address));
424 out_msg.DataBlk := tbe.DataBlk;
425 out_msg.Dirty := tbe.Dirty;
426 out_msg.MessageSize := MessageSizeType:Response_Data;
430 action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
431 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
432 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
433 assert(is_valid(cache_entry));
434 out_msg.Address := address;
435 out_msg.Type := CoherenceResponseType:DATA;
436 out_msg.Sender := machineID;
437 out_msg.Destination.add(in_msg.Requestor);
438 out_msg.DataBlk := cache_entry.DataBlk;
439 out_msg.Dirty := cache_entry.Dirty;
440 out_msg.MessageSize := MessageSizeType:Response_Data;
442 out_msg.AckCount := 0 - cache_entry.Sharers.count();
443 if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
444 out_msg.AckCount := out_msg.AckCount + 1;
450 action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
451 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
452 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
453 assert(is_valid(cache_entry));
454 out_msg.Address := address;
455 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
456 out_msg.Sender := machineID;
457 out_msg.Destination.add(in_msg.Requestor);
458 out_msg.DataBlk := cache_entry.DataBlk;
459 out_msg.Dirty := cache_entry.Dirty;
460 out_msg.MessageSize := MessageSizeType:Response_Data;
462 out_msg.AckCount := 0 - cache_entry.Sharers.count();
463 if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
464 out_msg.AckCount := out_msg.AckCount + 1;
470 action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
471 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
472 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
473 assert(is_valid(cache_entry));
474 out_msg.Address := address;
475 out_msg.Type := CoherenceResponseType:DATA;
476 out_msg.Sender := machineID;
477 out_msg.Destination.add(in_msg.Requestor);
478 out_msg.DataBlk := cache_entry.DataBlk;
479 out_msg.Dirty := cache_entry.Dirty;
480 out_msg.MessageSize := MessageSizeType:Response_Data;
481 out_msg.AckCount := 0;
486 action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
487 assert(is_valid(tbe));
488 assert(tbe.L1_GetS_IDs.count() > 0);
489 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
490 assert(is_valid(cache_entry));
491 out_msg.Address := address;
492 out_msg.Type := CoherenceResponseType:DATA;
493 out_msg.Sender := machineID;
494 out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
495 out_msg.DataBlk := cache_entry.DataBlk;
496 out_msg.Dirty := cache_entry.Dirty;
497 out_msg.MessageSize := MessageSizeType:Response_Data;
501 action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
502 assert(is_valid(tbe));
503 assert(tbe.L1_GetS_IDs.count() == 1);
504 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
505 assert(is_valid(cache_entry));
506 out_msg.Address := address;
507 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
508 out_msg.Sender := machineID;
509 out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
510 out_msg.DataBlk := cache_entry.DataBlk;
511 out_msg.Dirty := cache_entry.Dirty;
512 out_msg.MessageSize := MessageSizeType:Response_Data;
516 action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
517 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
518 assert(is_valid(tbe));
519 assert(is_valid(cache_entry));
520 out_msg.Address := address;
521 out_msg.Type := CoherenceResponseType:DATA;
522 out_msg.Sender := machineID;
523 out_msg.Destination.add(tbe.L1_GetX_ID);
524 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
525 out_msg.DataBlk := cache_entry.DataBlk;
526 out_msg.Dirty := cache_entry.Dirty;
527 DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
528 out_msg.Address, out_msg.Destination, out_msg.DataBlk);
529 out_msg.MessageSize := MessageSizeType:Response_Data;
533 action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
534 enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
535 assert(is_valid(cache_entry));
536 out_msg.Address := address;
537 out_msg.Type := CoherenceRequestType:INV;
538 out_msg.Requestor := machineID;
539 out_msg.Destination := cache_entry.Sharers;
540 out_msg.MessageSize := MessageSizeType:Request_Control;
544 action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
545 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
546 enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
547 assert(is_valid(cache_entry));
548 out_msg.Address := address;
549 out_msg.Type := CoherenceRequestType:INV;
550 out_msg.Requestor := in_msg.Requestor;
551 out_msg.Destination := cache_entry.Sharers;
552 out_msg.MessageSize := MessageSizeType:Request_Control;
557 action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
558 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
559 enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
560 assert(is_valid(cache_entry));
561 out_msg.Address := address;
562 out_msg.Type := CoherenceRequestType:INV;
563 out_msg.Requestor := in_msg.Requestor;
564 out_msg.Destination := cache_entry.Sharers;
565 out_msg.Destination.remove(in_msg.Requestor);
566 out_msg.MessageSize := MessageSizeType:Request_Control;
572 action(i_allocateTBE, "i", desc="Allocate TBE for internal/external request(isPrefetch=0, number of invalidates=0)") {
573 check_allocate(L2_TBEs);
574 assert(is_valid(cache_entry));
575 L2_TBEs.allocate(address);
576 set_tbe(L2_TBEs[address]);
577 tbe.L1_GetS_IDs.clear();
578 tbe.DataBlk := cache_entry.DataBlk;
579 tbe.Dirty := cache_entry.Dirty;
580 tbe.pendingAcks := cache_entry.Sharers.count();
583 action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
584 L2_TBEs.deallocate(address);
588 action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
589 profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles());
592 action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
593 profileMsgDelay(0, L1unblockNetwork_in.dequeue_getDelayCycles());
596 action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
597 profileMsgDelay(3, responseIntraChipL2Network_in.dequeue_getDelayCycles());
600 action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
601 peek(responseIntraChipL2Network_in, ResponseMsg) {
602 assert(is_valid(cache_entry));
603 cache_entry.DataBlk := in_msg.DataBlk;
604 cache_entry.Dirty := in_msg.Dirty;
608 action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
609 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
610 assert(is_valid(cache_entry));
611 cache_entry.DataBlk := in_msg.DataBlk;
612 cache_entry.Dirty := in_msg.Dirty;
616 action(q_updateAck, "q", desc="update pending ack count") {
617 peek(responseIntraChipL2Network_in, ResponseMsg) {
618 assert(is_valid(tbe));
619 tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
620 APPEND_TRANSITION_COMMENT(in_msg.AckCount);
621 APPEND_TRANSITION_COMMENT(" p: ");
622 APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
626 action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
627 peek(responseIntraChipL2Network_in, ResponseMsg) {
628 assert(is_valid(tbe));
629 tbe.DataBlk := in_msg.DataBlk;
630 tbe.Dirty := in_msg.Dirty;
634 action(z_stall, "z", desc="Stall") {
637 action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
638 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
639 assert(is_valid(tbe));
640 tbe.L1_GetS_IDs.add(in_msg.Requestor);
644 action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
645 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
646 assert(is_valid(tbe));
647 tbe.L1_GetX_ID := in_msg.Requestor;
651 action(set_setMRU, "\set", desc="set the MRU entry") {
652 L2cacheMemory.setMRU(address);
655 action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
656 if (is_invalid(cache_entry)) {
657 set_cache_entry(L2cacheMemory.allocate(address, new Entry));
661 action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
662 L2cacheMemory.deallocate(address);
666 action(t_sendWBAck, "t", desc="Send writeback ACK") {
667 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
668 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
669 out_msg.Address := address;
670 out_msg.Type := CoherenceResponseType:WB_ACK;
671 out_msg.Sender := machineID;
672 out_msg.Destination.add(in_msg.Requestor);
673 out_msg.MessageSize := MessageSizeType:Response_Control;
678 action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
679 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
680 enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
681 assert(is_valid(cache_entry));
682 out_msg.Address := address;
683 out_msg.Type := CoherenceResponseType:ACK;
684 out_msg.Sender := machineID;
685 out_msg.Destination.add(in_msg.Requestor);
686 out_msg.MessageSize := MessageSizeType:Response_Control;
687 // upgrader doesn't get ack from itself, hence the + 1
688 out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
693 action(uu_profileMiss, "\u", desc="Profile the demand miss") {
694 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
695 //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor));
699 action(ww_profileMissNoDir, "\w", desc="Profile this transition at the L2 because Dir won't see the request") {
700 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
701 // profile_request(in_msg.L1CacheStateStr, getStateStr(address), "NA", getCoherenceRequestTypeStr(in_msg.Type));
705 action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
706 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
707 assert(is_valid(cache_entry));
708 addSharer(address, in_msg.Requestor, cache_entry);
709 APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
713 action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
714 peek(L1unblockNetwork_in, ResponseMsg) {
715 assert(is_valid(cache_entry));
716 addSharer(address, in_msg.Sender, cache_entry);
720 action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
721 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
722 assert(is_valid(cache_entry));
723 cache_entry.Sharers.remove(in_msg.Requestor);
727 action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
728 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
729 assert(is_valid(cache_entry));
730 cache_entry.Sharers.clear();
734 action(mm_markExclusive, "\m", desc="set the exclusive owner") {
735 peek(L1RequestIntraChipL2Network_in, RequestMsg) {
736 assert(is_valid(cache_entry));
737 cache_entry.Sharers.clear();
738 cache_entry.Exclusive := in_msg.Requestor;
739 addSharer(address, in_msg.Requestor, cache_entry);
743 action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
744 peek(L1unblockNetwork_in, ResponseMsg) {
745 assert(is_valid(cache_entry));
746 cache_entry.Sharers.clear();
747 cache_entry.Exclusive := in_msg.Sender;
748 addSharer(address, in_msg.Sender, cache_entry);
752 action(zz_recycleL1RequestQueue, "zz", desc="recycle L1 request queue") {
753 L1RequestIntraChipL2Network_in.recycle();
756 action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
757 responseIntraChipL2Network_in.recycle();
761 //*****************************************************
763 //*****************************************************
766 //===============================================
769 // Transitions from I (Idle)
770 transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, M_MB, MT_IB, MT_SB}, L1_PUTX) {
772 jj_popL1RequestQueue;
775 transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, M_MB, MT_IB, MT_SB}, L1_PUTX_old) {
777 jj_popL1RequestQueue;
780 transition({IM, IS, ISS, SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
781 zz_recycleL1RequestQueue;
784 transition({IM, IS, ISS, SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
785 zn_recycleResponseNetwork;
788 transition({S_I, M_I, MT_I}, MEM_Inv) {
789 o_popIncomingResponseQueue;
793 transition({SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
794 zz_recycleL1RequestQueue;
798 transition(NP, L1_GETS, ISS) {
799 qq_allocateL2CacheBlock;
804 a_issueFetchToMemory;
806 jj_popL1RequestQueue;
809 transition(NP, L1_GET_INSTR, IS) {
810 qq_allocateL2CacheBlock;
815 a_issueFetchToMemory;
817 jj_popL1RequestQueue;
820 transition(NP, L1_GETX, IM) {
821 qq_allocateL2CacheBlock;
826 a_issueFetchToMemory;
828 jj_popL1RequestQueue;
832 // transitions from IS/IM
834 transition(ISS, Mem_Data, MT_MB) {
836 ex_sendExclusiveDataToGetSRequestors;
838 o_popIncomingResponseQueue;
841 transition(IS, Mem_Data, SS) {
843 e_sendDataToGetSRequestors;
845 o_popIncomingResponseQueue;
848 transition(IM, Mem_Data, MT_MB) {
850 ee_sendDataToGetXRequestor;
852 o_popIncomingResponseQueue;
855 transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
859 jj_popL1RequestQueue;
862 transition({IS, ISS}, L1_GETX) {
863 zz_recycleL1RequestQueue;
866 transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
867 zz_recycleL1RequestQueue;
870 // transitions from SS
871 transition(SS, {L1_GETS, L1_GET_INSTR}) {
872 ds_sendSharedDataToRequestor;
876 jj_popL1RequestQueue;
880 transition(SS, L1_GETX, SS_MB) {
881 d_sendDataToRequestor;
882 // fw_sendFwdInvToSharers;
883 fwm_sendFwdInvToSharersMinusRequestor;
886 jj_popL1RequestQueue;
889 transition(SS, L1_UPGRADE, SS_MB) {
890 fwm_sendFwdInvToSharersMinusRequestor;
891 ts_sendInvAckToUpgrader;
894 jj_popL1RequestQueue;
897 transition(SS, L2_Replacement_clean, I_I) {
900 rr_deallocateL2CacheBlock;
903 transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
906 rr_deallocateL2CacheBlock;
910 transition(M, L1_GETX, MT_MB) {
911 d_sendDataToRequestor;
914 jj_popL1RequestQueue;
917 transition(M, L1_GET_INSTR, SS) {
918 d_sendDataToRequestor;
922 jj_popL1RequestQueue;
925 transition(M, L1_GETS, MT_MB) {
926 dd_sendExclusiveDataToRequestor;
929 jj_popL1RequestQueue;
932 transition(M, {L2_Replacement, MEM_Inv}, M_I) {
934 c_exclusiveReplacement;
935 rr_deallocateL2CacheBlock;
938 transition(M, L2_Replacement_clean, M_I) {
940 c_exclusiveCleanReplacement;
941 rr_deallocateL2CacheBlock;
945 // transitions from MT
947 transition(MT, L1_GETX, MT_MB) {
948 b_forwardRequestToExclusive;
951 jj_popL1RequestQueue;
955 transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
956 b_forwardRequestToExclusive;
959 jj_popL1RequestQueue;
962 transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
965 rr_deallocateL2CacheBlock;
968 transition(MT, L2_Replacement_clean, MCT_I) {
971 rr_deallocateL2CacheBlock;
974 transition(MT, L1_PUTX, M) {
976 mr_writeDataToCacheFromRequest;
978 jj_popL1RequestQueue;
982 // transitions from blocking states
983 transition(SS_MB, Unblock_Cancel, SS) {
987 transition(MT_MB, Unblock_Cancel, MT) {
991 transition(MT_IB, Unblock_Cancel, MT) {
995 transition(SS_MB, Exclusive_Unblock, MT) {
996 // update actual directory
997 mmu_markExclusiveFromUnblock;
1001 transition({M_MB, MT_MB}, Exclusive_Unblock, MT) {
1002 // update actual directory
1003 mmu_markExclusiveFromUnblock;
1007 transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
1008 zz_recycleL1RequestQueue;
1011 transition(MT_IIB, Unblock, MT_IB) {
1012 nnu_addSharerFromUnblock;
1016 transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
1018 o_popIncomingResponseQueue;
1021 transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
1023 o_popIncomingResponseQueue;
1026 transition(MT_SB, Unblock, SS) {
1027 nnu_addSharerFromUnblock;
1032 transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
1033 zz_recycleL1RequestQueue;
1036 transition(I_I, Ack) {
1038 o_popIncomingResponseQueue;
1041 transition(I_I, Ack_all, M_I) {
1042 c_exclusiveCleanReplacement;
1043 o_popIncomingResponseQueue;
1046 transition({MT_I, MCT_I}, WB_Data, M_I) {
1048 ct_exclusiveReplacementFromTBE;
1049 o_popIncomingResponseQueue;
1052 transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
1053 c_exclusiveCleanReplacement;
1054 o_popIncomingResponseQueue;
1057 transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
1058 zz_recycleL1RequestQueue;
1061 // L1 never changed Dirty data
1062 transition(MT_I, Ack_all, M_I) {
1063 ct_exclusiveReplacementFromTBE;
1064 o_popIncomingResponseQueue;
1067 transition(MT_I, {L1_PUTX, L1_PUTX_old}){
1068 zz_recycleL1RequestQueue;
1071 // possible race between unblock and immediate replacement
1072 transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
1073 zz_recycleL1RequestQueue;
1076 transition(MT_I, WB_Data_clean, NP) {
1078 o_popIncomingResponseQueue;
1081 transition(S_I, Ack) {
1083 o_popIncomingResponseQueue;
1086 transition(S_I, Ack_all, M_I) {
1087 ct_exclusiveReplacementFromTBE;
1088 o_popIncomingResponseQueue;
1091 transition(M_I, Mem_Ack, NP) {
1093 o_popIncomingResponseQueue;