3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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31 * $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
34 // This file is copied from Yasuko Watanabe's prefetch / memory protocol
35 // Copied here by aep 12/14/07
38 machine(Directory, "MESI_CMP_filter_directory protocol")
39 : DirectoryMemory * directory,
40 MemoryControl * memBuffer,
41 int to_mem_ctrl_latency = 1,
42 int directory_latency = 6
45 MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false", vnet_type="request";
46 MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false", vnet_type="response";
48 MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false", vnet_type="request";
49 MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false", vnet_type="response";
52 state_declaration(State, desc="Directory states", default="Directory_State_I") {
54 I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
55 ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
56 ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
58 M, AccessPermission:Maybe_Stale, desc="memory copy may be stale, i.e. other modified copies may exist";
59 IM, AccessPermission:Busy, desc="Intermediate State I>M";
60 MI, AccessPermission:Busy, desc="Intermediate State M>I";
61 M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
62 M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
63 M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
64 M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
68 enumeration(Event, desc="Directory events") {
69 Fetch, desc="A memory fetch arrives";
70 Data, desc="writeback data arrives";
71 Memory_Data, desc="Fetched data from memory arrives";
72 Memory_Ack, desc="Writeback Ack from memory arrives";
74 DMA_READ, desc="A DMA Read memory request";
75 DMA_WRITE, desc="A DMA Write memory request";
76 CleanReplacement, desc="Clean Replacement in L2 cache";
83 structure(Entry, desc="...", interface="AbstractEntry") {
84 State DirectoryState, desc="Directory state";
85 DataBlock DataBlk, desc="data for the block";
86 NetDest Sharers, desc="Sharers for this block";
87 NetDest Owner, desc="Owner of this block";
90 // TBE entries for DMA requests
91 structure(TBE, desc="TBE entries for outstanding DMA requests") {
92 Address PhysicalAddress, desc="physical address";
93 State TBEState, desc="Transient State";
94 DataBlock DataBlk, desc="Data to be written (DMA write only)";
98 structure(TBETable, external="yes") {
100 void allocate(Address);
101 void deallocate(Address);
102 bool isPresent(Address);
108 TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
110 void set_tbe(TBE tbe);
112 void wakeUpBuffers(Address a);
114 Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
115 Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
117 if (is_valid(dir_entry)) {
121 dir_entry := static_cast(Entry, "pointer",
122 directory.allocate(addr, new Entry));
126 State getState(TBE tbe, Address addr) {
129 } else if (directory.isPresent(addr)) {
130 return getDirectoryEntry(addr).DirectoryState;
136 void setState(TBE tbe, Address addr, State state) {
139 tbe.TBEState := state;
142 if (directory.isPresent(addr)) {
144 if (state == State:I) {
145 assert(getDirectoryEntry(addr).Owner.count() == 0);
146 assert(getDirectoryEntry(addr).Sharers.count() == 0);
147 } else if (state == State:M) {
148 assert(getDirectoryEntry(addr).Owner.count() == 1);
149 assert(getDirectoryEntry(addr).Sharers.count() == 0);
152 getDirectoryEntry(addr).DirectoryState := state;
156 AccessPermission getAccessPermission(Address addr) {
157 TBE tbe := TBEs[addr];
159 DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
160 return Directory_State_to_permission(tbe.TBEState);
163 if(directory.isPresent(addr)) {
164 DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
165 return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
168 DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
169 return AccessPermission:NotPresent;
172 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
173 TBE tbe := TBEs[addr];
178 return getDirectoryEntry(addr).DataBlk;
181 void setAccessPermission(Address addr, State state) {
182 if (directory.isPresent(addr)) {
183 getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
187 bool isGETRequest(CoherenceRequestType type) {
188 return (type == CoherenceRequestType:GETS) ||
189 (type == CoherenceRequestType:GET_INSTR) ||
190 (type == CoherenceRequestType:GETX);
195 out_port(responseNetwork_out, ResponseMsg, responseFromDir);
196 out_port(memQueue_out, MemoryMsg, memBuffer);
200 in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) {
201 if (requestNetwork_in.isReady()) {
202 peek(requestNetwork_in, RequestMsg) {
203 assert(in_msg.Destination.isElement(machineID));
204 if (isGETRequest(in_msg.Type)) {
205 trigger(Event:Fetch, in_msg.Address, TBEs[in_msg.Address]);
206 } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
207 trigger(Event:DMA_READ, makeLineAddress(in_msg.Address),
208 TBEs[makeLineAddress(in_msg.Address)]);
209 } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
210 trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address),
211 TBEs[makeLineAddress(in_msg.Address)]);
213 DPRINTF(RubySlicc, "%s\n", in_msg);
214 error("Invalid message");
220 in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) {
221 if (responseNetwork_in.isReady()) {
222 peek(responseNetwork_in, ResponseMsg) {
223 assert(in_msg.Destination.isElement(machineID));
224 if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
225 trigger(Event:Data, in_msg.Address, TBEs[in_msg.Address]);
226 } else if (in_msg.Type == CoherenceResponseType:ACK) {
227 trigger(Event:CleanReplacement, in_msg.Address, TBEs[in_msg.Address]);
229 DPRINTF(RubySlicc, "%s\n", in_msg.Type);
230 error("Invalid message");
236 // off-chip memory request/response is done
237 in_port(memQueue_in, MemoryMsg, memBuffer, rank = 2) {
238 if (memQueue_in.isReady()) {
239 peek(memQueue_in, MemoryMsg) {
240 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
241 trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
242 } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
243 trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
245 DPRINTF(RubySlicc, "%s\n", in_msg.Type);
246 error("Invalid message");
254 action(a_sendAck, "a", desc="Send ack to L2") {
255 peek(responseNetwork_in, ResponseMsg) {
256 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
257 out_msg.Address := address;
258 out_msg.Type := CoherenceResponseType:MEMORY_ACK;
259 out_msg.Sender := machineID;
260 out_msg.Destination.add(in_msg.Sender);
261 out_msg.MessageSize := MessageSizeType:Response_Control;
266 action(d_sendData, "d", desc="Send data to requestor") {
267 peek(memQueue_in, MemoryMsg) {
268 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
269 out_msg.Address := address;
270 out_msg.Type := CoherenceResponseType:MEMORY_DATA;
271 out_msg.Sender := machineID;
272 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
273 out_msg.DataBlk := in_msg.DataBlk;
274 out_msg.Dirty := false;
275 out_msg.MessageSize := MessageSizeType:Response_Data;
281 action(aa_sendAck, "aa", desc="Send ack to L2") {
282 peek(memQueue_in, MemoryMsg) {
283 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
284 out_msg.Address := address;
285 out_msg.Type := CoherenceResponseType:MEMORY_ACK;
286 out_msg.Sender := machineID;
287 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
288 out_msg.MessageSize := MessageSizeType:Response_Control;
293 action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
294 requestNetwork_in.dequeue();
297 action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
298 responseNetwork_in.dequeue();
301 action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
302 memQueue_in.dequeue();
305 action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
306 wakeUpBuffers(address);
309 action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
310 peek(requestNetwork_in, RequestMsg) {
311 enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
312 out_msg.Address := address;
313 out_msg.Type := MemoryRequestType:MEMORY_READ;
314 out_msg.Sender := machineID;
315 out_msg.OriginalRequestorMachId := in_msg.Requestor;
316 out_msg.MessageSize := in_msg.MessageSize;
317 out_msg.Prefetch := in_msg.Prefetch;
318 out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
320 DPRINTF(RubySlicc, "%s\n", out_msg);
325 action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
326 peek(responseNetwork_in, ResponseMsg) {
327 enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
328 out_msg.Address := address;
329 out_msg.Type := MemoryRequestType:MEMORY_WB;
330 out_msg.Sender := machineID;
331 out_msg.OriginalRequestorMachId := in_msg.Sender;
332 out_msg.DataBlk := in_msg.DataBlk;
333 out_msg.MessageSize := in_msg.MessageSize;
334 //out_msg.Prefetch := in_msg.Prefetch;
336 DPRINTF(RubySlicc, "%s\n", out_msg);
341 action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
342 peek(responseNetwork_in, ResponseMsg) {
343 getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
344 DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
345 in_msg.Address, in_msg.DataBlk);
348 //added by SS for dma
349 action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
350 peek(requestNetwork_in, RequestMsg) {
351 enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
352 out_msg.Address := address;
353 out_msg.Type := MemoryRequestType:MEMORY_READ;
354 out_msg.Sender := machineID;
355 out_msg.OriginalRequestorMachId := machineID;
356 out_msg.MessageSize := in_msg.MessageSize;
357 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
358 DPRINTF(RubySlicc, "%s\n", out_msg);
363 action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
364 requestNetwork_in.dequeue();
367 action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
368 peek(memQueue_in, MemoryMsg) {
369 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
370 out_msg.Address := address;
371 out_msg.Type := CoherenceResponseType:DATA;
372 out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
373 out_msg.Destination.add(map_Address_to_DMA(address));
374 out_msg.MessageSize := MessageSizeType:Response_Data;
379 action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
380 peek(requestNetwork_in, RequestMsg) {
381 getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
385 action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
386 peek(requestNetwork_in, RequestMsg) {
387 enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
388 out_msg.Address := address;
389 out_msg.Type := MemoryRequestType:MEMORY_WB;
390 out_msg.OriginalRequestorMachId := machineID;
391 //out_msg.DataBlk := in_msg.DataBlk;
392 out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(address), in_msg.Len);
395 out_msg.MessageSize := in_msg.MessageSize;
396 //out_msg.Prefetch := in_msg.Prefetch;
398 DPRINTF(RubySlicc, "%s\n", out_msg);
403 action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
404 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
405 out_msg.Address := address;
406 out_msg.Type := CoherenceResponseType:ACK;
407 out_msg.Destination.add(map_Address_to_DMA(address));
408 out_msg.MessageSize := MessageSizeType:Writeback_Control;
412 action(z_stallAndWaitRequest, "z", desc="recycle request queue") {
413 stall_and_wait(requestNetwork_in, address);
416 action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
417 requestNetwork_in.recycle();
421 action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
422 peek(requestNetwork_in, RequestMsg) {
423 getDirectoryEntry(address).Owner.clear();
424 getDirectoryEntry(address).Owner.add(in_msg.Requestor);
429 action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
430 peek(requestNetwork_in, RequestMsg) {
431 enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
432 out_msg.Address := address;
433 out_msg.Type := CoherenceResponseType:INV;
434 out_msg.Sender := machineID;
435 out_msg.Destination := getDirectoryEntry(address).Owner;
436 out_msg.MessageSize := MessageSizeType:Response_Control;
442 action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
443 peek(responseNetwork_in, ResponseMsg) {
444 enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
445 out_msg.Address := address;
446 out_msg.Type := CoherenceResponseType:DATA;
447 out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
448 out_msg.Destination.add(map_Address_to_DMA(address));
449 out_msg.MessageSize := MessageSizeType:Response_Data;
454 action(c_clearOwner, "c", desc="Clear the owner field") {
455 getDirectoryEntry(address).Owner.clear();
458 action(v_allocateTBE, "v", desc="Allocate TBE") {
459 peek(requestNetwork_in, RequestMsg) {
460 TBEs.allocate(address);
461 set_tbe(TBEs[address]);
462 tbe.DataBlk := in_msg.DataBlk;
463 tbe.PhysicalAddress := in_msg.Address;
464 tbe.Len := in_msg.Len;
468 action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
469 assert(is_valid(tbe));
470 //getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
471 getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
477 action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
478 peek(responseNetwork_in, ResponseMsg) {
479 enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
480 assert(is_valid(tbe));
481 out_msg.Address := address;
482 out_msg.Type := MemoryRequestType:MEMORY_WB;
483 out_msg.OriginalRequestorMachId := in_msg.Sender;
484 //out_msg.DataBlk := in_msg.DataBlk;
485 //out_msg.DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
486 out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
488 out_msg.MessageSize := in_msg.MessageSize;
489 //out_msg.Prefetch := in_msg.Prefetch;
491 DPRINTF(RubySlicc, "%s\n", out_msg);
496 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
497 TBEs.deallocate(address);
505 transition(I, Fetch, IM) {
506 qf_queueMemoryFetchRequest;
508 j_popIncomingRequestQueue;
511 transition(IM, Memory_Data, M) {
517 transition(M, CleanReplacement, I) {
520 k_popIncomingResponseQueue;
523 transition(M, Data, MI) {
525 qw_queueMemoryWBRequest;
526 k_popIncomingResponseQueue;
529 transition(MI, Memory_Ack, I) {
537 //added by SS for dma support
538 transition(I, DMA_READ, ID) {
539 qf_queueMemoryFetchRequestDMA;
540 j_popIncomingRequestQueue;
543 transition(ID, Memory_Data, I) {
549 transition(I, DMA_WRITE, ID_W) {
551 qw_queueMemoryWBRequest_partial;
552 j_popIncomingRequestQueue;
555 transition(ID_W, Memory_Ack, I) {
561 transition({ID, ID_W, M_DRDI, M_DWRI, IM, MI}, {Fetch, Data} ) {
562 z_stallAndWaitRequest;
565 transition({ID, ID_W, M_DRD, M_DRDI, M_DWR, M_DWRI, IM, MI}, {DMA_WRITE, DMA_READ} ) {
570 transition(M, DMA_READ, M_DRD) {
571 inv_sendCacheInvalidate;
572 j_popIncomingRequestQueue;
575 transition(M_DRD, Data, M_DRDI) {
578 qw_queueMemoryWBRequest;
579 k_popIncomingResponseQueue;
582 transition(M_DRDI, Memory_Ack, I) {
589 transition(M, DMA_WRITE, M_DWR) {
591 inv_sendCacheInvalidate;
592 j_popIncomingRequestQueue;
595 transition(M_DWR, Data, M_DWRI) {
597 qw_queueMemoryWBRequest_partialTBE;
598 k_popIncomingResponseQueue;
601 transition(M_DWRI, Memory_Ack, I) {
602 dwt_writeDMADataFromTBE;