src/mem/protocol/MESI_CMP_directory-dma.sm

   1 /*
   2  * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 machine(DMA, "DMA Controller")
  31 : DMASequencer * dma_sequencer,
  32   Cycles request_latency = 6
  33 {
  34
  35   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
  36   MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
  37
  38   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  39     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  40     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  41     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  42   }
  43
  44   enumeration(Event, desc="DMA events") {
  45     ReadRequest,  desc="A new read request";
  46     WriteRequest, desc="A new write request";
  47     Data,         desc="Data from a DMA memory read";
  48     Ack,          desc="DMA write to memory completed";
  49   }
  50
  51   structure(DMASequencer, external="yes") {
  52     void ackCallback();
  53     void dataCallback(DataBlock);
  54   }
  55
  56   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
  57   State cur_state, no_vector="true";
  58
  59   State getState(Address addr) {
  60     return cur_state;
  61   }
  62   void setState(Address addr, State state) {
  63   cur_state := state;
  64   }
  65
  66   AccessPermission getAccessPermission(Address addr) {
  67     return AccessPermission:NotPresent;
  68   }
  69
  70   void setAccessPermission(Address addr, State state) {
  71   }
  72
  73   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
  74     error("DMA does not support get data block.");
  75   }
  76
  77   out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
  78
  79   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  80     if (dmaRequestQueue_in.isReady()) {
  81       peek(dmaRequestQueue_in, SequencerMsg) {
  82         if (in_msg.Type == SequencerRequestType:LD ) {
  83           trigger(Event:ReadRequest, in_msg.LineAddress);
  84         } else if (in_msg.Type == SequencerRequestType:ST) {
  85           trigger(Event:WriteRequest, in_msg.LineAddress);
  86         } else {
  87           error("Invalid request type");
  88         }
  89       }
  90     }
  91   }
  92
  93   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
  94     if (dmaResponseQueue_in.isReady()) {
  95       peek( dmaResponseQueue_in, ResponseMsg) {
  96         if (in_msg.Type == CoherenceResponseType:ACK) {
  97           trigger(Event:Ack, makeLineAddress(in_msg.Addr));
  98         } else if (in_msg.Type == CoherenceResponseType:DATA) {
  99           trigger(Event:Data, makeLineAddress(in_msg.Addr));
 100         } else {
 101           error("Invalid response type");
 102         }
 103       }
 104     }
 105   }
 106
 107   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 108     peek(dmaRequestQueue_in, SequencerMsg) {
 109       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 110         out_msg.Addr := in_msg.PhysicalAddress;
 111         out_msg.Type := CoherenceRequestType:DMA_READ;
 112         out_msg.DataBlk := in_msg.DataBlk;
 113         out_msg.Len := in_msg.Len;
 114         out_msg.Destination.add(map_Address_to_Directory(address));
 115         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 116       }
 117     }
 118   }
 119
 120   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 121     peek(dmaRequestQueue_in, SequencerMsg) {
 122       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 123           out_msg.Addr := in_msg.PhysicalAddress;
 124           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 125           out_msg.DataBlk := in_msg.DataBlk;
 126           out_msg.Len := in_msg.Len;
 127           out_msg.Destination.add(map_Address_to_Directory(address));
 128           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 129         }
 130       }
 131   }
 132
 133   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 134     dma_sequencer.ackCallback();
 135   }
 136
 137   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 138     peek (dmaResponseQueue_in, ResponseMsg) {
 139       dma_sequencer.dataCallback(in_msg.DataBlk);
 140     }
 141   }
 142
 143   action(p_popRequestQueue, "p", desc="Pop request queue") {
 144     dmaRequestQueue_in.dequeue();
 145   }
 146
 147   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 148     dmaResponseQueue_in.dequeue();
 149   }
 150
 151   action(z_stall, "z", desc="dma is busy..stall") {
 152     // do nothing
 153   }
 154
 155   transition(READY, ReadRequest, BUSY_RD) {
 156     s_sendReadRequest;
 157     p_popRequestQueue;
 158   }
 159
 160   transition(READY, WriteRequest, BUSY_WR) {
 161     s_sendWriteRequest;
 162     p_popRequestQueue;
 163   }
 164
 165   transition(BUSY_RD, Data, READY) {
 166     d_dataCallback;
 167     p_popResponseQueue;
 168   }
 169
 170   transition(BUSY_WR, Ack, READY) {
 171     a_ackCallback;
 172     p_popResponseQueue;
 173   }
 174 }