src/mem/protocol/MESI_CMP_directory-dma.sm

   1
   2 machine(DMA, "DMA Controller")
   3 : DMASequencer * dma_sequencer,
   4   int request_latency = 6
   5 {
   6
   7   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
   8   MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
   9
  10   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  11     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  12     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  13     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  14   }
  15
  16   enumeration(Event, desc="DMA events") {
  17     ReadRequest,  desc="A new read request";
  18     WriteRequest, desc="A new write request";
  19     Data,         desc="Data from a DMA memory read";
  20     Ack,          desc="DMA write to memory completed";
  21   }
  22
  23   external_type(DMASequencer) {
  24     void ackCallback();
  25     void dataCallback(DataBlock);
  26   }
  27
  28   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
  29   State cur_state, no_vector="true";
  30
  31   State getState(Address addr) {
  32     return cur_state;
  33   }
  34   void setState(Address addr, State state) {
  35   cur_state := state;
  36   }
  37
  38   out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
  39
  40   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  41     if (dmaRequestQueue_in.isReady()) {
  42       peek(dmaRequestQueue_in, SequencerMsg) {
  43         if (in_msg.Type == SequencerRequestType:LD ) {
  44           trigger(Event:ReadRequest, in_msg.LineAddress);
  45         } else if (in_msg.Type == SequencerRequestType:ST) {
  46           trigger(Event:WriteRequest, in_msg.LineAddress);
  47         } else {
  48           error("Invalid request type");
  49         }
  50       }
  51     }
  52   }
  53
  54   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
  55     if (dmaResponseQueue_in.isReady()) {
  56       peek( dmaResponseQueue_in, ResponseMsg) {
  57         if (in_msg.Type == CoherenceResponseType:ACK) {
  58           trigger(Event:Ack, makeLineAddress(in_msg.Address));
  59         } else if (in_msg.Type == CoherenceResponseType:DATA) {
  60           trigger(Event:Data, makeLineAddress(in_msg.Address));
  61         } else {
  62           error("Invalid response type");
  63         }
  64       }
  65     }
  66   }
  67
  68   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
  69     peek(dmaRequestQueue_in, SequencerMsg) {
  70       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
  71         out_msg.Address := in_msg.PhysicalAddress;
  72         out_msg.Type := CoherenceRequestType:DMA_READ;
  73         out_msg.DataBlk := in_msg.DataBlk;
  74         out_msg.Len := in_msg.Len;
  75         out_msg.Destination.add(map_Address_to_Directory(address));
  76         out_msg.MessageSize := MessageSizeType:Writeback_Control;
  77       }
  78     }
  79   }
  80
  81   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
  82     peek(dmaRequestQueue_in, SequencerMsg) {
  83       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
  84           out_msg.Address := in_msg.PhysicalAddress;
  85           out_msg.Type := CoherenceRequestType:DMA_WRITE;
  86           out_msg.DataBlk := in_msg.DataBlk;
  87           out_msg.Len := in_msg.Len;
  88           out_msg.Destination.add(map_Address_to_Directory(address));
  89           out_msg.MessageSize := MessageSizeType:Writeback_Control;
  90         }
  91       }
  92   }
  93
  94   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
  95     dma_sequencer.ackCallback();
  96   }
  97
  98   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
  99     peek (dmaResponseQueue_in, ResponseMsg) {
 100       dma_sequencer.dataCallback(in_msg.DataBlk);
 101     }
 102   }
 103
 104   action(p_popRequestQueue, "p", desc="Pop request queue") {
 105     dmaRequestQueue_in.dequeue();
 106   }
 107
 108   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 109     dmaResponseQueue_in.dequeue();
 110   }
 111
 112   action(z_stall, "z", desc="dma is busy..stall") {
 113     // do nothing
 114   }
 115
 116   transition(READY, ReadRequest, BUSY_RD) {
 117     s_sendReadRequest;
 118     p_popRequestQueue;
 119   }
 120
 121   transition(READY, WriteRequest, BUSY_WR) {
 122     s_sendWriteRequest;
 123     p_popRequestQueue;
 124   }
 125
 126   transition(BUSY_RD, Data, READY) {
 127     d_dataCallback;
 128     p_popResponseQueue;
 129   }
 130
 131   transition(BUSY_WR, Ack, READY) {
 132     a_ackCallback;
 133     p_popResponseQueue;
 134   }
 135 }