src/mem/protocol/MESI_CMP_directory-dma.sm

   1
   2 machine(DMA, "DMA Controller")
   3 : DMASequencer * dma_sequencer,
   4   int request_latency = 6
   5 {
   6
   7   MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
   8   MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
   9
  10   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  11     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  12     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  13     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  14   }
  15
  16   enumeration(Event, desc="DMA events") {
  17     ReadRequest,  desc="A new read request";
  18     WriteRequest, desc="A new write request";
  19     Data,         desc="Data from a DMA memory read";
  20     Ack,          desc="DMA write to memory completed";
  21   }
  22
  23   structure(DMASequencer, external="yes") {
  24     void ackCallback();
  25     void dataCallback(DataBlock);
  26   }
  27
  28   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
  29   State cur_state, no_vector="true";
  30
  31   State getState(Address addr) {
  32     return cur_state;
  33   }
  34   void setState(Address addr, State state) {
  35   cur_state := state;
  36   }
  37
  38   AccessPermission getAccessPermission(Address addr) {
  39     return AccessPermission:NotPresent;
  40   }
  41
  42   void setAccessPermission(Address addr, State state) {
  43   }
  44
  45   out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
  46
  47   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  48     if (dmaRequestQueue_in.isReady()) {
  49       peek(dmaRequestQueue_in, SequencerMsg) {
  50         if (in_msg.Type == SequencerRequestType:LD ) {
  51           trigger(Event:ReadRequest, in_msg.LineAddress);
  52         } else if (in_msg.Type == SequencerRequestType:ST) {
  53           trigger(Event:WriteRequest, in_msg.LineAddress);
  54         } else {
  55           error("Invalid request type");
  56         }
  57       }
  58     }
  59   }
  60
  61   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
  62     if (dmaResponseQueue_in.isReady()) {
  63       peek( dmaResponseQueue_in, ResponseMsg) {
  64         if (in_msg.Type == CoherenceResponseType:ACK) {
  65           trigger(Event:Ack, makeLineAddress(in_msg.Address));
  66         } else if (in_msg.Type == CoherenceResponseType:DATA) {
  67           trigger(Event:Data, makeLineAddress(in_msg.Address));
  68         } else {
  69           error("Invalid response type");
  70         }
  71       }
  72     }
  73   }
  74
  75   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
  76     peek(dmaRequestQueue_in, SequencerMsg) {
  77       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
  78         out_msg.Address := in_msg.PhysicalAddress;
  79         out_msg.Type := CoherenceRequestType:DMA_READ;
  80         out_msg.DataBlk := in_msg.DataBlk;
  81         out_msg.Len := in_msg.Len;
  82         out_msg.Destination.add(map_Address_to_Directory(address));
  83         out_msg.MessageSize := MessageSizeType:Writeback_Control;
  84       }
  85     }
  86   }
  87
  88   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
  89     peek(dmaRequestQueue_in, SequencerMsg) {
  90       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
  91           out_msg.Address := in_msg.PhysicalAddress;
  92           out_msg.Type := CoherenceRequestType:DMA_WRITE;
  93           out_msg.DataBlk := in_msg.DataBlk;
  94           out_msg.Len := in_msg.Len;
  95           out_msg.Destination.add(map_Address_to_Directory(address));
  96           out_msg.MessageSize := MessageSizeType:Writeback_Control;
  97         }
  98       }
  99   }
 100
 101   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 102     dma_sequencer.ackCallback();
 103   }
 104
 105   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 106     peek (dmaResponseQueue_in, ResponseMsg) {
 107       dma_sequencer.dataCallback(in_msg.DataBlk);
 108     }
 109   }
 110
 111   action(p_popRequestQueue, "p", desc="Pop request queue") {
 112     dmaRequestQueue_in.dequeue();
 113   }
 114
 115   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 116     dmaResponseQueue_in.dequeue();
 117   }
 118
 119   action(z_stall, "z", desc="dma is busy..stall") {
 120     // do nothing
 121   }
 122
 123   transition(READY, ReadRequest, BUSY_RD) {
 124     s_sendReadRequest;
 125     p_popRequestQueue;
 126   }
 127
 128   transition(READY, WriteRequest, BUSY_WR) {
 129     s_sendWriteRequest;
 130     p_popRequestQueue;
 131   }
 132
 133   transition(BUSY_RD, Data, READY) {
 134     d_dataCallback;
 135     p_popResponseQueue;
 136   }
 137
 138   transition(BUSY_WR, Ack, READY) {
 139     a_ackCallback;
 140     p_popResponseQueue;
 141   }
 142 }