Cache: Remove dangling doWriteback declaration
[gem5.git] / src / mem / protocol / MESI_CMP_directory-msg.sm
1
2 /*
3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30
31 // CoherenceRequestType
32 enumeration(CoherenceRequestType, desc="...") {
33 GETX, desc="Get eXclusive";
34 UPGRADE, desc="UPGRADE to exclusive";
35 GETS, desc="Get Shared";
36 GET_INSTR, desc="Get Instruction";
37 INV, desc="INValidate";
38 PUTX, desc="replacement message";
39
40 WB_ACK, desc="Writeback ack";
41 WB_NACK, desc="Writeback neg. ack";
42 FWD, desc="Generic FWD";
43
44 DMA_READ, desc="DMA Read";
45 DMA_WRITE, desc="DMA Write";
46 }
47
48 // CoherenceResponseType
49 enumeration(CoherenceResponseType, desc="...") {
50 MEMORY_ACK, desc="Ack from memory controller";
51 DATA, desc="Data";
52 DATA_EXCLUSIVE, desc="Data";
53 MEMORY_DATA, desc="Data";
54 ACK, desc="Generic invalidate ack";
55 WB_ACK, desc="writeback ack";
56 UNBLOCK, desc="unblock";
57 EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
58 INV, desc="Invalidate from directory";
59 }
60
61 // RequestMsg
62 structure(RequestMsg, desc="...", interface="NetworkMessage") {
63 Address Address, desc="Physical address for this request";
64 CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
65 RubyAccessMode AccessMode, desc="user/supervisor access type";
66 MachineID Requestor , desc="What component request";
67 NetDest Destination, desc="What components receive the request, includes MachineType and num";
68 MessageSizeType MessageSize, desc="size category of the message";
69 DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
70 int Len;
71 bool Dirty, default="false", desc="Dirty bit";
72 PrefetchBit Prefetch, desc="Is this a prefetch request";
73 }
74
75 // ResponseMsg
76 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
77 Address Address, desc="Physical address for this request";
78 CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
79 MachineID Sender, desc="What component sent the data";
80 NetDest Destination, desc="Node to whom the data is sent";
81 DataBlock DataBlk, desc="Data for the cache line";
82 bool Dirty, default="false", desc="Dirty bit";
83 int AckCount, default="0", desc="number of acks in this message";
84 MessageSizeType MessageSize, desc="size category of the message";
85 }
86
87