3 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
36 machine(L1Cache, "MSI Directory L1 Cache CMP") {
39 // From this node's L1 cache TO the network
40 // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
41 MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
42 // a local L1 -> this L2 bank
43 MessageBuffer responseFromL1Cache, network="To", virtual_network="3", ordered="false";
44 MessageBuffer unblockFromL1Cache, network="To", virtual_network="4", ordered="false";
47 // To this node's L1 cache FROM the network
48 // a L2 bank -> this L1
49 MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
50 // a L2 bank -> this L1
51 MessageBuffer responseToL1Cache, network="From", virtual_network="3", ordered="false";
54 enumeration(State, desc="Cache states", default="L1Cache_State_I") {
56 NP, desc="Not present in either cache";
57 I, desc="a L1 cache entry Idle";
58 S, desc="a L1 cache entry Shared";
59 E, desc="a L1 cache entry Exclusive";
60 M, desc="a L1 cache entry Modified", format="!b";
63 IS, desc="L1 idle, issued GETS, have not seen response yet";
64 IM, desc="L1 idle, issued GETX, have not seen response yet";
65 SM, desc="L1 idle, issued GETX, have not seen response yet";
66 IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
68 M_I, desc="L1 replacing, waiting for ACK";
69 E_I, desc="L1 replacing, waiting for ACK";
74 enumeration(Event, desc="Cache events") {
76 Load, desc="Load request from the home processor";
77 Ifetch, desc="I-fetch request from the home processor";
78 Store, desc="Store request from the home processor";
80 Inv, desc="Invalidate request from L2 bank";
82 // internal generated request
83 L1_Replacement, desc="L1 Replacement", format="!r";
86 Fwd_GETX, desc="GETX from other processor";
87 Fwd_GETS, desc="GETS from other processor";
88 Fwd_GET_INSTR, desc="GET_INSTR from other processor";
90 Data, desc="Data for processor";
91 Data_Exclusive, desc="Data for processor";
92 DataS_fromL1, desc="data for GETS request, need to unblock directory";
93 Data_all_Acks, desc="Data for processor, all acks";
95 Ack, desc="Ack for processor";
96 Ack_all, desc="Last ack for processor";
98 WB_Ack, desc="Ack for replacement";
104 structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
105 State CacheState, desc="cache state";
106 DataBlock DataBlk, desc="data for the block";
107 bool Dirty, default="false", desc="data is dirty";
111 structure(TBE, desc="...") {
112 Address Address, desc="Physical address for this TBE";
113 State TBEState, desc="Transient state";
114 DataBlock DataBlk, desc="Buffer for the data block";
115 bool Dirty, default="false", desc="data is dirty";
116 bool isPrefetch, desc="Set if this was caused by a prefetch";
117 int pendingAcks, default="0", desc="number of pending acks";
120 external_type(CacheMemory) {
121 bool cacheAvail(Address);
122 Address cacheProbe(Address);
123 void allocate(Address);
124 void deallocate(Address);
125 Entry lookup(Address);
126 void changePermission(Address, AccessPermission);
127 bool isTagPresent(Address);
130 external_type(TBETable) {
132 void allocate(Address);
133 void deallocate(Address);
134 bool isPresent(Address);
137 TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
139 CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
140 CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
142 MessageBuffer mandatoryQueue, ordered="false", rank="100", abstract_chip_ptr="true";
144 Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
146 int cache_state_to_int(State state);
148 // inclusive cache returns L1 entries only
149 Entry getL1CacheEntry(Address addr), return_by_ref="yes" {
150 if (L1DcacheMemory.isTagPresent(addr)) {
151 return L1DcacheMemory[addr];
153 return L1IcacheMemory[addr];
157 void changeL1Permission(Address addr, AccessPermission permission) {
158 if (L1DcacheMemory.isTagPresent(addr)) {
159 return L1DcacheMemory.changePermission(addr, permission);
160 } else if(L1IcacheMemory.isTagPresent(addr)) {
161 return L1IcacheMemory.changePermission(addr, permission);
163 error("cannot change permission, L1 block not present");
167 bool isL1CacheTagPresent(Address addr) {
168 return (L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
171 State getState(Address addr) {
172 if((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == true){
176 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
178 if(L1_TBEs.isPresent(addr)) {
179 return L1_TBEs[addr].TBEState;
180 } else if (isL1CacheTagPresent(addr)) {
181 return getL1CacheEntry(addr).CacheState;
187 void setState(Address addr, State state) {
188 assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
191 if(L1_TBEs.isPresent(addr)) {
192 L1_TBEs[addr].TBEState := state;
195 if (isL1CacheTagPresent(addr)) {
196 getL1CacheEntry(addr).CacheState := state;
199 if (state == State:I) {
200 changeL1Permission(addr, AccessPermission:Invalid);
201 } else if (state == State:S || state == State:E) {
202 changeL1Permission(addr, AccessPermission:Read_Only);
203 } else if (state == State:M) {
204 changeL1Permission(addr, AccessPermission:Read_Write);
206 changeL1Permission(addr, AccessPermission:Busy);
211 Event mandatory_request_type_to_event(CacheRequestType type) {
212 if (type == CacheRequestType:LD) {
214 } else if (type == CacheRequestType:IFETCH) {
216 } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
219 error("Invalid CacheRequestType");
223 GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
224 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
225 return GenericMachineType:L1Cache_wCC; // NOTE direct L1 hits should not call this
226 } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
227 return GenericMachineType:L2Cache;
229 return ConvertMachToGenericMach(machineIDToMachineType(sender));
235 out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
236 out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
237 out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
239 // Response IntraChip L1 Network - response msg to this L1 cache
240 in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
241 if (responseIntraChipL1Network_in.isReady()) {
242 peek(responseIntraChipL1Network_in, ResponseMsg) {
243 assert(in_msg.Destination.isElement(machineID));
244 if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
245 trigger(Event:Data_Exclusive, in_msg.Address);
246 } else if(in_msg.Type == CoherenceResponseType:DATA) {
247 if ( (getState(in_msg.Address) == State:IS || getState(in_msg.Address) == State:IS_I) &&
248 machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache ) {
250 trigger(Event:DataS_fromL1, in_msg.Address);
252 } else if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0 ) {
253 trigger(Event:Data_all_Acks, in_msg.Address);
255 trigger(Event:Data, in_msg.Address);
257 } else if (in_msg.Type == CoherenceResponseType:ACK) {
258 if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0 ) {
259 trigger(Event:Ack_all, in_msg.Address);
261 trigger(Event:Ack, in_msg.Address);
263 } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
264 trigger(Event:WB_Ack, in_msg.Address);
266 error("Invalid L1 response type");
272 // Request InterChip network - request from this L1 cache to the shared L2
273 in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
274 if(requestIntraChipL1Network_in.isReady()) {
275 peek(requestIntraChipL1Network_in, RequestMsg) {
276 assert(in_msg.Destination.isElement(machineID));
277 if (in_msg.Type == CoherenceRequestType:INV) {
278 trigger(Event:Inv, in_msg.Address);
279 } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
280 // upgrade transforms to GETX due to race
281 trigger(Event:Fwd_GETX, in_msg.Address);
282 } else if (in_msg.Type == CoherenceRequestType:GETS) {
283 trigger(Event:Fwd_GETS, in_msg.Address);
284 } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
285 trigger(Event:Fwd_GET_INSTR, in_msg.Address);
287 error("Invalid forwarded request type");
293 // Mandatory Queue betweens Node's CPU and it's L1 caches
294 in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
295 if (mandatoryQueue_in.isReady()) {
296 peek(mandatoryQueue_in, CacheMsg) {
298 // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
300 if (in_msg.Type == CacheRequestType:IFETCH) {
301 // ** INSTRUCTION ACCESS ***
303 // Check to see if it is in the OTHER L1
304 if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
305 // The block is in the wrong L1, put the request on the queue to the shared L2
306 trigger(Event:L1_Replacement, in_msg.Address);
308 if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
309 // The tag matches for the L1, so the L1 asks the L2 for it.
310 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
312 if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
313 // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
314 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
316 // No room in the L1, so we need to make room in the L1
317 trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.Address));
321 // *** DATA ACCESS ***
323 // Check to see if it is in the OTHER L1
324 if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
325 // The block is in the wrong L1, put the request on the queue to the shared L2
326 trigger(Event:L1_Replacement, in_msg.Address);
328 if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
329 // The tag matches for the L1, so the L1 ask the L2 for it
330 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
332 if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
333 // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
334 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
336 // No room in the L1, so we need to make room in the L1
337 trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.Address));
346 action(a_issueGETS, "a", desc="Issue GETS") {
347 peek(mandatoryQueue_in, CacheMsg) {
348 enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
349 out_msg.Address := address;
350 out_msg.Type := CoherenceRequestType:GETS;
351 out_msg.Requestor := machineID;
352 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
354 DEBUG_EXPR(out_msg.Destination);
355 out_msg.MessageSize := MessageSizeType:Control;
356 out_msg.Prefetch := in_msg.Prefetch;
357 out_msg.AccessMode := in_msg.AccessMode;
362 action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
363 peek(mandatoryQueue_in, CacheMsg) {
364 enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
365 out_msg.Address := address;
366 out_msg.Type := CoherenceRequestType:GET_INSTR;
367 out_msg.Requestor := machineID;
368 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
370 DEBUG_EXPR(out_msg.Destination);
371 out_msg.MessageSize := MessageSizeType:Control;
372 out_msg.Prefetch := in_msg.Prefetch;
373 out_msg.AccessMode := in_msg.AccessMode;
379 action(b_issueGETX, "b", desc="Issue GETX") {
380 peek(mandatoryQueue_in, CacheMsg) {
381 enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
382 out_msg.Address := address;
383 out_msg.Type := CoherenceRequestType:GETX;
384 out_msg.Requestor := machineID;
385 DEBUG_EXPR(machineID);
386 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
388 DEBUG_EXPR(out_msg.Destination);
389 out_msg.MessageSize := MessageSizeType:Control;
390 out_msg.Prefetch := in_msg.Prefetch;
391 out_msg.AccessMode := in_msg.AccessMode;
396 action(c_issueUPGRADE, "c", desc="Issue GETX") {
397 peek(mandatoryQueue_in, CacheMsg) {
398 enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
399 out_msg.Address := address;
400 out_msg.Type := CoherenceRequestType:UPGRADE;
401 out_msg.Requestor := machineID;
402 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
404 DEBUG_EXPR(out_msg.Destination);
405 out_msg.MessageSize := MessageSizeType:Control;
406 out_msg.Prefetch := in_msg.Prefetch;
407 out_msg.AccessMode := in_msg.AccessMode;
412 action(d_sendDataToRequestor, "d", desc="send data to requestor") {
413 peek(requestIntraChipL1Network_in, RequestMsg) {
414 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
415 out_msg.Address := address;
416 out_msg.Type := CoherenceResponseType:DATA;
417 out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
418 out_msg.Dirty := getL1CacheEntry(address).Dirty;
419 out_msg.Sender := machineID;
420 out_msg.Destination.add(in_msg.Requestor);
421 out_msg.MessageSize := MessageSizeType:Response_Data;
426 action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
427 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
428 out_msg.Address := address;
429 out_msg.Type := CoherenceResponseType:DATA;
430 out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
431 out_msg.Dirty := getL1CacheEntry(address).Dirty;
432 out_msg.Sender := machineID;
433 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
434 out_msg.MessageSize := MessageSizeType:Response_Data;
438 action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
439 peek(requestIntraChipL1Network_in, RequestMsg) {
440 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
441 out_msg.Address := address;
442 out_msg.Type := CoherenceResponseType:DATA;
443 out_msg.DataBlk := L1_TBEs[address].DataBlk;
444 out_msg.Dirty := L1_TBEs[address].Dirty;
445 out_msg.Sender := machineID;
446 out_msg.Destination.add(in_msg.Requestor);
447 out_msg.MessageSize := MessageSizeType:Response_Data;
452 action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
453 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
454 out_msg.Address := address;
455 out_msg.Type := CoherenceResponseType:DATA;
456 out_msg.DataBlk := L1_TBEs[address].DataBlk;
457 out_msg.Dirty := L1_TBEs[address].Dirty;
458 out_msg.Sender := machineID;
459 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
460 out_msg.MessageSize := MessageSizeType:Response_Data;
464 action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
465 peek(requestIntraChipL1Network_in, RequestMsg) {
466 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
467 out_msg.Address := address;
468 out_msg.Type := CoherenceResponseType:ACK;
469 out_msg.Sender := machineID;
470 out_msg.Destination.add(in_msg.Requestor);
471 out_msg.MessageSize := MessageSizeType:Response_Control;
476 action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
477 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
478 out_msg.Address := address;
479 out_msg.Type := CoherenceResponseType:DATA;
480 out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
481 out_msg.Dirty := getL1CacheEntry(address).Dirty;
482 out_msg.Sender := machineID;
483 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
484 out_msg.MessageSize := MessageSizeType:Writeback_Data;
488 action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
489 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
490 out_msg.Address := address;
491 out_msg.Type := CoherenceResponseType:DATA;
492 out_msg.DataBlk := L1_TBEs[address].DataBlk;
493 out_msg.Dirty := L1_TBEs[address].Dirty;
494 out_msg.Sender := machineID;
495 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
496 out_msg.MessageSize := MessageSizeType:Writeback_Data;
500 action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
501 peek(requestIntraChipL1Network_in, RequestMsg) {
502 enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
503 out_msg.Address := address;
504 out_msg.Type := CoherenceResponseType:ACK;
505 out_msg.Sender := machineID;
506 out_msg.Destination.add(in_msg.Requestor);
507 out_msg.MessageSize := MessageSizeType:Response_Control;
508 out_msg.AckCount := 1;
514 action(g_issuePUTX, "g", desc="send data to the L2 cache") {
515 enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_RESPONSE_LATENCY") {
516 out_msg.Address := address;
517 out_msg.Type := CoherenceRequestType:PUTX;
518 out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
519 out_msg.Dirty := getL1CacheEntry(address).Dirty;
520 out_msg.Requestor:= machineID;
521 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
522 if (getL1CacheEntry(address).Dirty) {
523 out_msg.MessageSize := MessageSizeType:Writeback_Data;
525 out_msg.MessageSize := MessageSizeType:Writeback_Control;
530 action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
531 enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
532 out_msg.Address := address;
533 out_msg.Type := CoherenceResponseType:UNBLOCK;
534 out_msg.Sender := machineID;
535 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
536 out_msg.MessageSize := MessageSizeType:Response_Control;
540 action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
541 enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
542 out_msg.Address := address;
543 out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
544 out_msg.Sender := machineID;
545 out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
546 out_msg.MessageSize := MessageSizeType:Response_Control;
552 action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
553 DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
554 sequencer.readCallback(address, getL1CacheEntry(address).DataBlk);
557 action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
558 peek(responseIntraChipL1Network_in, ResponseMsg) {
559 sequencer.readCallback(address, getL1CacheEntry(address).DataBlk, getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
564 action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
565 sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk);
566 getL1CacheEntry(address).Dirty := true;
569 action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
570 peek(responseIntraChipL1Network_in, ResponseMsg) {
571 sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk, getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
573 getL1CacheEntry(address).Dirty := true;
577 action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
578 check_allocate(L1_TBEs);
579 L1_TBEs.allocate(address);
580 L1_TBEs[address].isPrefetch := false;
581 L1_TBEs[address].Dirty := getL1CacheEntry(address).Dirty;
582 L1_TBEs[address].DataBlk := getL1CacheEntry(address).DataBlk;
585 action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
586 mandatoryQueue_in.dequeue();
589 action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
590 profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
593 action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
594 profileMsgDelay(3, responseIntraChipL1Network_in.dequeue_getDelayCycles());
597 action(s_deallocateTBE, "s", desc="Deallocate TBE") {
598 L1_TBEs.deallocate(address);
601 action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
602 peek(responseIntraChipL1Network_in, ResponseMsg) {
603 getL1CacheEntry(address).DataBlk := in_msg.DataBlk;
604 getL1CacheEntry(address).Dirty := in_msg.Dirty;
608 action(q_updateAckCount, "q", desc="Update ack count") {
609 peek(responseIntraChipL1Network_in, ResponseMsg) {
610 L1_TBEs[address].pendingAcks := L1_TBEs[address].pendingAcks - in_msg.AckCount;
611 APPEND_TRANSITION_COMMENT(in_msg.AckCount);
612 APPEND_TRANSITION_COMMENT(" p: ");
613 APPEND_TRANSITION_COMMENT(L1_TBEs[address].pendingAcks);
617 action(z_stall, "z", desc="Stall") {
620 action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
621 if (L1DcacheMemory.isTagPresent(address)) {
622 L1DcacheMemory.deallocate(address);
624 L1IcacheMemory.deallocate(address);
628 action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
629 if (L1DcacheMemory.isTagPresent(address) == false) {
630 L1DcacheMemory.allocate(address);
634 action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
635 if (L1IcacheMemory.isTagPresent(address) == false) {
636 L1IcacheMemory.allocate(address);
640 action(zz_recycleRequestQueue, "zz", desc="recycle L1 request queue") {
641 requestIntraChipL1Network_in.recycle();
644 action(z_recycleMandatoryQueue, "\z", desc="recycle L1 request queue") {
645 mandatoryQueue_in.recycle();
649 //*****************************************************
651 //*****************************************************
653 // Transitions for Load/Store/Replacement/WriteBack from transient states
654 transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
655 z_recycleMandatoryQueue;
658 // Transitions from Idle
659 transition({NP,I}, L1_Replacement) {
660 ff_deallocateL1CacheBlock;
663 transition({NP,I}, Load, IS) {
664 oo_allocateL1DCacheBlock;
670 transition({NP,I}, Ifetch, IS) {
671 pp_allocateL1ICacheBlock;
677 transition({NP,I}, Store, IM) {
678 oo_allocateL1DCacheBlock;
684 transition({NP, I}, Inv) {
689 // Transitions from Shared
690 transition(S, {Load,Ifetch}) {
695 transition(S, Store, SM) {
701 transition(S, L1_Replacement, I) {
702 ff_deallocateL1CacheBlock;
705 transition(S, Inv, I) {
710 // Transitions from Exclusive
712 transition(E, {Load, Ifetch}) {
717 transition(E, Store, M) {
722 transition(E, L1_Replacement, M_I) {
723 // silent E replacement??
725 g_issuePUTX; // send data, but hold in case forwarded request
726 ff_deallocateL1CacheBlock;
729 transition(E, Inv, I) {
735 transition(E, Fwd_GETX, I) {
736 d_sendDataToRequestor;
740 transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
741 d_sendDataToRequestor;
746 // Transitions from Modified
747 transition(M, {Load, Ifetch}) {
752 transition(M, Store) {
757 transition(M, L1_Replacement, M_I) {
759 g_issuePUTX; // send data, but hold in case forwarded request
760 ff_deallocateL1CacheBlock;
763 transition(M_I, WB_Ack, I) {
765 o_popIncomingResponseQueue;
768 transition(M, Inv, I) {
773 transition(M_I, Inv, I) {
774 ft_sendDataToL2_fromTBE;
779 transition(M, Fwd_GETX, I) {
780 d_sendDataToRequestor;
784 transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
785 d_sendDataToRequestor;
790 transition(M_I, Fwd_GETX, I) {
791 dt_sendDataToRequestor_fromTBE;
796 transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, I) {
797 dt_sendDataToRequestor_fromTBE;
798 d2t_sendDataToL2_fromTBE;
803 // Transitions from IS
804 transition({IS, IS_I}, Inv, IS_I) {
809 transition(IS, Data_all_Acks, S) {
810 u_writeDataToL1Cache;
814 o_popIncomingResponseQueue;
817 transition(IS_I, Data_all_Acks, I) {
818 u_writeDataToL1Cache;
822 o_popIncomingResponseQueue;
826 transition(IS, DataS_fromL1, S) {
827 u_writeDataToL1Cache;
831 o_popIncomingResponseQueue;
834 transition(IS_I, DataS_fromL1, I) {
835 u_writeDataToL1Cache;
839 o_popIncomingResponseQueue;
842 // directory is blocked when sending exclusive data
843 transition(IS_I, Data_Exclusive, E) {
844 u_writeDataToL1Cache;
846 jj_sendExclusiveUnblock;
848 o_popIncomingResponseQueue;
851 transition(IS, Data_Exclusive, E) {
852 u_writeDataToL1Cache;
854 jj_sendExclusiveUnblock;
856 o_popIncomingResponseQueue;
859 // Transitions from IM
860 transition({IM, SM}, Inv, IM) {
865 transition(IM, Data, SM) {
866 u_writeDataToL1Cache;
868 o_popIncomingResponseQueue;
871 transition(IM, Data_all_Acks, M) {
872 u_writeDataToL1Cache;
873 xx_external_store_hit;
874 jj_sendExclusiveUnblock;
876 o_popIncomingResponseQueue;
879 // transitions from SM
880 transition({SM, IM}, Ack) {
882 o_popIncomingResponseQueue;
885 transition(SM, Ack_all, M) {
886 jj_sendExclusiveUnblock;
887 xx_external_store_hit;
889 o_popIncomingResponseQueue;