src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
  32  *
  33  */
  34
  35 machine(L2Cache, "MOSI Directory L2 Cache CMP") {
  36
  37   // L2 BANK QUEUES
  38   // From local bank of L2 cache TO the network
  39   MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="2", ordered="false";  // this L2 bank -> Memory
  40   MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false";  // this L2 bank -> a local L1
  41   MessageBuffer responseFromL2Cache, network="To", virtual_network="3", ordered="false";  // this L2 bank -> a local L1 || Memory
  42
  43   // FROM the network to this local bank of L2 cache
  44   MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false";  // a local L1 -> this L2 bank
  45   MessageBuffer responseToL2Cache, network="From", virtual_network="3", ordered="false";  // a local L1 || Memory -> this L2 bank
  46   MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false";  // a local L1 || Memory -> this L2 bank
  47
  48   // STATES
  49   enumeration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
  50     // Base states
  51     NP, desc="Not present in either cache";
  52     SS, desc="L2 cache entry Shared, also present in one or more L1s";
  53     M, desc="L2 cache entry Modified, not present in any L1s", format="!b";
  54     MT, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
  55
  56     // L2 replacement
  57     M_I, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
  58     MT_I, desc="L2 cache replacing, getting data from exclusive";
  59     MCT_I, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
  60     I_I, desc="L2 replacing clean data, need to inv sharers and then drop data";
  61     S_I, desc="L2 replacing dirty data, collecting acks from L1s";
  62
  63     // Transient States for fetching data from memory
  64     ISS, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
  65     IS, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
  66     IM, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
  67
  68     // Blocking states
  69     SS_MB, desc="Blocked for L1_GETX from SS";
  70     MT_MB, desc="Blocked for L1_GETX from MT";
  71     M_MB, desc="Blocked for L1_GETX from M";
  72
  73     MT_IIB, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
  74     MT_IB, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
  75     MT_SB, desc="Blocked for L1_GETS from MT, got data,  waiting for unblock";
  76
  77   }
  78
  79   // EVENTS
  80   enumeration(Event, desc="L2 Cache events") {
  81     // L2 events
  82
  83     // events initiated by the local L1s
  84     L1_GET_INSTR,            desc="a L1I GET INSTR request for a block maped to us";
  85     L1_GETS,                 desc="a L1D GETS request for a block maped to us";
  86     L1_GETX,                 desc="a L1D GETX request for a block maped to us";
  87     L1_UPGRADE,                 desc="a L1D GETX request for a block maped to us";
  88
  89     L1_PUTX,                 desc="L1 replacing data";
  90     L1_PUTX_old,             desc="L1 replacing data, but no longer sharer";
  91
  92     Fwd_L1_GETX,             desc="L1 did not have data, so we supply";
  93     Fwd_L1_GETS,             desc="L1 did not have data, so we supply";
  94     Fwd_L1_GET_INSTR,             desc="L1 did not have data, so we supply";
  95
  96     // events initiated by this L2
  97     L2_Replacement,     desc="L2 Replacement", format="!r";
  98     L2_Replacement_clean,     desc="L2 Replacement, but data is clean", format="!r";
  99
 100     // events from memory controller
 101     Mem_Data,     desc="data from memory", format="!r";
 102     Mem_Ack,     desc="ack from memory", format="!r";
 103
 104     // M->S data writeback
 105     WB_Data,  desc="data from L1";
 106     WB_Data_clean,  desc="clean data from L1";
 107     Ack,      desc="writeback ack";
 108     Ack_all,      desc="writeback ack";
 109
 110     Unblock, desc="Unblock from L1 requestor";
 111     Unblock_Cancel, desc="Unblock from L1 requestor (FOR XACT MEMORY)";
 112     Exclusive_Unblock, desc="Unblock from L1 requestor";
 113
 114   }
 115
 116   // TYPES
 117
 118   // CacheEntry
 119   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 120     State CacheState,          desc="cache state";
 121     NetDest Sharers,               desc="tracks the L1 shares on-chip";
 122     MachineID Exclusive,          desc="Exclusive holder of block";
 123     DataBlock DataBlk,       desc="data for the block";
 124     bool Dirty, default="false", desc="data is dirty";
 125   }
 126
 127   // TBE fields
 128   structure(TBE, desc="...") {
 129     Address Address,            desc="Physical address for this TBE";
 130     State TBEState,             desc="Transient state";
 131     DataBlock DataBlk,          desc="Buffer for the data block";
 132     bool Dirty, default="false", desc="Data is Dirty";
 133
 134     NetDest L1_GetS_IDs,            desc="Set of the internal processors that want the block in shared state";
 135     MachineID L1_GetX_ID,          desc="ID of the L1 cache to forward the block to once we get a response";
 136     bool isPrefetch,            desc="Set if this was caused by a prefetch";
 137
 138     int pendingAcks,            desc="number of pending acks for invalidates during writeback";
 139   }
 140
 141   external_type(CacheMemory) {
 142     bool cacheAvail(Address);
 143     Address cacheProbe(Address);
 144     void allocate(Address);
 145     void deallocate(Address);
 146     Entry lookup(Address);
 147     void changePermission(Address, AccessPermission);
 148     bool isTagPresent(Address);
 149     void setMRU(Address);
 150   }
 151
 152   external_type(TBETable) {
 153     TBE lookup(Address);
 154     void allocate(Address);
 155     void deallocate(Address);
 156     bool isPresent(Address);
 157   }
 158
 159   TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
 160
 161   CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)';
 162
 163   // inclusive cache, returns L2 entries only
 164   Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
 165     return L2cacheMemory[addr];
 166   }
 167
 168   void changeL2Permission(Address addr, AccessPermission permission) {
 169     if (L2cacheMemory.isTagPresent(addr)) {
 170       return L2cacheMemory.changePermission(addr, permission);
 171     }
 172   }
 173
 174   std::string getCoherenceRequestTypeStr(CoherenceRequestType type) {
 175     return CoherenceRequestType_to_string(type);
 176   }
 177
 178   bool isL2CacheTagPresent(Address addr) {
 179     return (L2cacheMemory.isTagPresent(addr));
 180   }
 181
 182   bool isOneSharerLeft(Address addr, MachineID requestor) {
 183     assert(L2cacheMemory[addr].Sharers.isElement(requestor));
 184     return (L2cacheMemory[addr].Sharers.count() == 1);
 185   }
 186
 187   bool isSharer(Address addr, MachineID requestor) {
 188     if (L2cacheMemory.isTagPresent(addr)) {
 189       return L2cacheMemory[addr].Sharers.isElement(requestor);
 190     } else {
 191       return false;
 192     }
 193   }
 194
 195   void addSharer(Address addr, MachineID requestor) {
 196     DEBUG_EXPR(machineID);
 197     DEBUG_EXPR(requestor);
 198     DEBUG_EXPR(addr);
 199     assert(map_L1CacheMachId_to_L2Cache(addr, requestor) == machineID);
 200     L2cacheMemory[addr].Sharers.add(requestor);
 201   }
 202
 203   State getState(Address addr) {
 204     if(L2_TBEs.isPresent(addr)) {
 205       return L2_TBEs[addr].TBEState;
 206     } else if (isL2CacheTagPresent(addr)) {
 207       return getL2CacheEntry(addr).CacheState;
 208     }
 209     return State:NP;
 210   }
 211
 212   std::string getStateStr(Address addr) {
 213     return L2Cache_State_to_string(getState(addr));
 214   }
 215
 216   // when is this called
 217   void setState(Address addr, State state) {
 218
 219     // MUST CHANGE
 220     if (L2_TBEs.isPresent(addr)) {
 221       L2_TBEs[addr].TBEState := state;
 222     }
 223
 224     if (isL2CacheTagPresent(addr)) {
 225       getL2CacheEntry(addr).CacheState := state;
 226
 227       // Set permission
 228       if (state == State:SS ) {
 229         changeL2Permission(addr, AccessPermission:Read_Only);
 230       } else if (state == State:M) {
 231         changeL2Permission(addr, AccessPermission:Read_Write);
 232       } else if (state == State:MT) {
 233         changeL2Permission(addr, AccessPermission:Stale);
 234       } else {
 235         changeL2Permission(addr, AccessPermission:Busy);
 236       }
 237     }
 238   }
 239
 240   Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr, MachineID requestor) {
 241     if(type == CoherenceRequestType:GETS) {
 242       return Event:L1_GETS;
 243     } else if(type == CoherenceRequestType:GET_INSTR) {
 244       return Event:L1_GET_INSTR;
 245     } else if (type == CoherenceRequestType:GETX) {
 246       return Event:L1_GETX;
 247     } else if (type == CoherenceRequestType:UPGRADE) {
 248       if ( isL2CacheTagPresent(addr) && getL2CacheEntry(addr).Sharers.isElement(requestor) ) {
 249         return Event:L1_UPGRADE;
 250       } else {
 251         return Event:L1_GETX;
 252       }
 253     } else if (type == CoherenceRequestType:PUTX) {
 254       if (isSharer(addr, requestor)) {
 255         return Event:L1_PUTX;
 256       } else {
 257         return Event:L1_PUTX_old;
 258       }
 259     } else {
 260       DEBUG_EXPR(addr);
 261       DEBUG_EXPR(type);
 262       error("Invalid L1 forwarded request type");
 263     }
 264   }
 265
 266   // ** OUT_PORTS **
 267
 268   out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache);
 269   out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache);
 270   out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache);
 271
 272
 273   // Response IntraChip L2 Network - response msg to this particular L2 bank
 274   in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache) {
 275     if (responseIntraChipL2Network_in.isReady()) {
 276       peek(responseIntraChipL2Network_in, ResponseMsg) {
 277         // test wether it's from a local L1 or an off chip source
 278         assert(in_msg.Destination.isElement(machineID));
 279         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 280           if(in_msg.Type == CoherenceResponseType:DATA) {
 281             if (in_msg.Dirty) {
 282               trigger(Event:WB_Data, in_msg.Address);
 283             } else {
 284               trigger(Event:WB_Data_clean, in_msg.Address);
 285             }
 286           } else if (in_msg.Type == CoherenceResponseType:ACK) {
 287             if ((L2_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0) {
 288               trigger(Event:Ack_all, in_msg.Address);
 289             } else {
 290               trigger(Event:Ack, in_msg.Address);
 291             }
 292           } else {
 293             error("unknown message type");
 294           }
 295
 296         } else { // external message
 297           if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
 298             trigger(Event:Mem_Data, in_msg.Address);  // L2 now has data and all off-chip acks
 299           } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
 300             trigger(Event:Mem_Ack, in_msg.Address);  // L2 now has data and all off-chip acks
 301           } else {
 302             error("unknown message type");
 303           }
 304         }
 305       }
 306     }  // if not ready, do nothing
 307   }
 308
 309   // L1 Request
 310   in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache) {
 311     if(L1RequestIntraChipL2Network_in.isReady()) {
 312       peek(L1RequestIntraChipL2Network_in,  RequestMsg) {
 313         DEBUG_EXPR(in_msg.Address);
 314         DEBUG_EXPR(id);
 315         DEBUG_EXPR(getState(in_msg.Address));
 316         DEBUG_EXPR(in_msg.Requestor);
 317         DEBUG_EXPR(in_msg.Type);
 318         DEBUG_EXPR(in_msg.Destination);
 319         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
 320         assert(in_msg.Destination.isElement(machineID));
 321         if (L2cacheMemory.isTagPresent(in_msg.Address)) {
 322           // The L2 contains the block, so proceeded with handling the request
 323           trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address, in_msg.Requestor), in_msg.Address);
 324         } else {
 325           if (L2cacheMemory.cacheAvail(in_msg.Address)) {
 326             // L2 does't have the line, but we have space for it in the L2
 327             trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address, in_msg.Requestor), in_msg.Address);
 328           } else {
 329             // No room in the L2, so we need to make room before handling the request
 330             if (L2cacheMemory[ L2cacheMemory.cacheProbe(in_msg.Address) ].Dirty ) {
 331               trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
 332             } else {
 333               trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address));
 334             }
 335           }
 336         }
 337       }
 338     }
 339   }
 340
 341   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache) {
 342     if(L1unblockNetwork_in.isReady()) {
 343       peek(L1unblockNetwork_in,  ResponseMsg) {
 344         assert(in_msg.Destination.isElement(machineID));
 345         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
 346           trigger(Event:Exclusive_Unblock, in_msg.Address);
 347         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
 348           trigger(Event:Unblock, in_msg.Address);
 349         } else {
 350           error("unknown unblock message");
 351         }
 352       }
 353     }
 354   }
 355
 356   // ACTIONS
 357
 358   action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
 359     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 360       enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency="L2_REQUEST_LATENCY") {
 361         out_msg.Address := address;
 362         out_msg.Type := CoherenceRequestType:GETS;
 363         out_msg.Requestor := machineID;
 364         out_msg.Destination.add(map_Address_to_Directory(address));
 365         out_msg.MessageSize := MessageSizeType:Control;
 366       }
 367     }
 368   }
 369
 370   action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
 371     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 372       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency="L2_REQUEST_LATENCY") {
 373         out_msg.Address := address;
 374         out_msg.Type := in_msg.Type;
 375         out_msg.Requestor := in_msg.Requestor;
 376         out_msg.Destination.add(L2cacheMemory[address].Exclusive);
 377         out_msg.MessageSize := MessageSizeType:Request_Control;
 378       }
 379     }
 380   }
 381
 382   action(c_exclusiveReplacement, "c", desc="Send data to memory") {
 383     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") {
 384       out_msg.Address := address;
 385       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 386       out_msg.Sender := machineID;
 387       out_msg.Destination.add(map_Address_to_Directory(address));
 388       out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 389       out_msg.Dirty := getL2CacheEntry(address).Dirty;
 390       out_msg.MessageSize := MessageSizeType:Response_Data;
 391     }
 392   }
 393
 394   action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
 395     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") {
 396       out_msg.Address := address;
 397       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 398       out_msg.Sender := machineID;
 399       out_msg.Destination.add(map_Address_to_Directory(address));
 400       out_msg.DataBlk := L2_TBEs[address].DataBlk;
 401       out_msg.Dirty := L2_TBEs[address].Dirty;
 402       out_msg.MessageSize := MessageSizeType:Response_Data;
 403     }
 404   }
 405
 406
 407   action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
 408     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 409       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") {
 410         out_msg.Address := address;
 411         out_msg.Type := CoherenceResponseType:DATA;
 412         out_msg.Sender := machineID;
 413         out_msg.Destination.add(in_msg.Requestor);
 414         out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 415         out_msg.Dirty := getL2CacheEntry(address).Dirty;
 416         out_msg.MessageSize := MessageSizeType:Response_Data;
 417
 418         out_msg.AckCount := 0 - getL2CacheEntry(address).Sharers.count();
 419         if (getL2CacheEntry(address).Sharers.isElement(in_msg.Requestor)) {
 420           out_msg.AckCount := out_msg.AckCount + 1;
 421         }
 422       }
 423     }
 424   }
 425
 426   action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
 427     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 428       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") {
 429         out_msg.Address := address;
 430         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 431         out_msg.Sender := machineID;
 432         out_msg.Destination.add(in_msg.Requestor);
 433         out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 434         out_msg.Dirty := getL2CacheEntry(address).Dirty;
 435         out_msg.MessageSize := MessageSizeType:Response_Data;
 436
 437         out_msg.AckCount := 0 - getL2CacheEntry(address).Sharers.count();
 438         if (getL2CacheEntry(address).Sharers.isElement(in_msg.Requestor)) {
 439           out_msg.AckCount := out_msg.AckCount + 1;
 440         }
 441       }
 442     }
 443   }
 444
 445   action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
 446     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 447       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_RESPONSE_LATENCY") {
 448         out_msg.Address := address;
 449         out_msg.Type := CoherenceResponseType:DATA;
 450         out_msg.Sender := machineID;
 451         out_msg.Destination.add(in_msg.Requestor);
 452         out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 453         out_msg.Dirty := getL2CacheEntry(address).Dirty;
 454         out_msg.MessageSize := MessageSizeType:Response_Data;
 455         out_msg.AckCount := 0;
 456       }
 457     }
 458   }
 459
 460   action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
 461     assert(L2_TBEs[address].L1_GetS_IDs.count() > 0);
 462     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="1") {
 463       out_msg.Address := address;
 464       out_msg.Type := CoherenceResponseType:DATA;
 465       //out_msg.Sender := machineID;
 466       out_msg.Sender := map_Address_to_Directory(address);
 467       out_msg.Destination := L2_TBEs[address].L1_GetS_IDs;  // internal nodes
 468       out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 469       out_msg.Dirty := getL2CacheEntry(address).Dirty;
 470       out_msg.MessageSize := MessageSizeType:Response_Data;
 471     }
 472   }
 473
 474   action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
 475     assert(L2_TBEs[address].L1_GetS_IDs.count() == 1);
 476     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="1") {
 477       out_msg.Address := address;
 478       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 479       // out_msg.Sender := machineID;
 480       out_msg.Sender := map_Address_to_Directory(address);
 481       out_msg.Destination := L2_TBEs[address].L1_GetS_IDs;  // internal nodes
 482       out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 483       out_msg.Dirty := getL2CacheEntry(address).Dirty;
 484       out_msg.MessageSize := MessageSizeType:Response_Data;
 485     }
 486   }
 487
 488
 489   action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
 490     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="1") {
 491       out_msg.Address := address;
 492       out_msg.Type := CoherenceResponseType:DATA;
 493       // out_msg.Sender := machineID;
 494       out_msg.Sender := map_Address_to_Directory(address);
 495       out_msg.Destination.add(L2_TBEs[address].L1_GetX_ID);
 496       DEBUG_EXPR(out_msg.Destination);
 497       out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
 498       out_msg.Dirty := getL2CacheEntry(address).Dirty;
 499       DEBUG_EXPR(out_msg.Address);
 500       DEBUG_EXPR(out_msg.Destination);
 501       DEBUG_EXPR(out_msg.DataBlk);
 502       out_msg.MessageSize := MessageSizeType:Response_Data;
 503     }
 504   }
 505
 506
 507   action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
 508     enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency="L2_REQUEST_LATENCY") {
 509       out_msg.Address := address;
 510       out_msg.Type := CoherenceRequestType:INV;
 511       out_msg.Requestor := machineID;
 512       out_msg.Destination := L2cacheMemory[address].Sharers;
 513       out_msg.MessageSize := MessageSizeType:Request_Control;
 514     }
 515   }
 516
 517   action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
 518     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 519       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency="L2_REQUEST_LATENCY") {
 520         out_msg.Address := address;
 521         out_msg.Type := CoherenceRequestType:INV;
 522         out_msg.Requestor := in_msg.Requestor;
 523         out_msg.Destination := L2cacheMemory[address].Sharers;
 524         out_msg.MessageSize := MessageSizeType:Request_Control;
 525       }
 526     }
 527   }
 528
 529
 530   action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
 531     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 532       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency="L2_REQUEST_LATENCY") {
 533         out_msg.Address := address;
 534         out_msg.Type := CoherenceRequestType:INV;
 535         out_msg.Requestor := in_msg.Requestor;
 536         out_msg.Destination := L2cacheMemory[address].Sharers;
 537         out_msg.Destination.remove(in_msg.Requestor);
 538         out_msg.MessageSize := MessageSizeType:Request_Control;
 539       }
 540     }
 541   }
 542
 543   // OTHER ACTIONS
 544   action(i_allocateTBE, "i", desc="Allocate TBE for internal/external request(isPrefetch=0, number of invalidates=0)") {
 545     check_allocate(L2_TBEs);
 546     L2_TBEs.allocate(address);
 547     L2_TBEs[address].L1_GetS_IDs.clear();
 548     L2_TBEs[address].DataBlk := getL2CacheEntry(address).DataBlk;
 549     L2_TBEs[address].Dirty := getL2CacheEntry(address).Dirty;
 550     L2_TBEs[address].pendingAcks := getL2CacheEntry(address).Sharers.count();
 551   }
 552
 553   action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
 554     L2_TBEs.deallocate(address);
 555   }
 556
 557   action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
 558     profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles());
 559   }
 560
 561   action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
 562     profileMsgDelay(0, L1unblockNetwork_in.dequeue_getDelayCycles());
 563   }
 564
 565
 566   action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
 567     profileMsgDelay(3, responseIntraChipL2Network_in.dequeue_getDelayCycles());
 568   }
 569
 570
 571   action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
 572     peek(responseIntraChipL2Network_in, ResponseMsg) {
 573       getL2CacheEntry(address).DataBlk := in_msg.DataBlk;
 574       getL2CacheEntry(address).Dirty := in_msg.Dirty;
 575     }
 576   }
 577
 578   action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
 579     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 580       getL2CacheEntry(address).DataBlk := in_msg.DataBlk;
 581       getL2CacheEntry(address).Dirty := in_msg.Dirty;
 582     }
 583   }
 584
 585   action(q_updateAck, "q", desc="update pending ack count") {
 586     peek(responseIntraChipL2Network_in, ResponseMsg) {
 587       L2_TBEs[address].pendingAcks := L2_TBEs[address].pendingAcks - in_msg.AckCount;
 588       APPEND_TRANSITION_COMMENT(in_msg.AckCount);
 589       APPEND_TRANSITION_COMMENT(" p: ");
 590       APPEND_TRANSITION_COMMENT(L2_TBEs[address].pendingAcks);
 591     }
 592   }
 593
 594   action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
 595     peek(responseIntraChipL2Network_in, ResponseMsg) {
 596       L2_TBEs[address].DataBlk := in_msg.DataBlk;
 597       L2_TBEs[address].Dirty := in_msg.Dirty;
 598     }
 599   }
 600
 601
 602   action(z_stall, "z", desc="Stall") {
 603   }
 604
 605
 606   action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
 607     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 608       L2_TBEs[address].L1_GetS_IDs.add(in_msg.Requestor);
 609     }
 610   }
 611
 612   action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
 613     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 614       L2_TBEs[address].L1_GetX_ID := in_msg.Requestor;
 615     }
 616   }
 617
 618   action(set_setMRU, "\set", desc="set the MRU entry") {
 619     L2cacheMemory.setMRU(address);
 620   }
 621
 622   action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
 623     if (L2cacheMemory.isTagPresent(address) == false) {
 624       L2cacheMemory.allocate(address);
 625     }
 626   }
 627
 628   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 629     L2cacheMemory.deallocate(address);
 630   }
 631
 632   action(t_sendWBAck, "t", desc="Send writeback ACK") {
 633     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 634       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="1") {
 635         out_msg.Address := address;
 636         out_msg.Type := CoherenceResponseType:WB_ACK;
 637         out_msg.Sender := machineID;
 638         out_msg.Destination.add(in_msg.Requestor);
 639         out_msg.MessageSize := MessageSizeType:Response_Control;
 640       }
 641     }
 642   }
 643
 644   action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
 645     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 646       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_REQUEST_LATENCY") {
 647         out_msg.Address := address;
 648         out_msg.Type := CoherenceResponseType:ACK;
 649         out_msg.Sender := machineID;
 650         out_msg.Destination.add(in_msg.Requestor);
 651         out_msg.MessageSize := MessageSizeType:Response_Control;
 652         // upgrader doesn't get ack from itself, hence the + 1
 653         out_msg.AckCount := 0 - getL2CacheEntry(address).Sharers.count() + 1;
 654       }
 655     }
 656   }
 657
 658   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
 659     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 660       //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor));
 661     }
 662   }
 663
 664   action(ww_profileMissNoDir, "\w", desc="Profile this transition at the L2 because Dir won't see the request") {
 665     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 666       // profile_request(in_msg.L1CacheStateStr, getStateStr(address), "NA", getCoherenceRequestTypeStr(in_msg.Type));
 667     }
 668   }
 669
 670
 671
 672   action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
 673     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 674       addSharer(address, in_msg.Requestor);
 675       APPEND_TRANSITION_COMMENT( getL2CacheEntry(address).Sharers );
 676     }
 677   }
 678
 679   action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
 680     peek(L1unblockNetwork_in, ResponseMsg) {
 681       addSharer(address, in_msg.Sender);
 682     }
 683   }
 684
 685
 686   action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
 687     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 688       L2cacheMemory[address].Sharers.remove(in_msg.Requestor);
 689     }
 690   }
 691
 692   action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
 693     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 694       L2cacheMemory[address].Sharers.clear();
 695     }
 696   }
 697
 698   action(mm_markExclusive, "\m", desc="set the exclusive owner") {
 699     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
 700       L2cacheMemory[address].Sharers.clear();
 701       L2cacheMemory[address].Exclusive := in_msg.Requestor;
 702       addSharer(address, in_msg.Requestor);
 703     }
 704   }
 705
 706   action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
 707     peek(L1unblockNetwork_in, ResponseMsg) {
 708       L2cacheMemory[address].Sharers.clear();
 709       L2cacheMemory[address].Exclusive := in_msg.Sender;
 710       addSharer(address, in_msg.Sender);
 711     }
 712   }
 713
 714   action(zz_recycleL1RequestQueue, "zz", desc="recycle L1 request queue") {
 715     L1RequestIntraChipL2Network_in.recycle();
 716   }
 717
 718   //*****************************************************
 719   // TRANSITIONS
 720   //*****************************************************
 721
 722
 723   //===============================================
 724   // BASE STATE - I
 725
 726   // Transitions from I (Idle)
 727   transition({NP, IS, ISS, IM, SS, M, M_I, MT_I, MCT_I, I_I, S_I, SS_MB, M_MB, MT_IIB, MT_IB, MT_SB}, L1_PUTX) {
 728     jj_popL1RequestQueue;
 729   }
 730
 731   transition({NP, SS, M, MT, M_I, MT_I, MCT_I, I_I, S_I, IS, ISS, IM, SS_MB, MT_MB, M_MB, MT_IIB, MT_IB, MT_SB}, L1_PUTX_old) {
 732     jj_popL1RequestQueue;
 733   }
 734
 735   transition({IM, IS, ISS, SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
 736     zz_recycleL1RequestQueue;
 737   }
 738
 739   transition({SS_MB, M_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
 740     zz_recycleL1RequestQueue;
 741   }
 742
 743
 744   transition(NP, L1_GETS,  ISS) {
 745     qq_allocateL2CacheBlock;
 746     ll_clearSharers;
 747     nn_addSharer;
 748     i_allocateTBE;
 749     ss_recordGetSL1ID;
 750     a_issueFetchToMemory;
 751     uu_profileMiss;
 752     jj_popL1RequestQueue;
 753   }
 754
 755   transition(NP, L1_GET_INSTR, IS) {
 756     qq_allocateL2CacheBlock;
 757     ll_clearSharers;
 758     nn_addSharer;
 759     i_allocateTBE;
 760     ss_recordGetSL1ID;
 761     a_issueFetchToMemory;
 762     uu_profileMiss;
 763     jj_popL1RequestQueue;
 764   }
 765
 766   transition(NP, L1_GETX, IM) {
 767     qq_allocateL2CacheBlock;
 768     ll_clearSharers;
 769     // nn_addSharer;
 770     i_allocateTBE;
 771     xx_recordGetXL1ID;
 772     a_issueFetchToMemory;
 773     uu_profileMiss;
 774     jj_popL1RequestQueue;
 775   }
 776
 777
 778   // transitions from IS/IM
 779
 780   transition(ISS, Mem_Data, MT_MB) {
 781     m_writeDataToCache;
 782     ex_sendExclusiveDataToGetSRequestors;
 783     s_deallocateTBE;
 784     o_popIncomingResponseQueue;
 785   }
 786
 787   // transition(IS, Mem_Data, SS) {
 788   transition(IS, Mem_Data, SS_MB) {
 789     m_writeDataToCache;
 790     e_sendDataToGetSRequestors;
 791     s_deallocateTBE;
 792     o_popIncomingResponseQueue;
 793   }
 794
 795   transition(IM, Mem_Data, MT_MB) {
 796     m_writeDataToCache;
 797     ee_sendDataToGetXRequestor;
 798     s_deallocateTBE;
 799     o_popIncomingResponseQueue;
 800   }
 801
 802 /*
 803   transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
 804     nn_addSharer;
 805     ss_recordGetSL1ID;
 806     uu_profileMiss;
 807     jj_popL1RequestQueue;
 808   }
 809 */
 810
 811   transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}) {
 812     zz_recycleL1RequestQueue;
 813   }
 814
 815   transition({IS, ISS}, L1_GETX) {
 816     zz_recycleL1RequestQueue;
 817   }
 818
 819   transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
 820     zz_recycleL1RequestQueue;
 821   }
 822
 823   // transitions from SS
 824   // transition(SS, {L1_GETS, L1_GET_INSTR}) {
 825   transition(SS, {L1_GETS, L1_GET_INSTR}, SS_MB) {
 826     ds_sendSharedDataToRequestor;
 827     nn_addSharer;
 828     uu_profileMiss;
 829     set_setMRU;
 830     jj_popL1RequestQueue;
 831   }
 832
 833
 834   transition(SS, L1_GETX, SS_MB) {
 835     d_sendDataToRequestor;
 836     // fw_sendFwdInvToSharers;
 837     fwm_sendFwdInvToSharersMinusRequestor;
 838     uu_profileMiss;
 839     set_setMRU;
 840     jj_popL1RequestQueue;
 841   }
 842
 843   transition(SS, L1_UPGRADE, SS_MB) {
 844     fwm_sendFwdInvToSharersMinusRequestor;
 845     ts_sendInvAckToUpgrader;
 846     uu_profileMiss;
 847     set_setMRU;
 848     jj_popL1RequestQueue;
 849   }
 850
 851   transition(SS, L2_Replacement_clean, I_I) {
 852     i_allocateTBE;
 853     f_sendInvToSharers;
 854     rr_deallocateL2CacheBlock;
 855   }
 856
 857   transition(SS, L2_Replacement, S_I) {
 858     i_allocateTBE;
 859     f_sendInvToSharers;
 860     rr_deallocateL2CacheBlock;
 861   }
 862
 863   transition(M, L1_GETX, MT_MB) {
 864     d_sendDataToRequestor;
 865     uu_profileMiss;
 866     set_setMRU;
 867     jj_popL1RequestQueue;
 868   }
 869
 870   // transition(M, L1_GET_INSTR, SS) {
 871   transition(M, L1_GET_INSTR, SS_MB) {
 872     d_sendDataToRequestor;
 873     nn_addSharer;
 874     uu_profileMiss;
 875     set_setMRU;
 876     jj_popL1RequestQueue;
 877   }
 878
 879   transition(M, L1_GETS, MT_MB) {
 880     dd_sendExclusiveDataToRequestor;
 881     uu_profileMiss;
 882     set_setMRU;
 883     jj_popL1RequestQueue;
 884   }
 885
 886   transition(M, L2_Replacement, M_I) {
 887     i_allocateTBE;
 888     c_exclusiveReplacement;
 889     rr_deallocateL2CacheBlock;
 890   }
 891
 892   transition(M, L2_Replacement_clean, M_I) {
 893     rr_deallocateL2CacheBlock;
 894   }
 895
 896
 897   // transitions from MT
 898
 899   transition(MT, L1_GETX, MT_MB) {
 900     b_forwardRequestToExclusive;
 901     uu_profileMiss;
 902     set_setMRU;
 903     jj_popL1RequestQueue;
 904   }
 905
 906
 907   transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
 908     b_forwardRequestToExclusive;
 909     uu_profileMiss;
 910     set_setMRU;
 911     jj_popL1RequestQueue;
 912   }
 913
 914   transition(MT, L2_Replacement, MT_I) {
 915     i_allocateTBE;
 916     f_sendInvToSharers;
 917     rr_deallocateL2CacheBlock;
 918   }
 919
 920   transition(MT, L2_Replacement_clean, MCT_I) {
 921     i_allocateTBE;
 922     f_sendInvToSharers;
 923     rr_deallocateL2CacheBlock;
 924   }
 925
 926   transition(MT, L1_PUTX, M) {
 927     ll_clearSharers;
 928     mr_writeDataToCacheFromRequest;
 929     t_sendWBAck;
 930     jj_popL1RequestQueue;
 931   }
 932
 933
 934   // transitions from blocking states
 935   transition(SS_MB, Unblock_Cancel, SS) {
 936     k_popUnblockQueue;
 937   }
 938
 939   transition(MT_MB, Unblock_Cancel, MT) {
 940     k_popUnblockQueue;
 941   }
 942
 943   transition(MT_IB, Unblock_Cancel, MT) {
 944     k_popUnblockQueue;
 945   }
 946
 947   transition(SS_MB, Exclusive_Unblock, MT) {
 948     // update actual directory
 949     mmu_markExclusiveFromUnblock;
 950     k_popUnblockQueue;
 951   }
 952
 953   transition(SS_MB, Unblock, SS) {
 954     k_popUnblockQueue;
 955   }
 956
 957   transition({M_MB, MT_MB}, Exclusive_Unblock, MT) {
 958     // update actual directory
 959     mmu_markExclusiveFromUnblock;
 960     k_popUnblockQueue;
 961   }
 962
 963   transition(MT_IIB, Unblock, MT_IB) {
 964     nnu_addSharerFromUnblock;
 965     k_popUnblockQueue;
 966   }
 967
 968   transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
 969     m_writeDataToCache;
 970     o_popIncomingResponseQueue;
 971   }
 972
 973   transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
 974     m_writeDataToCache;
 975     o_popIncomingResponseQueue;
 976   }
 977
 978   transition(MT_SB, Unblock, SS) {
 979     nnu_addSharerFromUnblock;
 980     k_popUnblockQueue;
 981   }
 982
 983   // writeback states
 984   transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
 985     zz_recycleL1RequestQueue;
 986   }
 987
 988   transition(I_I, Ack) {
 989     q_updateAck;
 990     o_popIncomingResponseQueue;
 991   }
 992
 993   transition(I_I, Ack_all, NP) {
 994     s_deallocateTBE;
 995     o_popIncomingResponseQueue;
 996   }
 997
 998   transition({MT_I, MCT_I}, WB_Data, M_I) {
 999     qq_writeDataToTBE;
1000     ct_exclusiveReplacementFromTBE;
1001     o_popIncomingResponseQueue;
1002   }
1003
1004   transition(MCT_I, WB_Data_clean, NP) {
1005     s_deallocateTBE;
1006     o_popIncomingResponseQueue;
1007   }
1008
1009   // L1 never changed Dirty data
1010   transition(MT_I, Ack_all, M_I) {
1011     ct_exclusiveReplacementFromTBE;
1012     o_popIncomingResponseQueue;
1013   }
1014
1015   // clean data that L1 exclusive never wrote
1016   transition(MCT_I, Ack_all, NP) {
1017     s_deallocateTBE;
1018     o_popIncomingResponseQueue;
1019   }
1020
1021   // drop this because L1 will send data again
1022   //  the reason we don't accept is that the request virtual network may be completely backed up
1023   // transition(MT_I, L1_PUTX) {
1024   //   jj_popL1RequestQueue;
1025   //}
1026
1027   // possible race between unblock and immediate replacement
1028   transition(MT_MB, L1_PUTX) {
1029     zz_recycleL1RequestQueue;
1030   }
1031
1032   transition(MT_I, WB_Data_clean, NP) {
1033     s_deallocateTBE;
1034     o_popIncomingResponseQueue;
1035   }
1036
1037   transition(S_I, Ack) {
1038     q_updateAck;
1039     o_popIncomingResponseQueue;
1040   }
1041
1042   transition(S_I, Ack_all, M_I) {
1043     ct_exclusiveReplacementFromTBE;
1044     o_popIncomingResponseQueue;
1045   }
1046
1047   transition(M_I, Mem_Ack, NP) {
1048     s_deallocateTBE;
1049     o_popIncomingResponseQueue;
1050   }
1051 }
1052