src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
  32  */
  33
  34 // This file is copied from Yasuko Watanabe's prefetch / memory protocol
  35 // Copied here by aep 12/14/07
  36
  37
  38 machine(Directory, "MESI_SCMP_bankdirectory protocol") {
  39
  40   MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
  41   MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false";
  42   MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false";
  43
  44   // STATES
  45   enumeration(State, desc="Directory states", default="Directory_State_I") {
  46     // Base states
  47     I, desc="Owner";
  48   }
  49
  50   // Events
  51   enumeration(Event, desc="Directory events") {
  52     Fetch, desc="A memory fetch arrives";
  53     Data, desc="writeback data arrives";
  54     Memory_Data, desc="Fetched data from memory arrives";
  55     Memory_Ack, desc="Writeback Ack from memory arrives";
  56   }
  57
  58   // TYPES
  59
  60   // DirectoryEntry
  61   structure(Entry, desc="...") {
  62     DataBlock DataBlk,             desc="data for the block";
  63   }
  64
  65   external_type(DirectoryMemory) {
  66     Entry lookup(Address);
  67     bool isPresent(Address);
  68   }
  69
  70   // to simulate detailed DRAM
  71   external_type(MemoryControl, inport="yes", outport="yes") {
  72
  73   }
  74
  75
  76   // ** OBJECTS **
  77
  78   DirectoryMemory directory, constructor_hack="i";
  79   MemoryControl memBuffer, constructor_hack="i";
  80
  81   State getState(Address addr) {
  82     return State:I;
  83   }
  84
  85   void setState(Address addr, State state) {
  86   }
  87
  88   bool isGETRequest(CoherenceRequestType type) {
  89     return (type == CoherenceRequestType:GETS) ||
  90       (type == CoherenceRequestType:GET_INSTR) ||
  91       (type == CoherenceRequestType:GETX);
  92   }
  93
  94
  95   // ** OUT_PORTS **
  96   out_port(responseNetwork_out, ResponseMsg, responseFromDir);
  97   out_port(memQueue_out, MemoryMsg, memBuffer);
  98
  99   // ** IN_PORTS **
 100
 101   in_port(requestNetwork_in, RequestMsg, requestToDir) {
 102     if (requestNetwork_in.isReady()) {
 103       peek(requestNetwork_in, RequestMsg) {
 104         assert(in_msg.Destination.isElement(machineID));
 105         if (isGETRequest(in_msg.Type)) {
 106           trigger(Event:Fetch, in_msg.Address);
 107         } else {
 108           DEBUG_EXPR(in_msg);
 109           error("Invalid message");
 110         }
 111       }
 112     }
 113   }
 114
 115   in_port(responseNetwork_in, ResponseMsg, responseToDir) {
 116     if (responseNetwork_in.isReady()) {
 117       peek(responseNetwork_in, ResponseMsg) {
 118         assert(in_msg.Destination.isElement(machineID));
 119         if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
 120           trigger(Event:Data, in_msg.Address);
 121         } else {
 122           DEBUG_EXPR(in_msg.Type);
 123           error("Invalid message");
 124         }
 125       }
 126     }
 127   }
 128
 129   // off-chip memory request/response is done
 130   in_port(memQueue_in, MemoryMsg, memBuffer) {
 131     if (memQueue_in.isReady()) {
 132       peek(memQueue_in, MemoryMsg) {
 133         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
 134           trigger(Event:Memory_Data, in_msg.Address);
 135         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
 136           trigger(Event:Memory_Ack, in_msg.Address);
 137         } else {
 138           DEBUG_EXPR(in_msg.Type);
 139           error("Invalid message");
 140         }
 141       }
 142     }
 143   }
 144
 145
 146
 147   // Actions
 148   action(a_sendAck, "a", desc="Send ack to L2") {
 149     peek(memQueue_in, MemoryMsg) {
 150       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 151         out_msg.Address := address;
 152         out_msg.Type := CoherenceResponseType:MEMORY_ACK;
 153         out_msg.Sender := machineID;
 154         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
 155         out_msg.MessageSize := MessageSizeType:Response_Control;
 156       }
 157     }
 158   }
 159
 160   action(d_sendData, "d", desc="Send data to requestor") {
 161     peek(memQueue_in, MemoryMsg) {
 162       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
 163         out_msg.Address := address;
 164         out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 165         out_msg.Sender := machineID;
 166         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
 167         out_msg.DataBlk := in_msg.DataBlk;
 168         out_msg.Dirty := false;
 169         out_msg.MessageSize := MessageSizeType:Response_Data;
 170       }
 171     }
 172   }
 173
 174   action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
 175     requestNetwork_in.dequeue();
 176   }
 177
 178   action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
 179     responseNetwork_in.dequeue();
 180   }
 181
 182   action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
 183     memQueue_in.dequeue();
 184   }
 185
 186   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
 187     peek(requestNetwork_in, RequestMsg) {
 188       enqueue(memQueue_out, MemoryMsg, latency="1") {
 189         out_msg.Address := address;
 190         out_msg.Type := MemoryRequestType:MEMORY_READ;
 191         out_msg.Sender := machineID;
 192         out_msg.OriginalRequestorMachId := in_msg.Requestor;
 193         out_msg.MessageSize := in_msg.MessageSize;
 194         out_msg.Prefetch := in_msg.Prefetch;
 195         out_msg.DataBlk := directory[in_msg.Address].DataBlk;
 196
 197         DEBUG_EXPR(out_msg);
 198       }
 199     }
 200   }
 201
 202   action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
 203     peek(responseNetwork_in, ResponseMsg) {
 204       enqueue(memQueue_out, MemoryMsg, latency="1") {
 205         out_msg.Address := address;
 206         out_msg.Type := MemoryRequestType:MEMORY_WB;
 207         out_msg.Sender := machineID;
 208         out_msg.OriginalRequestorMachId := in_msg.Sender;
 209         out_msg.DataBlk := in_msg.DataBlk;
 210         out_msg.MessageSize := in_msg.MessageSize;
 211         //out_msg.Prefetch := in_msg.Prefetch;
 212
 213         DEBUG_EXPR(out_msg);
 214       }
 215     }
 216   }
 217
 218   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
 219     peek(responseNetwork_in, ResponseMsg) {
 220       directory[in_msg.Address].DataBlk := in_msg.DataBlk;
 221       DEBUG_EXPR(in_msg.Address);
 222       DEBUG_EXPR(in_msg.DataBlk);
 223     }
 224   }
 225
 226   // TRANSITIONS
 227
 228   transition(I, Fetch) {
 229     //d_sendData;
 230     qf_queueMemoryFetchRequest;
 231     j_popIncomingRequestQueue;
 232   }
 233
 234   transition(I, Data) {
 235     m_writeDataToMemory;
 236     //a_sendAck;
 237     qw_queueMemoryWBRequest;
 238     k_popIncomingResponseQueue;
 239   }
 240
 241   transition(I, Memory_Data) {
 242     d_sendData;
 243     l_popMemQueue;
 244   }
 245
 246   transition(I, Memory_Ack) {
 247     a_sendAck;
 248     l_popMemQueue;
 249   }
 250 }