src/mem/protocol/MESI_Two_Level-L2cache.sm

   1 /*
   2  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 machine(L2Cache, "MESI Directory L2 Cache CMP")
  30  : CacheMemory * L2cache;
  31    Cycles l2_request_latency := 2;
  32    Cycles l2_response_latency := 2;
  33    Cycles to_l1_latency := 1;
  34
  35   // Message Queues
  36   // From local bank of L2 cache TO the network
  37   MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0",
  38     ordered="false", vnet_type="request";  // this L2 bank -> Memory
  39
  40   MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2",
  41     ordered="false", vnet_type="request";  // this L2 bank -> a local L1
  42
  43   MessageBuffer * responseFromL2Cache, network="To", virtual_network="1",
  44     ordered="false", vnet_type="response";  // this L2 bank -> a local L1 || Memory
  45
  46   // FROM the network to this local bank of L2 cache
  47   MessageBuffer * unblockToL2Cache, network="From", virtual_network="2",
  48     ordered="false", vnet_type="unblock";  // a local L1 || Memory -> this L2 bank
  49
  50   MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
  51     ordered="false", vnet_type="request";  // a local L1 -> this L2 bank
  52
  53   MessageBuffer * responseToL2Cache, network="From", virtual_network="1",
  54     ordered="false", vnet_type="response";  // a local L1 || Memory -> this L2 bank
  55 {
  56   // STATES
  57   state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
  58     // Base states
  59     NP, AccessPermission:Invalid, desc="Not present in either cache";
  60     SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
  61     M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
  62     MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
  63
  64     // L2 replacement
  65     M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
  66     MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
  67     MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
  68     I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
  69     S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
  70
  71     // Transient States for fetching data from memory
  72     ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
  73     IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
  74     IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
  75
  76     // Blocking states
  77     SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
  78     MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
  79
  80     MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
  81     MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
  82     MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data,  waiting for unblock";
  83
  84   }
  85
  86   // EVENTS
  87   enumeration(Event, desc="L2 Cache events") {
  88     // L2 events
  89
  90     // events initiated by the local L1s
  91     L1_GET_INSTR,            desc="a L1I GET INSTR request for a block maped to us";
  92     L1_GETS,                 desc="a L1D GETS request for a block maped to us";
  93     L1_GETX,                 desc="a L1D GETX request for a block maped to us";
  94     L1_UPGRADE,                 desc="a L1D GETX request for a block maped to us";
  95
  96     L1_PUTX,                 desc="L1 replacing data";
  97     L1_PUTX_old,             desc="L1 replacing data, but no longer sharer";
  98
  99     // events initiated by this L2
 100     L2_Replacement,     desc="L2 Replacement", format="!r";
 101     L2_Replacement_clean,     desc="L2 Replacement, but data is clean", format="!r";
 102
 103     // events from memory controller
 104     Mem_Data,     desc="data from memory", format="!r";
 105     Mem_Ack,     desc="ack from memory", format="!r";
 106
 107     // M->S data writeback
 108     WB_Data,  desc="data from L1";
 109     WB_Data_clean,  desc="clean data from L1";
 110     Ack,      desc="writeback ack";
 111     Ack_all,      desc="writeback ack";
 112
 113     Unblock, desc="Unblock from L1 requestor";
 114     Exclusive_Unblock, desc="Unblock from L1 requestor";
 115
 116     MEM_Inv, desc="Invalidation from directory";
 117   }
 118
 119   // TYPES
 120
 121   // CacheEntry
 122   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 123     State CacheState,          desc="cache state";
 124     NetDest Sharers,               desc="tracks the L1 shares on-chip";
 125     MachineID Exclusive,          desc="Exclusive holder of block";
 126     DataBlock DataBlk,       desc="data for the block";
 127     bool Dirty, default="false", desc="data is dirty";
 128   }
 129
 130   // TBE fields
 131   structure(TBE, desc="...") {
 132     Address Addr,            desc="Physical address for this TBE";
 133     State TBEState,             desc="Transient state";
 134     DataBlock DataBlk,          desc="Buffer for the data block";
 135     bool Dirty, default="false", desc="Data is Dirty";
 136
 137     NetDest L1_GetS_IDs,            desc="Set of the internal processors that want the block in shared state";
 138     MachineID L1_GetX_ID,          desc="ID of the L1 cache to forward the block to once we get a response";
 139     int pendingAcks,            desc="number of pending acks for invalidates during writeback";
 140   }
 141
 142   structure(TBETable, external="yes") {
 143     TBE lookup(Address);
 144     void allocate(Address);
 145     void deallocate(Address);
 146     bool isPresent(Address);
 147   }
 148
 149   TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 150
 151   void set_cache_entry(AbstractCacheEntry a);
 152   void unset_cache_entry();
 153   void set_tbe(TBE a);
 154   void unset_tbe();
 155   void wakeUpBuffers(Address a);
 156   void profileMsgDelay(int virtualNetworkType, Cycles c);
 157
 158   // inclusive cache, returns L2 entries only
 159   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 160     return static_cast(Entry, "pointer", L2cache[addr]);
 161   }
 162
 163   bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
 164     if (is_valid(cache_entry)) {
 165       return cache_entry.Sharers.isElement(requestor);
 166     } else {
 167       return false;
 168     }
 169   }
 170
 171   void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
 172     assert(is_valid(cache_entry));
 173     DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
 174             machineID, requestor, addr);
 175     cache_entry.Sharers.add(requestor);
 176   }
 177
 178   State getState(TBE tbe, Entry cache_entry, Address addr) {
 179     if(is_valid(tbe)) {
 180       return tbe.TBEState;
 181     } else if (is_valid(cache_entry)) {
 182       return cache_entry.CacheState;
 183     }
 184     return State:NP;
 185   }
 186
 187   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 188     // MUST CHANGE
 189     if (is_valid(tbe)) {
 190       tbe.TBEState := state;
 191     }
 192
 193     if (is_valid(cache_entry)) {
 194       cache_entry.CacheState := state;
 195     }
 196   }
 197
 198   AccessPermission getAccessPermission(Address addr) {
 199     TBE tbe := L2_TBEs[addr];
 200     if(is_valid(tbe)) {
 201       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
 202       return L2Cache_State_to_permission(tbe.TBEState);
 203     }
 204
 205     Entry cache_entry := getCacheEntry(addr);
 206     if(is_valid(cache_entry)) {
 207       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
 208       return L2Cache_State_to_permission(cache_entry.CacheState);
 209     }
 210
 211     DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
 212     return AccessPermission:NotPresent;
 213   }
 214
 215   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 216     TBE tbe := L2_TBEs[addr];
 217     if(is_valid(tbe)) {
 218         return tbe.DataBlk;
 219     }
 220
 221     return getCacheEntry(addr).DataBlk;
 222   }
 223
 224   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 225     if (is_valid(cache_entry)) {
 226       cache_entry.changePermission(L2Cache_State_to_permission(state));
 227     }
 228   }
 229
 230   Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
 231                                       MachineID requestor, Entry cache_entry) {
 232     if(type == CoherenceRequestType:GETS) {
 233       return Event:L1_GETS;
 234     } else if(type == CoherenceRequestType:GET_INSTR) {
 235       return Event:L1_GET_INSTR;
 236     } else if (type == CoherenceRequestType:GETX) {
 237       return Event:L1_GETX;
 238     } else if (type == CoherenceRequestType:UPGRADE) {
 239       if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
 240         return Event:L1_UPGRADE;
 241       } else {
 242         return Event:L1_GETX;
 243       }
 244     } else if (type == CoherenceRequestType:PUTX) {
 245       if (isSharer(addr, requestor, cache_entry)) {
 246         return Event:L1_PUTX;
 247       } else {
 248         return Event:L1_PUTX_old;
 249       }
 250     } else {
 251       DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
 252       error("Invalid L1 forwarded request type");
 253     }
 254   }
 255
 256   int getPendingAcks(TBE tbe) {
 257     return tbe.pendingAcks;
 258   }
 259
 260   bool isDirty(Entry cache_entry) {
 261     assert(is_valid(cache_entry));
 262     return cache_entry.Dirty;
 263   }
 264
 265   // ** OUT_PORTS **
 266
 267   out_port(L1RequestL2Network_out, RequestMsg, L1RequestFromL2Cache);
 268   out_port(DirRequestL2Network_out, RequestMsg, DirRequestFromL2Cache);
 269   out_port(responseL2Network_out, ResponseMsg, responseFromL2Cache);
 270
 271
 272   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
 273     if(L1unblockNetwork_in.isReady()) {
 274       peek(L1unblockNetwork_in,  ResponseMsg) {
 275         Entry cache_entry := getCacheEntry(in_msg.Addr);
 276         TBE tbe := L2_TBEs[in_msg.Addr];
 277         DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
 278                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
 279                 in_msg.Sender, in_msg.Type, in_msg.Destination);
 280
 281         assert(in_msg.Destination.isElement(machineID));
 282         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
 283           trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
 284         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
 285           trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
 286         } else {
 287           error("unknown unblock message");
 288         }
 289       }
 290     }
 291   }
 292
 293   // Response  L2 Network - response msg to this particular L2 bank
 294   in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
 295     if (responseL2Network_in.isReady()) {
 296       peek(responseL2Network_in, ResponseMsg) {
 297         // test wether it's from a local L1 or an off chip source
 298         assert(in_msg.Destination.isElement(machineID));
 299         Entry cache_entry := getCacheEntry(in_msg.Addr);
 300         TBE tbe := L2_TBEs[in_msg.Addr];
 301
 302         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 303           if(in_msg.Type == CoherenceResponseType:DATA) {
 304             if (in_msg.Dirty) {
 305               trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
 306             } else {
 307               trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
 308             }
 309           } else if (in_msg.Type == CoherenceResponseType:ACK) {
 310             if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
 311               trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
 312             } else {
 313               trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
 314             }
 315           } else {
 316             error("unknown message type");
 317           }
 318
 319         } else { // external message
 320           if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
 321               trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
 322           } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
 323               trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
 324           } else if(in_msg.Type == CoherenceResponseType:INV) {
 325               trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
 326           } else {
 327             error("unknown message type");
 328           }
 329         }
 330       }
 331     }  // if not ready, do nothing
 332   }
 333
 334   // L1 Request
 335   in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
 336     if(L1RequestL2Network_in.isReady()) {
 337       peek(L1RequestL2Network_in,  RequestMsg) {
 338         Entry cache_entry := getCacheEntry(in_msg.Addr);
 339         TBE tbe := L2_TBEs[in_msg.Addr];
 340
 341         DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
 342                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
 343                 in_msg.Requestor, in_msg.Type, in_msg.Destination);
 344
 345         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
 346         assert(in_msg.Destination.isElement(machineID));
 347
 348         if (is_valid(cache_entry)) {
 349           // The L2 contains the block, so proceeded with handling the request
 350           trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
 351                                                 in_msg.Requestor, cache_entry),
 352                   in_msg.Addr, cache_entry, tbe);
 353         } else {
 354           if (L2cache.cacheAvail(in_msg.Addr)) {
 355             // L2 does't have the line, but we have space for it in the L2
 356             trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
 357                                                   in_msg.Requestor, cache_entry),
 358                     in_msg.Addr, cache_entry, tbe);
 359           } else {
 360             // No room in the L2, so we need to make room before handling the request
 361             Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
 362             if (isDirty(L2cache_entry)) {
 363               trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
 364                       L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
 365             } else {
 366               trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
 367                       L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
 368             }
 369           }
 370         }
 371       }
 372     }
 373   }
 374
 375
 376   // ACTIONS
 377
 378   action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
 379     peek(L1RequestL2Network_in, RequestMsg) {
 380       enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
 381         out_msg.Addr := address;
 382         out_msg.Type := CoherenceRequestType:GETS;
 383         out_msg.Requestor := machineID;
 384         out_msg.Destination.add(map_Address_to_Directory(address));
 385         out_msg.MessageSize := MessageSizeType:Control;
 386       }
 387     }
 388   }
 389
 390   action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
 391     peek(L1RequestL2Network_in, RequestMsg) {
 392       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 393         assert(is_valid(cache_entry));
 394         out_msg.Addr := address;
 395         out_msg.Type := in_msg.Type;
 396         out_msg.Requestor := in_msg.Requestor;
 397         out_msg.Destination.add(cache_entry.Exclusive);
 398         out_msg.MessageSize := MessageSizeType:Request_Control;
 399       }
 400     }
 401   }
 402
 403   action(c_exclusiveReplacement, "c", desc="Send data to memory") {
 404     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 405       assert(is_valid(cache_entry));
 406       out_msg.Addr := address;
 407       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 408       out_msg.Sender := machineID;
 409       out_msg.Destination.add(map_Address_to_Directory(address));
 410       out_msg.DataBlk := cache_entry.DataBlk;
 411       out_msg.Dirty := cache_entry.Dirty;
 412       out_msg.MessageSize := MessageSizeType:Response_Data;
 413     }
 414   }
 415
 416   action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
 417     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 418       out_msg.Addr := address;
 419       out_msg.Type := CoherenceResponseType:ACK;
 420       out_msg.Sender := machineID;
 421       out_msg.Destination.add(map_Address_to_Directory(address));
 422       out_msg.MessageSize := MessageSizeType:Response_Control;
 423     }
 424   }
 425
 426   action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
 427     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 428       assert(is_valid(tbe));
 429       out_msg.Addr := address;
 430       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 431       out_msg.Sender := machineID;
 432       out_msg.Destination.add(map_Address_to_Directory(address));
 433       out_msg.DataBlk := tbe.DataBlk;
 434       out_msg.Dirty := tbe.Dirty;
 435       out_msg.MessageSize := MessageSizeType:Response_Data;
 436     }
 437   }
 438
 439   action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
 440     peek(L1RequestL2Network_in, RequestMsg) {
 441       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 442         assert(is_valid(cache_entry));
 443         out_msg.Addr := address;
 444         out_msg.Type := CoherenceResponseType:DATA;
 445         out_msg.Sender := machineID;
 446         out_msg.Destination.add(in_msg.Requestor);
 447         out_msg.DataBlk := cache_entry.DataBlk;
 448         out_msg.MessageSize := MessageSizeType:Response_Data;
 449
 450         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 451         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 452           out_msg.AckCount := out_msg.AckCount + 1;
 453         }
 454       }
 455     }
 456   }
 457
 458   action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
 459     peek(L1RequestL2Network_in, RequestMsg) {
 460       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 461         assert(is_valid(cache_entry));
 462         out_msg.Addr := address;
 463         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 464         out_msg.Sender := machineID;
 465         out_msg.Destination.add(in_msg.Requestor);
 466         out_msg.DataBlk := cache_entry.DataBlk;
 467         out_msg.MessageSize := MessageSizeType:Response_Data;
 468
 469         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 470         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 471           out_msg.AckCount := out_msg.AckCount + 1;
 472         }
 473       }
 474     }
 475   }
 476
 477   action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
 478     peek(L1RequestL2Network_in, RequestMsg) {
 479       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 480         assert(is_valid(cache_entry));
 481         out_msg.Addr := address;
 482         out_msg.Type := CoherenceResponseType:DATA;
 483         out_msg.Sender := machineID;
 484         out_msg.Destination.add(in_msg.Requestor);
 485         out_msg.DataBlk := cache_entry.DataBlk;
 486         out_msg.MessageSize := MessageSizeType:Response_Data;
 487         out_msg.AckCount := 0;
 488       }
 489     }
 490   }
 491
 492   action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
 493     assert(is_valid(tbe));
 494     assert(tbe.L1_GetS_IDs.count() > 0);
 495     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 496       assert(is_valid(cache_entry));
 497       out_msg.Addr := address;
 498       out_msg.Type := CoherenceResponseType:DATA;
 499       out_msg.Sender := machineID;
 500       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 501       out_msg.DataBlk := cache_entry.DataBlk;
 502       out_msg.MessageSize := MessageSizeType:Response_Data;
 503     }
 504   }
 505
 506   action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
 507     assert(is_valid(tbe));
 508     assert(tbe.L1_GetS_IDs.count() == 1);
 509     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 510       assert(is_valid(cache_entry));
 511       out_msg.Addr := address;
 512       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 513       out_msg.Sender := machineID;
 514       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 515       out_msg.DataBlk := cache_entry.DataBlk;
 516       out_msg.MessageSize := MessageSizeType:Response_Data;
 517     }
 518   }
 519
 520   action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
 521     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 522       assert(is_valid(tbe));
 523       assert(is_valid(cache_entry));
 524       out_msg.Addr := address;
 525       out_msg.Type := CoherenceResponseType:DATA;
 526       out_msg.Sender := machineID;
 527       out_msg.Destination.add(tbe.L1_GetX_ID);
 528       DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 529       out_msg.DataBlk := cache_entry.DataBlk;
 530       DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
 531               out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
 532       out_msg.MessageSize := MessageSizeType:Response_Data;
 533     }
 534   }
 535
 536   action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
 537     enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 538       assert(is_valid(cache_entry));
 539       out_msg.Addr := address;
 540       out_msg.Type := CoherenceRequestType:INV;
 541       out_msg.Requestor := machineID;
 542       out_msg.Destination := cache_entry.Sharers;
 543       out_msg.MessageSize := MessageSizeType:Request_Control;
 544     }
 545   }
 546
 547   action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
 548     peek(L1RequestL2Network_in, RequestMsg) {
 549       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 550         assert(is_valid(cache_entry));
 551         out_msg.Addr := address;
 552         out_msg.Type := CoherenceRequestType:INV;
 553         out_msg.Requestor := in_msg.Requestor;
 554         out_msg.Destination := cache_entry.Sharers;
 555         out_msg.MessageSize := MessageSizeType:Request_Control;
 556       }
 557     }
 558   }
 559
 560   action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
 561     peek(L1RequestL2Network_in, RequestMsg) {
 562       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 563         assert(is_valid(cache_entry));
 564         out_msg.Addr := address;
 565         out_msg.Type := CoherenceRequestType:INV;
 566         out_msg.Requestor := in_msg.Requestor;
 567         out_msg.Destination := cache_entry.Sharers;
 568         out_msg.Destination.remove(in_msg.Requestor);
 569         out_msg.MessageSize := MessageSizeType:Request_Control;
 570       }
 571     }
 572   }
 573
 574   // OTHER ACTIONS
 575   action(i_allocateTBE, "i", desc="Allocate TBE for request") {
 576     check_allocate(L2_TBEs);
 577     assert(is_valid(cache_entry));
 578     L2_TBEs.allocate(address);
 579     set_tbe(L2_TBEs[address]);
 580     tbe.L1_GetS_IDs.clear();
 581     tbe.DataBlk := cache_entry.DataBlk;
 582     tbe.Dirty := cache_entry.Dirty;
 583     tbe.pendingAcks := cache_entry.Sharers.count();
 584   }
 585
 586   action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
 587     L2_TBEs.deallocate(address);
 588     unset_tbe();
 589   }
 590
 591   action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
 592     profileMsgDelay(0, L1RequestL2Network_in.dequeue());
 593   }
 594
 595   action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
 596     profileMsgDelay(0, L1unblockNetwork_in.dequeue());
 597   }
 598
 599   action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
 600     profileMsgDelay(1, responseL2Network_in.dequeue());
 601   }
 602
 603   action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
 604     peek(responseL2Network_in, ResponseMsg) {
 605       assert(is_valid(cache_entry));
 606       cache_entry.DataBlk := in_msg.DataBlk;
 607       if (in_msg.Dirty) {
 608         cache_entry.Dirty := in_msg.Dirty;
 609       }
 610     }
 611   }
 612
 613   action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
 614     peek(L1RequestL2Network_in, RequestMsg) {
 615       assert(is_valid(cache_entry));
 616       cache_entry.DataBlk := in_msg.DataBlk;
 617       if (in_msg.Dirty) {
 618         cache_entry.Dirty := in_msg.Dirty;
 619       }
 620     }
 621   }
 622
 623   action(q_updateAck, "q", desc="update pending ack count") {
 624     peek(responseL2Network_in, ResponseMsg) {
 625       assert(is_valid(tbe));
 626       tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
 627       APPEND_TRANSITION_COMMENT(in_msg.AckCount);
 628       APPEND_TRANSITION_COMMENT(" p: ");
 629       APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
 630     }
 631   }
 632
 633   action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
 634     peek(responseL2Network_in, ResponseMsg) {
 635       assert(is_valid(tbe));
 636       tbe.DataBlk := in_msg.DataBlk;
 637       tbe.Dirty := in_msg.Dirty;
 638     }
 639   }
 640
 641   action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
 642     peek(L1RequestL2Network_in, RequestMsg) {
 643       assert(is_valid(tbe));
 644       tbe.L1_GetS_IDs.add(in_msg.Requestor);
 645     }
 646   }
 647
 648   action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
 649     peek(L1RequestL2Network_in, RequestMsg) {
 650       assert(is_valid(tbe));
 651       tbe.L1_GetX_ID := in_msg.Requestor;
 652     }
 653   }
 654
 655   action(set_setMRU, "\set", desc="set the MRU entry") {
 656     L2cache.setMRU(address);
 657   }
 658
 659   action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
 660     if (is_invalid(cache_entry)) {
 661       set_cache_entry(L2cache.allocate(address, new Entry));
 662     }
 663   }
 664
 665   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 666     L2cache.deallocate(address);
 667     unset_cache_entry();
 668   }
 669
 670   action(t_sendWBAck, "t", desc="Send writeback ACK") {
 671     peek(L1RequestL2Network_in, RequestMsg) {
 672       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 673         out_msg.Addr := address;
 674         out_msg.Type := CoherenceResponseType:WB_ACK;
 675         out_msg.Sender := machineID;
 676         out_msg.Destination.add(in_msg.Requestor);
 677         out_msg.MessageSize := MessageSizeType:Response_Control;
 678       }
 679     }
 680   }
 681
 682   action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
 683     peek(L1RequestL2Network_in, RequestMsg) {
 684       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 685         assert(is_valid(cache_entry));
 686         out_msg.Addr := address;
 687         out_msg.Type := CoherenceResponseType:ACK;
 688         out_msg.Sender := machineID;
 689         out_msg.Destination.add(in_msg.Requestor);
 690         out_msg.MessageSize := MessageSizeType:Response_Control;
 691         // upgrader doesn't get ack from itself, hence the + 1
 692         out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
 693       }
 694     }
 695   }
 696
 697   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
 698       ++L2cache.demand_misses;
 699   }
 700
 701   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
 702       ++L2cache.demand_hits;
 703   }
 704
 705   action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
 706     peek(L1RequestL2Network_in, RequestMsg) {
 707       assert(is_valid(cache_entry));
 708       addSharer(address, in_msg.Requestor, cache_entry);
 709       APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
 710     }
 711   }
 712
 713   action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
 714     peek(L1unblockNetwork_in, ResponseMsg) {
 715       assert(is_valid(cache_entry));
 716       addSharer(address, in_msg.Sender, cache_entry);
 717     }
 718   }
 719
 720   action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
 721     peek(L1RequestL2Network_in, RequestMsg) {
 722       assert(is_valid(cache_entry));
 723       cache_entry.Sharers.remove(in_msg.Requestor);
 724     }
 725   }
 726
 727   action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
 728     peek(L1RequestL2Network_in, RequestMsg) {
 729       assert(is_valid(cache_entry));
 730       cache_entry.Sharers.clear();
 731     }
 732   }
 733
 734   action(mm_markExclusive, "\m", desc="set the exclusive owner") {
 735     peek(L1RequestL2Network_in, RequestMsg) {
 736       assert(is_valid(cache_entry));
 737       cache_entry.Sharers.clear();
 738       cache_entry.Exclusive := in_msg.Requestor;
 739       addSharer(address, in_msg.Requestor, cache_entry);
 740     }
 741   }
 742
 743   action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
 744     peek(L1unblockNetwork_in, ResponseMsg) {
 745       assert(is_valid(cache_entry));
 746       cache_entry.Sharers.clear();
 747       cache_entry.Exclusive := in_msg.Sender;
 748       addSharer(address, in_msg.Sender, cache_entry);
 749     }
 750   }
 751
 752   action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
 753     stall_and_wait(L1RequestL2Network_in, address);
 754   }
 755
 756   action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
 757     responseL2Network_in.recycle();
 758   }
 759
 760   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
 761     wakeUpBuffers(address);
 762   }
 763
 764   //*****************************************************
 765   // TRANSITIONS
 766   //*****************************************************
 767
 768
 769   //===============================================
 770   // BASE STATE - I
 771
 772   // Transitions from I (Idle)
 773   transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
 774     t_sendWBAck;
 775     jj_popL1RequestQueue;
 776   }
 777
 778   transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
 779     t_sendWBAck;
 780     jj_popL1RequestQueue;
 781   }
 782
 783   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
 784     zz_stallAndWaitL1RequestQueue;
 785   }
 786
 787   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
 788     zn_recycleResponseNetwork;
 789   }
 790
 791   transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
 792     o_popIncomingResponseQueue;
 793   }
 794
 795
 796   transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
 797     zz_stallAndWaitL1RequestQueue;
 798   }
 799
 800
 801   transition(NP, L1_GETS,  ISS) {
 802     qq_allocateL2CacheBlock;
 803     ll_clearSharers;
 804     nn_addSharer;
 805     i_allocateTBE;
 806     ss_recordGetSL1ID;
 807     a_issueFetchToMemory;
 808     uu_profileMiss;
 809     jj_popL1RequestQueue;
 810   }
 811
 812   transition(NP, L1_GET_INSTR, IS) {
 813     qq_allocateL2CacheBlock;
 814     ll_clearSharers;
 815     nn_addSharer;
 816     i_allocateTBE;
 817     ss_recordGetSL1ID;
 818     a_issueFetchToMemory;
 819     uu_profileMiss;
 820     jj_popL1RequestQueue;
 821   }
 822
 823   transition(NP, L1_GETX, IM) {
 824     qq_allocateL2CacheBlock;
 825     ll_clearSharers;
 826     // nn_addSharer;
 827     i_allocateTBE;
 828     xx_recordGetXL1ID;
 829     a_issueFetchToMemory;
 830     uu_profileMiss;
 831     jj_popL1RequestQueue;
 832   }
 833
 834
 835   // transitions from IS/IM
 836
 837   transition(ISS, Mem_Data, MT_MB) {
 838     m_writeDataToCache;
 839     ex_sendExclusiveDataToGetSRequestors;
 840     s_deallocateTBE;
 841     o_popIncomingResponseQueue;
 842   }
 843
 844   transition(IS, Mem_Data, SS) {
 845     m_writeDataToCache;
 846     e_sendDataToGetSRequestors;
 847     s_deallocateTBE;
 848     o_popIncomingResponseQueue;
 849     kd_wakeUpDependents;
 850   }
 851
 852   transition(IM, Mem_Data, MT_MB) {
 853     m_writeDataToCache;
 854     ee_sendDataToGetXRequestor;
 855     s_deallocateTBE;
 856     o_popIncomingResponseQueue;
 857   }
 858
 859   transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
 860     nn_addSharer;
 861     ss_recordGetSL1ID;
 862     uu_profileMiss;
 863     jj_popL1RequestQueue;
 864   }
 865
 866   transition({IS, ISS}, L1_GETX) {
 867     zz_stallAndWaitL1RequestQueue;
 868   }
 869
 870   transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
 871     zz_stallAndWaitL1RequestQueue;
 872   }
 873
 874   // transitions from SS
 875   transition(SS, {L1_GETS, L1_GET_INSTR}) {
 876     ds_sendSharedDataToRequestor;
 877     nn_addSharer;
 878     set_setMRU;
 879     uu_profileHit;
 880     jj_popL1RequestQueue;
 881   }
 882
 883
 884   transition(SS, L1_GETX, SS_MB) {
 885     d_sendDataToRequestor;
 886     // fw_sendFwdInvToSharers;
 887     fwm_sendFwdInvToSharersMinusRequestor;
 888     set_setMRU;
 889     uu_profileHit;
 890     jj_popL1RequestQueue;
 891   }
 892
 893   transition(SS, L1_UPGRADE, SS_MB) {
 894     fwm_sendFwdInvToSharersMinusRequestor;
 895     ts_sendInvAckToUpgrader;
 896     set_setMRU;
 897     uu_profileHit;
 898     jj_popL1RequestQueue;
 899   }
 900
 901   transition(SS, L2_Replacement_clean, I_I) {
 902     i_allocateTBE;
 903     f_sendInvToSharers;
 904     rr_deallocateL2CacheBlock;
 905   }
 906
 907   transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
 908     i_allocateTBE;
 909     f_sendInvToSharers;
 910     rr_deallocateL2CacheBlock;
 911   }
 912
 913
 914   transition(M, L1_GETX, MT_MB) {
 915     d_sendDataToRequestor;
 916     set_setMRU;
 917     uu_profileHit;
 918     jj_popL1RequestQueue;
 919   }
 920
 921   transition(M, L1_GET_INSTR, SS) {
 922     d_sendDataToRequestor;
 923     nn_addSharer;
 924     set_setMRU;
 925     uu_profileHit;
 926     jj_popL1RequestQueue;
 927   }
 928
 929   transition(M, L1_GETS, MT_MB) {
 930     dd_sendExclusiveDataToRequestor;
 931     set_setMRU;
 932     uu_profileHit;
 933     jj_popL1RequestQueue;
 934   }
 935
 936   transition(M, {L2_Replacement, MEM_Inv}, M_I) {
 937     i_allocateTBE;
 938     c_exclusiveReplacement;
 939     rr_deallocateL2CacheBlock;
 940   }
 941
 942   transition(M, L2_Replacement_clean, M_I) {
 943     i_allocateTBE;
 944     c_exclusiveCleanReplacement;
 945     rr_deallocateL2CacheBlock;
 946   }
 947
 948
 949   // transitions from MT
 950
 951   transition(MT, L1_GETX, MT_MB) {
 952     b_forwardRequestToExclusive;
 953     uu_profileMiss;
 954     set_setMRU;
 955     jj_popL1RequestQueue;
 956   }
 957
 958
 959   transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
 960     b_forwardRequestToExclusive;
 961     uu_profileMiss;
 962     set_setMRU;
 963     jj_popL1RequestQueue;
 964   }
 965
 966   transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
 967     i_allocateTBE;
 968     f_sendInvToSharers;
 969     rr_deallocateL2CacheBlock;
 970   }
 971
 972   transition(MT, L2_Replacement_clean, MCT_I) {
 973     i_allocateTBE;
 974     f_sendInvToSharers;
 975     rr_deallocateL2CacheBlock;
 976   }
 977
 978   transition(MT, L1_PUTX, M) {
 979     ll_clearSharers;
 980     mr_writeDataToCacheFromRequest;
 981     t_sendWBAck;
 982     jj_popL1RequestQueue;
 983   }
 984
 985   transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
 986     // update actual directory
 987     mmu_markExclusiveFromUnblock;
 988     k_popUnblockQueue;
 989     kd_wakeUpDependents;
 990   }
 991
 992   transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
 993     zz_stallAndWaitL1RequestQueue;
 994   }
 995
 996   transition(MT_IIB, Unblock, MT_IB) {
 997     nnu_addSharerFromUnblock;
 998     k_popUnblockQueue;
 999   }
1000
1001   transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
1002     m_writeDataToCache;
1003     o_popIncomingResponseQueue;
1004   }
1005
1006   transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
1007     m_writeDataToCache;
1008     o_popIncomingResponseQueue;
1009     kd_wakeUpDependents;
1010   }
1011
1012   transition(MT_SB, Unblock, SS) {
1013     nnu_addSharerFromUnblock;
1014     k_popUnblockQueue;
1015     kd_wakeUpDependents;
1016   }
1017
1018   // writeback states
1019   transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
1020     zz_stallAndWaitL1RequestQueue;
1021   }
1022
1023   transition(I_I, Ack) {
1024     q_updateAck;
1025     o_popIncomingResponseQueue;
1026   }
1027
1028   transition(I_I, Ack_all, M_I) {
1029     c_exclusiveCleanReplacement;
1030     o_popIncomingResponseQueue;
1031   }
1032
1033   transition({MT_I, MCT_I}, WB_Data, M_I) {
1034     qq_writeDataToTBE;
1035     ct_exclusiveReplacementFromTBE;
1036     o_popIncomingResponseQueue;
1037   }
1038
1039   transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
1040     c_exclusiveCleanReplacement;
1041     o_popIncomingResponseQueue;
1042   }
1043
1044   transition(MCT_I,  {L1_PUTX, L1_PUTX_old}){
1045     zz_stallAndWaitL1RequestQueue;
1046   }
1047
1048   // L1 never changed Dirty data
1049   transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
1050     ct_exclusiveReplacementFromTBE;
1051     o_popIncomingResponseQueue;
1052   }
1053
1054   transition(MT_I, {L1_PUTX, L1_PUTX_old}){
1055     zz_stallAndWaitL1RequestQueue;
1056   }
1057
1058   // possible race between unblock and immediate replacement
1059   transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
1060     zz_stallAndWaitL1RequestQueue;
1061   }
1062
1063   transition(S_I, Ack) {
1064     q_updateAck;
1065     o_popIncomingResponseQueue;
1066   }
1067
1068   transition(S_I, Ack_all, M_I) {
1069     ct_exclusiveReplacementFromTBE;
1070     o_popIncomingResponseQueue;
1071   }
1072
1073   transition(M_I, Mem_Ack, NP) {
1074     s_deallocateTBE;
1075     o_popIncomingResponseQueue;
1076     kd_wakeUpDependents;
1077   }
1078 }