src/mem/protocol/MESI_Two_Level-L2cache.sm

   1 /*
   2  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
  31  *
  32  */
  33
  34 machine(L2Cache, "MESI Directory L2 Cache CMP")
  35  : CacheMemory * L2cache,
  36    Cycles l2_request_latency = 2,
  37    Cycles l2_response_latency = 2,
  38    Cycles to_l1_latency = 1
  39 {
  40   // L2 BANK QUEUES
  41   // From local bank of L2 cache TO the network
  42   MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0",
  43     ordered="false", vnet_type="request";  // this L2 bank -> Memory
  44   MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0",
  45     ordered="false", vnet_type="request";  // this L2 bank -> a local L1
  46   MessageBuffer responseFromL2Cache, network="To", virtual_network="1",
  47     ordered="false", vnet_type="response";  // this L2 bank -> a local L1 || Memory
  48
  49   // FROM the network to this local bank of L2 cache
  50   MessageBuffer unblockToL2Cache, network="From", virtual_network="2",
  51     ordered="false", vnet_type="unblock";  // a local L1 || Memory -> this L2 bank
  52   MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0",
  53     ordered="false", vnet_type="request";  // a local L1 -> this L2 bank
  54   MessageBuffer responseToL2Cache, network="From", virtual_network="1",
  55     ordered="false", vnet_type="response";  // a local L1 || Memory -> this L2 bank
  56
  57   // STATES
  58   state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
  59     // Base states
  60     NP, AccessPermission:Invalid, desc="Not present in either cache";
  61     SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
  62     M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
  63     MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
  64
  65     // L2 replacement
  66     M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
  67     MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
  68     MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
  69     I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
  70     S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
  71
  72     // Transient States for fetching data from memory
  73     ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
  74     IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
  75     IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
  76
  77     // Blocking states
  78     SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
  79     MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
  80
  81     MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
  82     MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
  83     MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data,  waiting for unblock";
  84
  85   }
  86
  87   // EVENTS
  88   enumeration(Event, desc="L2 Cache events") {
  89     // L2 events
  90
  91     // events initiated by the local L1s
  92     L1_GET_INSTR,            desc="a L1I GET INSTR request for a block maped to us";
  93     L1_GETS,                 desc="a L1D GETS request for a block maped to us";
  94     L1_GETX,                 desc="a L1D GETX request for a block maped to us";
  95     L1_UPGRADE,                 desc="a L1D GETX request for a block maped to us";
  96
  97     L1_PUTX,                 desc="L1 replacing data";
  98     L1_PUTX_old,             desc="L1 replacing data, but no longer sharer";
  99
 100     // events initiated by this L2
 101     L2_Replacement,     desc="L2 Replacement", format="!r";
 102     L2_Replacement_clean,     desc="L2 Replacement, but data is clean", format="!r";
 103
 104     // events from memory controller
 105     Mem_Data,     desc="data from memory", format="!r";
 106     Mem_Ack,     desc="ack from memory", format="!r";
 107
 108     // M->S data writeback
 109     WB_Data,  desc="data from L1";
 110     WB_Data_clean,  desc="clean data from L1";
 111     Ack,      desc="writeback ack";
 112     Ack_all,      desc="writeback ack";
 113
 114     Unblock, desc="Unblock from L1 requestor";
 115     Exclusive_Unblock, desc="Unblock from L1 requestor";
 116
 117     MEM_Inv, desc="Invalidation from directory";
 118   }
 119
 120   // TYPES
 121
 122   // CacheEntry
 123   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 124     State CacheState,          desc="cache state";
 125     NetDest Sharers,               desc="tracks the L1 shares on-chip";
 126     MachineID Exclusive,          desc="Exclusive holder of block";
 127     DataBlock DataBlk,       desc="data for the block";
 128     bool Dirty, default="false", desc="data is dirty";
 129   }
 130
 131   // TBE fields
 132   structure(TBE, desc="...") {
 133     Address Addr,            desc="Physical address for this TBE";
 134     State TBEState,             desc="Transient state";
 135     DataBlock DataBlk,          desc="Buffer for the data block";
 136     bool Dirty, default="false", desc="Data is Dirty";
 137
 138     NetDest L1_GetS_IDs,            desc="Set of the internal processors that want the block in shared state";
 139     MachineID L1_GetX_ID,          desc="ID of the L1 cache to forward the block to once we get a response";
 140     int pendingAcks,            desc="number of pending acks for invalidates during writeback";
 141   }
 142
 143   structure(TBETable, external="yes") {
 144     TBE lookup(Address);
 145     void allocate(Address);
 146     void deallocate(Address);
 147     bool isPresent(Address);
 148   }
 149
 150   TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 151
 152   void set_cache_entry(AbstractCacheEntry a);
 153   void unset_cache_entry();
 154   void set_tbe(TBE a);
 155   void unset_tbe();
 156   void wakeUpBuffers(Address a);
 157   void profileMsgDelay(int virtualNetworkType, Cycles c);
 158
 159   // inclusive cache, returns L2 entries only
 160   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 161     return static_cast(Entry, "pointer", L2cache[addr]);
 162   }
 163
 164   bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
 165     if (is_valid(cache_entry)) {
 166       return cache_entry.Sharers.isElement(requestor);
 167     } else {
 168       return false;
 169     }
 170   }
 171
 172   void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
 173     assert(is_valid(cache_entry));
 174     DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
 175             machineID, requestor, addr);
 176     cache_entry.Sharers.add(requestor);
 177   }
 178
 179   State getState(TBE tbe, Entry cache_entry, Address addr) {
 180     if(is_valid(tbe)) {
 181       return tbe.TBEState;
 182     } else if (is_valid(cache_entry)) {
 183       return cache_entry.CacheState;
 184     }
 185     return State:NP;
 186   }
 187
 188   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 189     // MUST CHANGE
 190     if (is_valid(tbe)) {
 191       tbe.TBEState := state;
 192     }
 193
 194     if (is_valid(cache_entry)) {
 195       cache_entry.CacheState := state;
 196     }
 197   }
 198
 199   AccessPermission getAccessPermission(Address addr) {
 200     TBE tbe := L2_TBEs[addr];
 201     if(is_valid(tbe)) {
 202       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
 203       return L2Cache_State_to_permission(tbe.TBEState);
 204     }
 205
 206     Entry cache_entry := getCacheEntry(addr);
 207     if(is_valid(cache_entry)) {
 208       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
 209       return L2Cache_State_to_permission(cache_entry.CacheState);
 210     }
 211
 212     DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
 213     return AccessPermission:NotPresent;
 214   }
 215
 216   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 217     TBE tbe := L2_TBEs[addr];
 218     if(is_valid(tbe)) {
 219         return tbe.DataBlk;
 220     }
 221
 222     return getCacheEntry(addr).DataBlk;
 223   }
 224
 225   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 226     if (is_valid(cache_entry)) {
 227       cache_entry.changePermission(L2Cache_State_to_permission(state));
 228     }
 229   }
 230
 231   Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
 232                                       MachineID requestor, Entry cache_entry) {
 233     if(type == CoherenceRequestType:GETS) {
 234       return Event:L1_GETS;
 235     } else if(type == CoherenceRequestType:GET_INSTR) {
 236       return Event:L1_GET_INSTR;
 237     } else if (type == CoherenceRequestType:GETX) {
 238       return Event:L1_GETX;
 239     } else if (type == CoherenceRequestType:UPGRADE) {
 240       if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
 241         return Event:L1_UPGRADE;
 242       } else {
 243         return Event:L1_GETX;
 244       }
 245     } else if (type == CoherenceRequestType:PUTX) {
 246       if (isSharer(addr, requestor, cache_entry)) {
 247         return Event:L1_PUTX;
 248       } else {
 249         return Event:L1_PUTX_old;
 250       }
 251     } else {
 252       DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
 253       error("Invalid L1 forwarded request type");
 254     }
 255   }
 256
 257   int getPendingAcks(TBE tbe) {
 258     return tbe.pendingAcks;
 259   }
 260
 261   bool isDirty(Entry cache_entry) {
 262     assert(is_valid(cache_entry));
 263     return cache_entry.Dirty;
 264   }
 265
 266   // ** OUT_PORTS **
 267
 268   out_port(L1RequestL2Network_out, RequestMsg, L1RequestFromL2Cache);
 269   out_port(DirRequestL2Network_out, RequestMsg, DirRequestFromL2Cache);
 270   out_port(responseL2Network_out, ResponseMsg, responseFromL2Cache);
 271
 272
 273   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
 274     if(L1unblockNetwork_in.isReady()) {
 275       peek(L1unblockNetwork_in,  ResponseMsg) {
 276         Entry cache_entry := getCacheEntry(in_msg.Addr);
 277         TBE tbe := L2_TBEs[in_msg.Addr];
 278         DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
 279                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
 280                 in_msg.Sender, in_msg.Type, in_msg.Destination);
 281
 282         assert(in_msg.Destination.isElement(machineID));
 283         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
 284           trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
 285         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
 286           trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
 287         } else {
 288           error("unknown unblock message");
 289         }
 290       }
 291     }
 292   }
 293
 294   // Response  L2 Network - response msg to this particular L2 bank
 295   in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
 296     if (responseL2Network_in.isReady()) {
 297       peek(responseL2Network_in, ResponseMsg) {
 298         // test wether it's from a local L1 or an off chip source
 299         assert(in_msg.Destination.isElement(machineID));
 300         Entry cache_entry := getCacheEntry(in_msg.Addr);
 301         TBE tbe := L2_TBEs[in_msg.Addr];
 302
 303         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 304           if(in_msg.Type == CoherenceResponseType:DATA) {
 305             if (in_msg.Dirty) {
 306               trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
 307             } else {
 308               trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
 309             }
 310           } else if (in_msg.Type == CoherenceResponseType:ACK) {
 311             if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
 312               trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
 313             } else {
 314               trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
 315             }
 316           } else {
 317             error("unknown message type");
 318           }
 319
 320         } else { // external message
 321           if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
 322               trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
 323           } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
 324               trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
 325           } else if(in_msg.Type == CoherenceResponseType:INV) {
 326               trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
 327           } else {
 328             error("unknown message type");
 329           }
 330         }
 331       }
 332     }  // if not ready, do nothing
 333   }
 334
 335   // L1 Request
 336   in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
 337     if(L1RequestL2Network_in.isReady()) {
 338       peek(L1RequestL2Network_in,  RequestMsg) {
 339         Entry cache_entry := getCacheEntry(in_msg.Addr);
 340         TBE tbe := L2_TBEs[in_msg.Addr];
 341
 342         DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
 343                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
 344                 in_msg.Requestor, in_msg.Type, in_msg.Destination);
 345
 346         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
 347         assert(in_msg.Destination.isElement(machineID));
 348
 349         if (is_valid(cache_entry)) {
 350           // The L2 contains the block, so proceeded with handling the request
 351           trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
 352                                                 in_msg.Requestor, cache_entry),
 353                   in_msg.Addr, cache_entry, tbe);
 354         } else {
 355           if (L2cache.cacheAvail(in_msg.Addr)) {
 356             // L2 does't have the line, but we have space for it in the L2
 357             trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
 358                                                   in_msg.Requestor, cache_entry),
 359                     in_msg.Addr, cache_entry, tbe);
 360           } else {
 361             // No room in the L2, so we need to make room before handling the request
 362             Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
 363             if (isDirty(L2cache_entry)) {
 364               trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
 365                       L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
 366             } else {
 367               trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
 368                       L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
 369             }
 370           }
 371         }
 372       }
 373     }
 374   }
 375
 376
 377   // ACTIONS
 378
 379   action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
 380     peek(L1RequestL2Network_in, RequestMsg) {
 381       enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
 382         out_msg.Addr := address;
 383         out_msg.Type := CoherenceRequestType:GETS;
 384         out_msg.Requestor := machineID;
 385         out_msg.Destination.add(map_Address_to_Directory(address));
 386         out_msg.MessageSize := MessageSizeType:Control;
 387       }
 388     }
 389   }
 390
 391   action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
 392     peek(L1RequestL2Network_in, RequestMsg) {
 393       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 394         assert(is_valid(cache_entry));
 395         out_msg.Addr := address;
 396         out_msg.Type := in_msg.Type;
 397         out_msg.Requestor := in_msg.Requestor;
 398         out_msg.Destination.add(cache_entry.Exclusive);
 399         out_msg.MessageSize := MessageSizeType:Request_Control;
 400       }
 401     }
 402   }
 403
 404   action(c_exclusiveReplacement, "c", desc="Send data to memory") {
 405     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 406       assert(is_valid(cache_entry));
 407       out_msg.Addr := address;
 408       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 409       out_msg.Sender := machineID;
 410       out_msg.Destination.add(map_Address_to_Directory(address));
 411       out_msg.DataBlk := cache_entry.DataBlk;
 412       out_msg.Dirty := cache_entry.Dirty;
 413       out_msg.MessageSize := MessageSizeType:Response_Data;
 414     }
 415   }
 416
 417   action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
 418     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 419       out_msg.Addr := address;
 420       out_msg.Type := CoherenceResponseType:ACK;
 421       out_msg.Sender := machineID;
 422       out_msg.Destination.add(map_Address_to_Directory(address));
 423       out_msg.MessageSize := MessageSizeType:Response_Control;
 424     }
 425   }
 426
 427   action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
 428     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 429       assert(is_valid(tbe));
 430       out_msg.Addr := address;
 431       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 432       out_msg.Sender := machineID;
 433       out_msg.Destination.add(map_Address_to_Directory(address));
 434       out_msg.DataBlk := tbe.DataBlk;
 435       out_msg.Dirty := tbe.Dirty;
 436       out_msg.MessageSize := MessageSizeType:Response_Data;
 437     }
 438   }
 439
 440   action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
 441     peek(L1RequestL2Network_in, RequestMsg) {
 442       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 443         assert(is_valid(cache_entry));
 444         out_msg.Addr := address;
 445         out_msg.Type := CoherenceResponseType:DATA;
 446         out_msg.Sender := machineID;
 447         out_msg.Destination.add(in_msg.Requestor);
 448         out_msg.DataBlk := cache_entry.DataBlk;
 449         out_msg.MessageSize := MessageSizeType:Response_Data;
 450
 451         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 452         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 453           out_msg.AckCount := out_msg.AckCount + 1;
 454         }
 455       }
 456     }
 457   }
 458
 459   action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
 460     peek(L1RequestL2Network_in, RequestMsg) {
 461       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 462         assert(is_valid(cache_entry));
 463         out_msg.Addr := address;
 464         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 465         out_msg.Sender := machineID;
 466         out_msg.Destination.add(in_msg.Requestor);
 467         out_msg.DataBlk := cache_entry.DataBlk;
 468         out_msg.MessageSize := MessageSizeType:Response_Data;
 469
 470         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 471         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 472           out_msg.AckCount := out_msg.AckCount + 1;
 473         }
 474       }
 475     }
 476   }
 477
 478   action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
 479     peek(L1RequestL2Network_in, RequestMsg) {
 480       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 481         assert(is_valid(cache_entry));
 482         out_msg.Addr := address;
 483         out_msg.Type := CoherenceResponseType:DATA;
 484         out_msg.Sender := machineID;
 485         out_msg.Destination.add(in_msg.Requestor);
 486         out_msg.DataBlk := cache_entry.DataBlk;
 487         out_msg.MessageSize := MessageSizeType:Response_Data;
 488         out_msg.AckCount := 0;
 489       }
 490     }
 491   }
 492
 493   action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
 494     assert(is_valid(tbe));
 495     assert(tbe.L1_GetS_IDs.count() > 0);
 496     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 497       assert(is_valid(cache_entry));
 498       out_msg.Addr := address;
 499       out_msg.Type := CoherenceResponseType:DATA;
 500       out_msg.Sender := machineID;
 501       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 502       out_msg.DataBlk := cache_entry.DataBlk;
 503       out_msg.MessageSize := MessageSizeType:Response_Data;
 504     }
 505   }
 506
 507   action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
 508     assert(is_valid(tbe));
 509     assert(tbe.L1_GetS_IDs.count() == 1);
 510     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 511       assert(is_valid(cache_entry));
 512       out_msg.Addr := address;
 513       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 514       out_msg.Sender := machineID;
 515       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 516       out_msg.DataBlk := cache_entry.DataBlk;
 517       out_msg.MessageSize := MessageSizeType:Response_Data;
 518     }
 519   }
 520
 521   action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
 522     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 523       assert(is_valid(tbe));
 524       assert(is_valid(cache_entry));
 525       out_msg.Addr := address;
 526       out_msg.Type := CoherenceResponseType:DATA;
 527       out_msg.Sender := machineID;
 528       out_msg.Destination.add(tbe.L1_GetX_ID);
 529       DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 530       out_msg.DataBlk := cache_entry.DataBlk;
 531       DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
 532               out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
 533       out_msg.MessageSize := MessageSizeType:Response_Data;
 534     }
 535   }
 536
 537   action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
 538     enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 539       assert(is_valid(cache_entry));
 540       out_msg.Addr := address;
 541       out_msg.Type := CoherenceRequestType:INV;
 542       out_msg.Requestor := machineID;
 543       out_msg.Destination := cache_entry.Sharers;
 544       out_msg.MessageSize := MessageSizeType:Request_Control;
 545     }
 546   }
 547
 548   action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
 549     peek(L1RequestL2Network_in, RequestMsg) {
 550       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 551         assert(is_valid(cache_entry));
 552         out_msg.Addr := address;
 553         out_msg.Type := CoherenceRequestType:INV;
 554         out_msg.Requestor := in_msg.Requestor;
 555         out_msg.Destination := cache_entry.Sharers;
 556         out_msg.MessageSize := MessageSizeType:Request_Control;
 557       }
 558     }
 559   }
 560
 561   action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
 562     peek(L1RequestL2Network_in, RequestMsg) {
 563       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 564         assert(is_valid(cache_entry));
 565         out_msg.Addr := address;
 566         out_msg.Type := CoherenceRequestType:INV;
 567         out_msg.Requestor := in_msg.Requestor;
 568         out_msg.Destination := cache_entry.Sharers;
 569         out_msg.Destination.remove(in_msg.Requestor);
 570         out_msg.MessageSize := MessageSizeType:Request_Control;
 571       }
 572     }
 573   }
 574
 575   // OTHER ACTIONS
 576   action(i_allocateTBE, "i", desc="Allocate TBE for request") {
 577     check_allocate(L2_TBEs);
 578     assert(is_valid(cache_entry));
 579     L2_TBEs.allocate(address);
 580     set_tbe(L2_TBEs[address]);
 581     tbe.L1_GetS_IDs.clear();
 582     tbe.DataBlk := cache_entry.DataBlk;
 583     tbe.Dirty := cache_entry.Dirty;
 584     tbe.pendingAcks := cache_entry.Sharers.count();
 585   }
 586
 587   action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
 588     L2_TBEs.deallocate(address);
 589     unset_tbe();
 590   }
 591
 592   action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
 593     profileMsgDelay(0, L1RequestL2Network_in.dequeue());
 594   }
 595
 596   action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
 597     profileMsgDelay(0, L1unblockNetwork_in.dequeue());
 598   }
 599
 600   action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
 601     profileMsgDelay(1, responseL2Network_in.dequeue());
 602   }
 603
 604   action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
 605     peek(responseL2Network_in, ResponseMsg) {
 606       assert(is_valid(cache_entry));
 607       cache_entry.DataBlk := in_msg.DataBlk;
 608       if (in_msg.Dirty) {
 609         cache_entry.Dirty := in_msg.Dirty;
 610       }
 611     }
 612   }
 613
 614   action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
 615     peek(L1RequestL2Network_in, RequestMsg) {
 616       assert(is_valid(cache_entry));
 617       cache_entry.DataBlk := in_msg.DataBlk;
 618       if (in_msg.Dirty) {
 619         cache_entry.Dirty := in_msg.Dirty;
 620       }
 621     }
 622   }
 623
 624   action(q_updateAck, "q", desc="update pending ack count") {
 625     peek(responseL2Network_in, ResponseMsg) {
 626       assert(is_valid(tbe));
 627       tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
 628       APPEND_TRANSITION_COMMENT(in_msg.AckCount);
 629       APPEND_TRANSITION_COMMENT(" p: ");
 630       APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
 631     }
 632   }
 633
 634   action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
 635     peek(responseL2Network_in, ResponseMsg) {
 636       assert(is_valid(tbe));
 637       tbe.DataBlk := in_msg.DataBlk;
 638       tbe.Dirty := in_msg.Dirty;
 639     }
 640   }
 641
 642   action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
 643     peek(L1RequestL2Network_in, RequestMsg) {
 644       assert(is_valid(tbe));
 645       tbe.L1_GetS_IDs.add(in_msg.Requestor);
 646     }
 647   }
 648
 649   action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
 650     peek(L1RequestL2Network_in, RequestMsg) {
 651       assert(is_valid(tbe));
 652       tbe.L1_GetX_ID := in_msg.Requestor;
 653     }
 654   }
 655
 656   action(set_setMRU, "\set", desc="set the MRU entry") {
 657     L2cache.setMRU(address);
 658   }
 659
 660   action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
 661     if (is_invalid(cache_entry)) {
 662       set_cache_entry(L2cache.allocate(address, new Entry));
 663     }
 664   }
 665
 666   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 667     L2cache.deallocate(address);
 668     unset_cache_entry();
 669   }
 670
 671   action(t_sendWBAck, "t", desc="Send writeback ACK") {
 672     peek(L1RequestL2Network_in, RequestMsg) {
 673       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 674         out_msg.Addr := address;
 675         out_msg.Type := CoherenceResponseType:WB_ACK;
 676         out_msg.Sender := machineID;
 677         out_msg.Destination.add(in_msg.Requestor);
 678         out_msg.MessageSize := MessageSizeType:Response_Control;
 679       }
 680     }
 681   }
 682
 683   action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
 684     peek(L1RequestL2Network_in, RequestMsg) {
 685       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 686         assert(is_valid(cache_entry));
 687         out_msg.Addr := address;
 688         out_msg.Type := CoherenceResponseType:ACK;
 689         out_msg.Sender := machineID;
 690         out_msg.Destination.add(in_msg.Requestor);
 691         out_msg.MessageSize := MessageSizeType:Response_Control;
 692         // upgrader doesn't get ack from itself, hence the + 1
 693         out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
 694       }
 695     }
 696   }
 697
 698   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
 699       ++L2cache.demand_misses;
 700   }
 701
 702   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
 703       ++L2cache.demand_hits;
 704   }
 705
 706   action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
 707     peek(L1RequestL2Network_in, RequestMsg) {
 708       assert(is_valid(cache_entry));
 709       addSharer(address, in_msg.Requestor, cache_entry);
 710       APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
 711     }
 712   }
 713
 714   action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
 715     peek(L1unblockNetwork_in, ResponseMsg) {
 716       assert(is_valid(cache_entry));
 717       addSharer(address, in_msg.Sender, cache_entry);
 718     }
 719   }
 720
 721   action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
 722     peek(L1RequestL2Network_in, RequestMsg) {
 723       assert(is_valid(cache_entry));
 724       cache_entry.Sharers.remove(in_msg.Requestor);
 725     }
 726   }
 727
 728   action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
 729     peek(L1RequestL2Network_in, RequestMsg) {
 730       assert(is_valid(cache_entry));
 731       cache_entry.Sharers.clear();
 732     }
 733   }
 734
 735   action(mm_markExclusive, "\m", desc="set the exclusive owner") {
 736     peek(L1RequestL2Network_in, RequestMsg) {
 737       assert(is_valid(cache_entry));
 738       cache_entry.Sharers.clear();
 739       cache_entry.Exclusive := in_msg.Requestor;
 740       addSharer(address, in_msg.Requestor, cache_entry);
 741     }
 742   }
 743
 744   action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
 745     peek(L1unblockNetwork_in, ResponseMsg) {
 746       assert(is_valid(cache_entry));
 747       cache_entry.Sharers.clear();
 748       cache_entry.Exclusive := in_msg.Sender;
 749       addSharer(address, in_msg.Sender, cache_entry);
 750     }
 751   }
 752
 753   action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
 754     stall_and_wait(L1RequestL2Network_in, address);
 755   }
 756
 757   action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
 758     responseL2Network_in.recycle();
 759   }
 760
 761   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
 762     wakeUpBuffers(address);
 763   }
 764
 765   //*****************************************************
 766   // TRANSITIONS
 767   //*****************************************************
 768
 769
 770   //===============================================
 771   // BASE STATE - I
 772
 773   // Transitions from I (Idle)
 774   transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
 775     t_sendWBAck;
 776     jj_popL1RequestQueue;
 777   }
 778
 779   transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
 780     t_sendWBAck;
 781     jj_popL1RequestQueue;
 782   }
 783
 784   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
 785     zz_stallAndWaitL1RequestQueue;
 786   }
 787
 788   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
 789     zn_recycleResponseNetwork;
 790   }
 791
 792   transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
 793     o_popIncomingResponseQueue;
 794   }
 795
 796
 797   transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
 798     zz_stallAndWaitL1RequestQueue;
 799   }
 800
 801
 802   transition(NP, L1_GETS,  ISS) {
 803     qq_allocateL2CacheBlock;
 804     ll_clearSharers;
 805     nn_addSharer;
 806     i_allocateTBE;
 807     ss_recordGetSL1ID;
 808     a_issueFetchToMemory;
 809     uu_profileMiss;
 810     jj_popL1RequestQueue;
 811   }
 812
 813   transition(NP, L1_GET_INSTR, IS) {
 814     qq_allocateL2CacheBlock;
 815     ll_clearSharers;
 816     nn_addSharer;
 817     i_allocateTBE;
 818     ss_recordGetSL1ID;
 819     a_issueFetchToMemory;
 820     uu_profileMiss;
 821     jj_popL1RequestQueue;
 822   }
 823
 824   transition(NP, L1_GETX, IM) {
 825     qq_allocateL2CacheBlock;
 826     ll_clearSharers;
 827     // nn_addSharer;
 828     i_allocateTBE;
 829     xx_recordGetXL1ID;
 830     a_issueFetchToMemory;
 831     uu_profileMiss;
 832     jj_popL1RequestQueue;
 833   }
 834
 835
 836   // transitions from IS/IM
 837
 838   transition(ISS, Mem_Data, MT_MB) {
 839     m_writeDataToCache;
 840     ex_sendExclusiveDataToGetSRequestors;
 841     s_deallocateTBE;
 842     o_popIncomingResponseQueue;
 843   }
 844
 845   transition(IS, Mem_Data, SS) {
 846     m_writeDataToCache;
 847     e_sendDataToGetSRequestors;
 848     s_deallocateTBE;
 849     o_popIncomingResponseQueue;
 850     kd_wakeUpDependents;
 851   }
 852
 853   transition(IM, Mem_Data, MT_MB) {
 854     m_writeDataToCache;
 855     ee_sendDataToGetXRequestor;
 856     s_deallocateTBE;
 857     o_popIncomingResponseQueue;
 858   }
 859
 860   transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
 861     nn_addSharer;
 862     ss_recordGetSL1ID;
 863     uu_profileMiss;
 864     jj_popL1RequestQueue;
 865   }
 866
 867   transition({IS, ISS}, L1_GETX) {
 868     zz_stallAndWaitL1RequestQueue;
 869   }
 870
 871   transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
 872     zz_stallAndWaitL1RequestQueue;
 873   }
 874
 875   // transitions from SS
 876   transition(SS, {L1_GETS, L1_GET_INSTR}) {
 877     ds_sendSharedDataToRequestor;
 878     nn_addSharer;
 879     set_setMRU;
 880     uu_profileHit;
 881     jj_popL1RequestQueue;
 882   }
 883
 884
 885   transition(SS, L1_GETX, SS_MB) {
 886     d_sendDataToRequestor;
 887     // fw_sendFwdInvToSharers;
 888     fwm_sendFwdInvToSharersMinusRequestor;
 889     set_setMRU;
 890     uu_profileHit;
 891     jj_popL1RequestQueue;
 892   }
 893
 894   transition(SS, L1_UPGRADE, SS_MB) {
 895     fwm_sendFwdInvToSharersMinusRequestor;
 896     ts_sendInvAckToUpgrader;
 897     set_setMRU;
 898     uu_profileHit;
 899     jj_popL1RequestQueue;
 900   }
 901
 902   transition(SS, L2_Replacement_clean, I_I) {
 903     i_allocateTBE;
 904     f_sendInvToSharers;
 905     rr_deallocateL2CacheBlock;
 906   }
 907
 908   transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
 909     i_allocateTBE;
 910     f_sendInvToSharers;
 911     rr_deallocateL2CacheBlock;
 912   }
 913
 914
 915   transition(M, L1_GETX, MT_MB) {
 916     d_sendDataToRequestor;
 917     set_setMRU;
 918     uu_profileHit;
 919     jj_popL1RequestQueue;
 920   }
 921
 922   transition(M, L1_GET_INSTR, SS) {
 923     d_sendDataToRequestor;
 924     nn_addSharer;
 925     set_setMRU;
 926     uu_profileHit;
 927     jj_popL1RequestQueue;
 928   }
 929
 930   transition(M, L1_GETS, MT_MB) {
 931     dd_sendExclusiveDataToRequestor;
 932     set_setMRU;
 933     uu_profileHit;
 934     jj_popL1RequestQueue;
 935   }
 936
 937   transition(M, {L2_Replacement, MEM_Inv}, M_I) {
 938     i_allocateTBE;
 939     c_exclusiveReplacement;
 940     rr_deallocateL2CacheBlock;
 941   }
 942
 943   transition(M, L2_Replacement_clean, M_I) {
 944     i_allocateTBE;
 945     c_exclusiveCleanReplacement;
 946     rr_deallocateL2CacheBlock;
 947   }
 948
 949
 950   // transitions from MT
 951
 952   transition(MT, L1_GETX, MT_MB) {
 953     b_forwardRequestToExclusive;
 954     uu_profileMiss;
 955     set_setMRU;
 956     jj_popL1RequestQueue;
 957   }
 958
 959
 960   transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
 961     b_forwardRequestToExclusive;
 962     uu_profileMiss;
 963     set_setMRU;
 964     jj_popL1RequestQueue;
 965   }
 966
 967   transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
 968     i_allocateTBE;
 969     f_sendInvToSharers;
 970     rr_deallocateL2CacheBlock;
 971   }
 972
 973   transition(MT, L2_Replacement_clean, MCT_I) {
 974     i_allocateTBE;
 975     f_sendInvToSharers;
 976     rr_deallocateL2CacheBlock;
 977   }
 978
 979   transition(MT, L1_PUTX, M) {
 980     ll_clearSharers;
 981     mr_writeDataToCacheFromRequest;
 982     t_sendWBAck;
 983     jj_popL1RequestQueue;
 984   }
 985
 986   transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
 987     // update actual directory
 988     mmu_markExclusiveFromUnblock;
 989     k_popUnblockQueue;
 990     kd_wakeUpDependents;
 991   }
 992
 993   transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
 994     zz_stallAndWaitL1RequestQueue;
 995   }
 996
 997   transition(MT_IIB, Unblock, MT_IB) {
 998     nnu_addSharerFromUnblock;
 999     k_popUnblockQueue;
1000   }
1001
1002   transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
1003     m_writeDataToCache;
1004     o_popIncomingResponseQueue;
1005   }
1006
1007   transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
1008     m_writeDataToCache;
1009     o_popIncomingResponseQueue;
1010     kd_wakeUpDependents;
1011   }
1012
1013   transition(MT_SB, Unblock, SS) {
1014     nnu_addSharerFromUnblock;
1015     k_popUnblockQueue;
1016     kd_wakeUpDependents;
1017   }
1018
1019   // writeback states
1020   transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
1021     zz_stallAndWaitL1RequestQueue;
1022   }
1023
1024   transition(I_I, Ack) {
1025     q_updateAck;
1026     o_popIncomingResponseQueue;
1027   }
1028
1029   transition(I_I, Ack_all, M_I) {
1030     c_exclusiveCleanReplacement;
1031     o_popIncomingResponseQueue;
1032   }
1033
1034   transition({MT_I, MCT_I}, WB_Data, M_I) {
1035     qq_writeDataToTBE;
1036     ct_exclusiveReplacementFromTBE;
1037     o_popIncomingResponseQueue;
1038   }
1039
1040   transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
1041     c_exclusiveCleanReplacement;
1042     o_popIncomingResponseQueue;
1043   }
1044
1045   transition(MCT_I,  {L1_PUTX, L1_PUTX_old}){
1046     zz_stallAndWaitL1RequestQueue;
1047   }
1048
1049   // L1 never changed Dirty data
1050   transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
1051     ct_exclusiveReplacementFromTBE;
1052     o_popIncomingResponseQueue;
1053   }
1054
1055   transition(MT_I, {L1_PUTX, L1_PUTX_old}){
1056     zz_stallAndWaitL1RequestQueue;
1057   }
1058
1059   // possible race between unblock and immediate replacement
1060   transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
1061     zz_stallAndWaitL1RequestQueue;
1062   }
1063
1064   transition(S_I, Ack) {
1065     q_updateAck;
1066     o_popIncomingResponseQueue;
1067   }
1068
1069   transition(S_I, Ack_all, M_I) {
1070     ct_exclusiveReplacementFromTBE;
1071     o_popIncomingResponseQueue;
1072   }
1073
1074   transition(M_I, Mem_Ack, NP) {
1075     s_deallocateTBE;
1076     o_popIncomingResponseQueue;
1077     kd_wakeUpDependents;
1078   }
1079 }