2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
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29 machine(L2Cache, "MESI Directory L2 Cache CMP")
30 : CacheMemory * L2cache;
31 Cycles l2_request_latency := 2;
32 Cycles l2_response_latency := 2;
33 Cycles to_l1_latency := 1;
36 // From local bank of L2 cache TO the network
37 MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0",
38 vnet_type="request"; // this L2 bank -> Memory
40 MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2",
41 vnet_type="request"; // this L2 bank -> a local L1
43 MessageBuffer * responseFromL2Cache, network="To", virtual_network="1",
44 vnet_type="response"; // this L2 bank -> a local L1 || Memory
46 // FROM the network to this local bank of L2 cache
47 MessageBuffer * unblockToL2Cache, network="From", virtual_network="2",
48 vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
50 MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
51 vnet_type="request"; // a local L1 -> this L2 bank
53 MessageBuffer * responseToL2Cache, network="From", virtual_network="1",
54 vnet_type="response"; // a local L1 || Memory -> this L2 bank
57 state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
59 NP, AccessPermission:Invalid, desc="Not present in either cache";
60 SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
61 M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
62 MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
65 M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
66 MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
67 MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
68 I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
69 S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
71 // Transient States for fetching data from memory
72 ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
73 IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
74 IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
77 SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
78 MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
80 MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
81 MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
82 MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
87 enumeration(Event, desc="L2 Cache events") {
90 // events initiated by the local L1s
91 L1_GET_INSTR, desc="a L1I GET INSTR request for a block maped to us";
92 L1_GETS, desc="a L1D GETS request for a block maped to us";
93 L1_GETX, desc="a L1D GETX request for a block maped to us";
94 L1_UPGRADE, desc="a L1D GETX request for a block maped to us";
96 L1_PUTX, desc="L1 replacing data";
97 L1_PUTX_old, desc="L1 replacing data, but no longer sharer";
99 // events initiated by this L2
100 L2_Replacement, desc="L2 Replacement", format="!r";
101 L2_Replacement_clean, desc="L2 Replacement, but data is clean", format="!r";
103 // events from memory controller
104 Mem_Data, desc="data from memory", format="!r";
105 Mem_Ack, desc="ack from memory", format="!r";
107 // M->S data writeback
108 WB_Data, desc="data from L1";
109 WB_Data_clean, desc="clean data from L1";
110 Ack, desc="writeback ack";
111 Ack_all, desc="writeback ack";
113 Unblock, desc="Unblock from L1 requestor";
114 Exclusive_Unblock, desc="Unblock from L1 requestor";
116 MEM_Inv, desc="Invalidation from directory";
122 structure(Entry, desc="...", interface="AbstractCacheEntry") {
123 State CacheState, desc="cache state";
124 NetDest Sharers, desc="tracks the L1 shares on-chip";
125 MachineID Exclusive, desc="Exclusive holder of block";
126 DataBlock DataBlk, desc="data for the block";
127 bool Dirty, default="false", desc="data is dirty";
131 structure(TBE, desc="...") {
132 Addr addr, desc="Physical address for this TBE";
133 State TBEState, desc="Transient state";
134 DataBlock DataBlk, desc="Buffer for the data block";
135 bool Dirty, default="false", desc="Data is Dirty";
137 NetDest L1_GetS_IDs, desc="Set of the internal processors that want the block in shared state";
138 MachineID L1_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
139 int pendingAcks, desc="number of pending acks for invalidates during writeback";
142 structure(TBETable, external="yes") {
145 void deallocate(Addr);
146 bool isPresent(Addr);
149 TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
151 void set_cache_entry(AbstractCacheEntry a);
152 void unset_cache_entry();
155 void wakeUpBuffers(Addr a);
156 void profileMsgDelay(int virtualNetworkType, Cycles c);
158 // inclusive cache, returns L2 entries only
159 Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
160 return static_cast(Entry, "pointer", L2cache[addr]);
163 bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) {
164 if (is_valid(cache_entry)) {
165 return cache_entry.Sharers.isElement(requestor);
171 void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
172 assert(is_valid(cache_entry));
173 DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
174 machineID, requestor, addr);
175 cache_entry.Sharers.add(requestor);
178 State getState(TBE tbe, Entry cache_entry, Addr addr) {
181 } else if (is_valid(cache_entry)) {
182 return cache_entry.CacheState;
187 void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
190 tbe.TBEState := state;
193 if (is_valid(cache_entry)) {
194 cache_entry.CacheState := state;
198 AccessPermission getAccessPermission(Addr addr) {
199 TBE tbe := TBEs[addr];
201 DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
202 return L2Cache_State_to_permission(tbe.TBEState);
205 Entry cache_entry := getCacheEntry(addr);
206 if(is_valid(cache_entry)) {
207 DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
208 return L2Cache_State_to_permission(cache_entry.CacheState);
211 DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
212 return AccessPermission:NotPresent;
215 void functionalRead(Addr addr, Packet *pkt) {
216 TBE tbe := TBEs[addr];
218 testAndRead(addr, tbe.DataBlk, pkt);
220 testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
224 int functionalWrite(Addr addr, Packet *pkt) {
225 int num_functional_writes := 0;
227 TBE tbe := TBEs[addr];
229 num_functional_writes := num_functional_writes +
230 testAndWrite(addr, tbe.DataBlk, pkt);
231 return num_functional_writes;
234 num_functional_writes := num_functional_writes +
235 testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
236 return num_functional_writes;
239 void setAccessPermission(Entry cache_entry, Addr addr, State state) {
240 if (is_valid(cache_entry)) {
241 cache_entry.changePermission(L2Cache_State_to_permission(state));
245 Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr,
246 MachineID requestor, Entry cache_entry) {
247 if(type == CoherenceRequestType:GETS) {
248 return Event:L1_GETS;
249 } else if(type == CoherenceRequestType:GET_INSTR) {
250 return Event:L1_GET_INSTR;
251 } else if (type == CoherenceRequestType:GETX) {
252 return Event:L1_GETX;
253 } else if (type == CoherenceRequestType:UPGRADE) {
254 if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
255 return Event:L1_UPGRADE;
257 return Event:L1_GETX;
259 } else if (type == CoherenceRequestType:PUTX) {
260 if (isSharer(addr, requestor, cache_entry)) {
261 return Event:L1_PUTX;
263 return Event:L1_PUTX_old;
266 DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
267 error("Invalid L1 forwarded request type");
271 int getPendingAcks(TBE tbe) {
272 return tbe.pendingAcks;
275 bool isDirty(Entry cache_entry) {
276 assert(is_valid(cache_entry));
277 return cache_entry.Dirty;
282 out_port(L1RequestL2Network_out, RequestMsg, L1RequestFromL2Cache);
283 out_port(DirRequestL2Network_out, RequestMsg, DirRequestFromL2Cache);
284 out_port(responseL2Network_out, ResponseMsg, responseFromL2Cache);
287 in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
288 if(L1unblockNetwork_in.isReady()) {
289 peek(L1unblockNetwork_in, ResponseMsg) {
290 Entry cache_entry := getCacheEntry(in_msg.addr);
291 TBE tbe := TBEs[in_msg.addr];
292 DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
293 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
294 in_msg.Sender, in_msg.Type, in_msg.Destination);
296 assert(in_msg.Destination.isElement(machineID));
297 if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
298 trigger(Event:Exclusive_Unblock, in_msg.addr, cache_entry, tbe);
299 } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
300 trigger(Event:Unblock, in_msg.addr, cache_entry, tbe);
302 error("unknown unblock message");
308 // Response L2 Network - response msg to this particular L2 bank
309 in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
310 if (responseL2Network_in.isReady()) {
311 peek(responseL2Network_in, ResponseMsg) {
312 // test wether it's from a local L1 or an off chip source
313 assert(in_msg.Destination.isElement(machineID));
314 Entry cache_entry := getCacheEntry(in_msg.addr);
315 TBE tbe := TBEs[in_msg.addr];
317 if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
318 if(in_msg.Type == CoherenceResponseType:DATA) {
320 trigger(Event:WB_Data, in_msg.addr, cache_entry, tbe);
322 trigger(Event:WB_Data_clean, in_msg.addr, cache_entry, tbe);
324 } else if (in_msg.Type == CoherenceResponseType:ACK) {
325 if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
326 trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe);
328 trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
331 error("unknown message type");
334 } else { // external message
335 if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
336 trigger(Event:Mem_Data, in_msg.addr, cache_entry, tbe);
337 } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
338 trigger(Event:Mem_Ack, in_msg.addr, cache_entry, tbe);
339 } else if(in_msg.Type == CoherenceResponseType:INV) {
340 trigger(Event:MEM_Inv, in_msg.addr, cache_entry, tbe);
342 error("unknown message type");
346 } // if not ready, do nothing
350 in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
351 if(L1RequestL2Network_in.isReady()) {
352 peek(L1RequestL2Network_in, RequestMsg) {
353 Entry cache_entry := getCacheEntry(in_msg.addr);
354 TBE tbe := TBEs[in_msg.addr];
356 DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
357 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
358 in_msg.Requestor, in_msg.Type, in_msg.Destination);
360 assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
361 assert(in_msg.Destination.isElement(machineID));
363 if (is_valid(cache_entry)) {
364 // The L2 contains the block, so proceeded with handling the request
365 trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
366 in_msg.Requestor, cache_entry),
367 in_msg.addr, cache_entry, tbe);
369 if (L2cache.cacheAvail(in_msg.addr)) {
370 // L2 does't have the line, but we have space for it in the L2
371 trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
372 in_msg.Requestor, cache_entry),
373 in_msg.addr, cache_entry, tbe);
375 // No room in the L2, so we need to make room before handling the request
376 Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.addr));
377 if (isDirty(L2cache_entry)) {
378 trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr),
379 L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
381 trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.addr),
382 L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
393 action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
394 peek(L1RequestL2Network_in, RequestMsg) {
395 enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
396 out_msg.addr := address;
397 out_msg.Type := CoherenceRequestType:GETS;
398 out_msg.Requestor := machineID;
399 out_msg.Destination.add(map_Address_to_Directory(address));
400 out_msg.MessageSize := MessageSizeType:Control;
405 action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
406 peek(L1RequestL2Network_in, RequestMsg) {
407 enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
408 assert(is_valid(cache_entry));
409 out_msg.addr := address;
410 out_msg.Type := in_msg.Type;
411 out_msg.Requestor := in_msg.Requestor;
412 out_msg.Destination.add(cache_entry.Exclusive);
413 out_msg.MessageSize := MessageSizeType:Request_Control;
418 action(c_exclusiveReplacement, "c", desc="Send data to memory") {
419 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
420 assert(is_valid(cache_entry));
421 out_msg.addr := address;
422 out_msg.Type := CoherenceResponseType:MEMORY_DATA;
423 out_msg.Sender := machineID;
424 out_msg.Destination.add(map_Address_to_Directory(address));
425 out_msg.DataBlk := cache_entry.DataBlk;
426 out_msg.Dirty := cache_entry.Dirty;
427 out_msg.MessageSize := MessageSizeType:Response_Data;
431 action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
432 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
433 out_msg.addr := address;
434 out_msg.Type := CoherenceResponseType:ACK;
435 out_msg.Sender := machineID;
436 out_msg.Destination.add(map_Address_to_Directory(address));
437 out_msg.MessageSize := MessageSizeType:Response_Control;
441 action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
442 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
443 assert(is_valid(tbe));
444 out_msg.addr := address;
445 out_msg.Type := CoherenceResponseType:MEMORY_DATA;
446 out_msg.Sender := machineID;
447 out_msg.Destination.add(map_Address_to_Directory(address));
448 out_msg.DataBlk := tbe.DataBlk;
449 out_msg.Dirty := tbe.Dirty;
450 out_msg.MessageSize := MessageSizeType:Response_Data;
454 action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
455 peek(L1RequestL2Network_in, RequestMsg) {
456 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
457 assert(is_valid(cache_entry));
458 out_msg.addr := address;
459 out_msg.Type := CoherenceResponseType:DATA;
460 out_msg.Sender := machineID;
461 out_msg.Destination.add(in_msg.Requestor);
462 out_msg.DataBlk := cache_entry.DataBlk;
463 out_msg.MessageSize := MessageSizeType:Response_Data;
465 out_msg.AckCount := 0 - cache_entry.Sharers.count();
466 if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
467 out_msg.AckCount := out_msg.AckCount + 1;
473 action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
474 peek(L1RequestL2Network_in, RequestMsg) {
475 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
476 assert(is_valid(cache_entry));
477 out_msg.addr := address;
478 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
479 out_msg.Sender := machineID;
480 out_msg.Destination.add(in_msg.Requestor);
481 out_msg.DataBlk := cache_entry.DataBlk;
482 out_msg.MessageSize := MessageSizeType:Response_Data;
484 out_msg.AckCount := 0 - cache_entry.Sharers.count();
485 if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
486 out_msg.AckCount := out_msg.AckCount + 1;
492 action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
493 peek(L1RequestL2Network_in, RequestMsg) {
494 enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
495 assert(is_valid(cache_entry));
496 out_msg.addr := address;
497 out_msg.Type := CoherenceResponseType:DATA;
498 out_msg.Sender := machineID;
499 out_msg.Destination.add(in_msg.Requestor);
500 out_msg.DataBlk := cache_entry.DataBlk;
501 out_msg.MessageSize := MessageSizeType:Response_Data;
502 out_msg.AckCount := 0;
507 action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
508 assert(is_valid(tbe));
509 assert(tbe.L1_GetS_IDs.count() > 0);
510 enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
511 assert(is_valid(cache_entry));
512 out_msg.addr := address;
513 out_msg.Type := CoherenceResponseType:DATA;
514 out_msg.Sender := machineID;
515 out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
516 out_msg.DataBlk := cache_entry.DataBlk;
517 out_msg.MessageSize := MessageSizeType:Response_Data;
521 action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
522 assert(is_valid(tbe));
523 assert(tbe.L1_GetS_IDs.count() == 1);
524 enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
525 assert(is_valid(cache_entry));
526 out_msg.addr := address;
527 out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
528 out_msg.Sender := machineID;
529 out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
530 out_msg.DataBlk := cache_entry.DataBlk;
531 out_msg.MessageSize := MessageSizeType:Response_Data;
535 action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
536 enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
537 assert(is_valid(tbe));
538 assert(is_valid(cache_entry));
539 out_msg.addr := address;
540 out_msg.Type := CoherenceResponseType:DATA;
541 out_msg.Sender := machineID;
542 out_msg.Destination.add(tbe.L1_GetX_ID);
543 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
544 out_msg.DataBlk := cache_entry.DataBlk;
545 DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
546 out_msg.addr, out_msg.Destination, out_msg.DataBlk);
547 out_msg.MessageSize := MessageSizeType:Response_Data;
551 action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
552 enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
553 assert(is_valid(cache_entry));
554 out_msg.addr := address;
555 out_msg.Type := CoherenceRequestType:INV;
556 out_msg.Requestor := machineID;
557 out_msg.Destination := cache_entry.Sharers;
558 out_msg.MessageSize := MessageSizeType:Request_Control;
562 action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
563 peek(L1RequestL2Network_in, RequestMsg) {
564 enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
565 assert(is_valid(cache_entry));
566 out_msg.addr := address;
567 out_msg.Type := CoherenceRequestType:INV;
568 out_msg.Requestor := in_msg.Requestor;
569 out_msg.Destination := cache_entry.Sharers;
570 out_msg.MessageSize := MessageSizeType:Request_Control;
575 action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
576 peek(L1RequestL2Network_in, RequestMsg) {
577 enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
578 assert(is_valid(cache_entry));
579 out_msg.addr := address;
580 out_msg.Type := CoherenceRequestType:INV;
581 out_msg.Requestor := in_msg.Requestor;
582 out_msg.Destination := cache_entry.Sharers;
583 out_msg.Destination.remove(in_msg.Requestor);
584 out_msg.MessageSize := MessageSizeType:Request_Control;
590 action(i_allocateTBE, "i", desc="Allocate TBE for request") {
591 check_allocate(TBEs);
592 assert(is_valid(cache_entry));
593 TBEs.allocate(address);
594 set_tbe(TBEs[address]);
595 tbe.L1_GetS_IDs.clear();
596 tbe.DataBlk := cache_entry.DataBlk;
597 tbe.Dirty := cache_entry.Dirty;
598 tbe.pendingAcks := cache_entry.Sharers.count();
601 action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
602 TBEs.deallocate(address);
606 action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
607 profileMsgDelay(0, L1RequestL2Network_in.dequeue());
610 action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
611 profileMsgDelay(0, L1unblockNetwork_in.dequeue());
614 action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
615 profileMsgDelay(1, responseL2Network_in.dequeue());
618 action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
619 peek(responseL2Network_in, ResponseMsg) {
620 assert(is_valid(cache_entry));
621 cache_entry.DataBlk := in_msg.DataBlk;
623 cache_entry.Dirty := in_msg.Dirty;
628 action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
629 peek(L1RequestL2Network_in, RequestMsg) {
630 assert(is_valid(cache_entry));
632 cache_entry.DataBlk := in_msg.DataBlk;
633 cache_entry.Dirty := in_msg.Dirty;
638 action(q_updateAck, "q", desc="update pending ack count") {
639 peek(responseL2Network_in, ResponseMsg) {
640 assert(is_valid(tbe));
641 tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
642 APPEND_TRANSITION_COMMENT(in_msg.AckCount);
643 APPEND_TRANSITION_COMMENT(" p: ");
644 APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
648 action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
649 peek(responseL2Network_in, ResponseMsg) {
650 assert(is_valid(tbe));
651 tbe.DataBlk := in_msg.DataBlk;
652 tbe.Dirty := in_msg.Dirty;
656 action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
657 peek(L1RequestL2Network_in, RequestMsg) {
658 assert(is_valid(tbe));
659 tbe.L1_GetS_IDs.add(in_msg.Requestor);
663 action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
664 peek(L1RequestL2Network_in, RequestMsg) {
665 assert(is_valid(tbe));
666 tbe.L1_GetX_ID := in_msg.Requestor;
670 action(set_setMRU, "\set", desc="set the MRU entry") {
671 L2cache.setMRU(address);
674 action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
675 if (is_invalid(cache_entry)) {
676 set_cache_entry(L2cache.allocate(address, new Entry));
680 action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
681 L2cache.deallocate(address);
685 action(t_sendWBAck, "t", desc="Send writeback ACK") {
686 peek(L1RequestL2Network_in, RequestMsg) {
687 enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
688 out_msg.addr := address;
689 out_msg.Type := CoherenceResponseType:WB_ACK;
690 out_msg.Sender := machineID;
691 out_msg.Destination.add(in_msg.Requestor);
692 out_msg.MessageSize := MessageSizeType:Response_Control;
697 action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
698 peek(L1RequestL2Network_in, RequestMsg) {
699 enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
700 assert(is_valid(cache_entry));
701 out_msg.addr := address;
702 out_msg.Type := CoherenceResponseType:ACK;
703 out_msg.Sender := machineID;
704 out_msg.Destination.add(in_msg.Requestor);
705 out_msg.MessageSize := MessageSizeType:Response_Control;
706 // upgrader doesn't get ack from itself, hence the + 1
707 out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
712 action(uu_profileMiss, "\um", desc="Profile the demand miss") {
713 ++L2cache.demand_misses;
716 action(uu_profileHit, "\uh", desc="Profile the demand hit") {
717 ++L2cache.demand_hits;
720 action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
721 peek(L1RequestL2Network_in, RequestMsg) {
722 assert(is_valid(cache_entry));
723 addSharer(address, in_msg.Requestor, cache_entry);
724 APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
728 action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
729 peek(L1unblockNetwork_in, ResponseMsg) {
730 assert(is_valid(cache_entry));
731 addSharer(address, in_msg.Sender, cache_entry);
735 action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
736 peek(L1RequestL2Network_in, RequestMsg) {
737 assert(is_valid(cache_entry));
738 cache_entry.Sharers.remove(in_msg.Requestor);
742 action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
743 peek(L1RequestL2Network_in, RequestMsg) {
744 assert(is_valid(cache_entry));
745 cache_entry.Sharers.clear();
749 action(mm_markExclusive, "\m", desc="set the exclusive owner") {
750 peek(L1RequestL2Network_in, RequestMsg) {
751 assert(is_valid(cache_entry));
752 cache_entry.Sharers.clear();
753 cache_entry.Exclusive := in_msg.Requestor;
754 addSharer(address, in_msg.Requestor, cache_entry);
758 action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
759 peek(L1unblockNetwork_in, ResponseMsg) {
760 assert(is_valid(cache_entry));
761 cache_entry.Sharers.clear();
762 cache_entry.Exclusive := in_msg.Sender;
763 addSharer(address, in_msg.Sender, cache_entry);
767 action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
768 stall_and_wait(L1RequestL2Network_in, address);
771 action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
772 responseL2Network_in.recycle();
775 action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
776 wakeUpBuffers(address);
779 //*****************************************************
781 //*****************************************************
784 //===============================================
787 // Transitions from I (Idle)
788 transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
790 jj_popL1RequestQueue;
793 transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
795 jj_popL1RequestQueue;
798 transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
799 zz_stallAndWaitL1RequestQueue;
802 transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
803 zn_recycleResponseNetwork;
806 transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
807 o_popIncomingResponseQueue;
811 transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
812 zz_stallAndWaitL1RequestQueue;
816 transition(NP, L1_GETS, ISS) {
817 qq_allocateL2CacheBlock;
822 a_issueFetchToMemory;
824 jj_popL1RequestQueue;
827 transition(NP, L1_GET_INSTR, IS) {
828 qq_allocateL2CacheBlock;
833 a_issueFetchToMemory;
835 jj_popL1RequestQueue;
838 transition(NP, L1_GETX, IM) {
839 qq_allocateL2CacheBlock;
844 a_issueFetchToMemory;
846 jj_popL1RequestQueue;
850 // transitions from IS/IM
852 transition(ISS, Mem_Data, MT_MB) {
854 ex_sendExclusiveDataToGetSRequestors;
856 o_popIncomingResponseQueue;
859 transition(IS, Mem_Data, SS) {
861 e_sendDataToGetSRequestors;
863 o_popIncomingResponseQueue;
867 transition(IM, Mem_Data, MT_MB) {
869 ee_sendDataToGetXRequestor;
871 o_popIncomingResponseQueue;
874 transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
878 jj_popL1RequestQueue;
881 transition({IS, ISS}, L1_GETX) {
882 zz_stallAndWaitL1RequestQueue;
885 transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
886 zz_stallAndWaitL1RequestQueue;
889 // transitions from SS
890 transition(SS, {L1_GETS, L1_GET_INSTR}) {
891 ds_sendSharedDataToRequestor;
895 jj_popL1RequestQueue;
899 transition(SS, L1_GETX, SS_MB) {
900 d_sendDataToRequestor;
901 // fw_sendFwdInvToSharers;
902 fwm_sendFwdInvToSharersMinusRequestor;
905 jj_popL1RequestQueue;
908 transition(SS, L1_UPGRADE, SS_MB) {
909 fwm_sendFwdInvToSharersMinusRequestor;
910 ts_sendInvAckToUpgrader;
913 jj_popL1RequestQueue;
916 transition(SS, L2_Replacement_clean, I_I) {
919 rr_deallocateL2CacheBlock;
922 transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
925 rr_deallocateL2CacheBlock;
929 transition(M, L1_GETX, MT_MB) {
930 d_sendDataToRequestor;
933 jj_popL1RequestQueue;
936 transition(M, L1_GET_INSTR, SS) {
937 d_sendDataToRequestor;
941 jj_popL1RequestQueue;
944 transition(M, L1_GETS, MT_MB) {
945 dd_sendExclusiveDataToRequestor;
948 jj_popL1RequestQueue;
951 transition(M, {L2_Replacement, MEM_Inv}, M_I) {
953 c_exclusiveReplacement;
954 rr_deallocateL2CacheBlock;
957 transition(M, L2_Replacement_clean, M_I) {
959 c_exclusiveCleanReplacement;
960 rr_deallocateL2CacheBlock;
964 // transitions from MT
966 transition(MT, L1_GETX, MT_MB) {
967 b_forwardRequestToExclusive;
970 jj_popL1RequestQueue;
974 transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
975 b_forwardRequestToExclusive;
978 jj_popL1RequestQueue;
981 transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
984 rr_deallocateL2CacheBlock;
987 transition(MT, L2_Replacement_clean, MCT_I) {
990 rr_deallocateL2CacheBlock;
993 transition(MT, L1_PUTX, M) {
995 mr_writeDataToCacheFromRequest;
997 jj_popL1RequestQueue;
1000 transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
1001 // update actual directory
1002 mmu_markExclusiveFromUnblock;
1004 kd_wakeUpDependents;
1007 transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
1008 zz_stallAndWaitL1RequestQueue;
1011 transition(MT_IIB, Unblock, MT_IB) {
1012 nnu_addSharerFromUnblock;
1016 transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
1018 o_popIncomingResponseQueue;
1021 transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
1023 o_popIncomingResponseQueue;
1024 kd_wakeUpDependents;
1027 transition(MT_SB, Unblock, SS) {
1028 nnu_addSharerFromUnblock;
1030 kd_wakeUpDependents;
1034 transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
1035 zz_stallAndWaitL1RequestQueue;
1038 transition(I_I, Ack) {
1040 o_popIncomingResponseQueue;
1043 transition(I_I, Ack_all, M_I) {
1044 c_exclusiveCleanReplacement;
1045 o_popIncomingResponseQueue;
1048 transition({MT_I, MCT_I}, WB_Data, M_I) {
1050 ct_exclusiveReplacementFromTBE;
1051 o_popIncomingResponseQueue;
1054 transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
1055 c_exclusiveCleanReplacement;
1056 o_popIncomingResponseQueue;
1059 transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
1060 zz_stallAndWaitL1RequestQueue;
1063 // L1 never changed Dirty data
1064 transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
1065 ct_exclusiveReplacementFromTBE;
1066 o_popIncomingResponseQueue;
1069 transition(MT_I, {L1_PUTX, L1_PUTX_old}){
1070 zz_stallAndWaitL1RequestQueue;
1073 // possible race between unblock and immediate replacement
1074 transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
1075 zz_stallAndWaitL1RequestQueue;
1078 transition(S_I, Ack) {
1080 o_popIncomingResponseQueue;
1083 transition(S_I, Ack_all, M_I) {
1084 ct_exclusiveReplacementFromTBE;
1085 o_popIncomingResponseQueue;
1088 transition(M_I, Mem_Ack, NP) {
1090 o_popIncomingResponseQueue;
1091 kd_wakeUpDependents;