src/mem/protocol/MESI_Two_Level-L2cache.sm

   1 /*
   2  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
  30  : CacheMemory * L2cache;
  31    Cycles l2_request_latency := 2;
  32    Cycles l2_response_latency := 2;
  33    Cycles to_l1_latency := 1;
  34
  35   // Message Queues
  36   // From local bank of L2 cache TO the network
  37   MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0",
  38     vnet_type="request";  // this L2 bank -> Memory
  39
  40   MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2",
  41     vnet_type="request";  // this L2 bank -> a local L1
  42
  43   MessageBuffer * responseFromL2Cache, network="To", virtual_network="1",
  44     vnet_type="response";  // this L2 bank -> a local L1 || Memory
  45
  46   // FROM the network to this local bank of L2 cache
  47   MessageBuffer * unblockToL2Cache, network="From", virtual_network="2",
  48     vnet_type="unblock";  // a local L1 || Memory -> this L2 bank
  49
  50   MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
  51     vnet_type="request";  // a local L1 -> this L2 bank
  52
  53   MessageBuffer * responseToL2Cache, network="From", virtual_network="1",
  54     vnet_type="response";  // a local L1 || Memory -> this L2 bank
  55 {
  56   // STATES
  57   state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
  58     // Base states
  59     NP, AccessPermission:Invalid, desc="Not present in either cache";
  60     SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
  61     M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
  62     MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
  63
  64     // L2 replacement
  65     M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
  66     MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
  67     MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
  68     I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
  69     S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
  70
  71     // Transient States for fetching data from memory
  72     ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
  73     IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
  74     IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
  75
  76     // Blocking states
  77     SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
  78     MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
  79
  80     MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
  81     MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
  82     MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data,  waiting for unblock";
  83
  84   }
  85
  86   // EVENTS
  87   enumeration(Event, desc="L2 Cache events") {
  88     // L2 events
  89
  90     // events initiated by the local L1s
  91     L1_GET_INSTR,            desc="a L1I GET INSTR request for a block maped to us";
  92     L1_GETS,                 desc="a L1D GETS request for a block maped to us";
  93     L1_GETX,                 desc="a L1D GETX request for a block maped to us";
  94     L1_UPGRADE,                 desc="a L1D GETX request for a block maped to us";
  95
  96     L1_PUTX,                 desc="L1 replacing data";
  97     L1_PUTX_old,             desc="L1 replacing data, but no longer sharer";
  98
  99     // events initiated by this L2
 100     L2_Replacement,     desc="L2 Replacement", format="!r";
 101     L2_Replacement_clean,     desc="L2 Replacement, but data is clean", format="!r";
 102
 103     // events from memory controller
 104     Mem_Data,     desc="data from memory", format="!r";
 105     Mem_Ack,     desc="ack from memory", format="!r";
 106
 107     // M->S data writeback
 108     WB_Data,  desc="data from L1";
 109     WB_Data_clean,  desc="clean data from L1";
 110     Ack,      desc="writeback ack";
 111     Ack_all,      desc="writeback ack";
 112
 113     Unblock, desc="Unblock from L1 requestor";
 114     Exclusive_Unblock, desc="Unblock from L1 requestor";
 115
 116     MEM_Inv, desc="Invalidation from directory";
 117   }
 118
 119   // TYPES
 120
 121   // CacheEntry
 122   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 123     State CacheState,          desc="cache state";
 124     NetDest Sharers,               desc="tracks the L1 shares on-chip";
 125     MachineID Exclusive,          desc="Exclusive holder of block";
 126     DataBlock DataBlk,       desc="data for the block";
 127     bool Dirty, default="false", desc="data is dirty";
 128   }
 129
 130   // TBE fields
 131   structure(TBE, desc="...") {
 132     Addr addr,            desc="Physical address for this TBE";
 133     State TBEState,             desc="Transient state";
 134     DataBlock DataBlk,          desc="Buffer for the data block";
 135     bool Dirty, default="false", desc="Data is Dirty";
 136
 137     NetDest L1_GetS_IDs,            desc="Set of the internal processors that want the block in shared state";
 138     MachineID L1_GetX_ID,          desc="ID of the L1 cache to forward the block to once we get a response";
 139     int pendingAcks,            desc="number of pending acks for invalidates during writeback";
 140   }
 141
 142   structure(TBETable, external="yes") {
 143     TBE lookup(Addr);
 144     void allocate(Addr);
 145     void deallocate(Addr);
 146     bool isPresent(Addr);
 147   }
 148
 149   TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 150
 151   Tick clockEdge();
 152   Tick cyclesToTicks(Cycles c);
 153   Cycles ticksToCycles(Tick t);
 154
 155   void set_cache_entry(AbstractCacheEntry a);
 156   void unset_cache_entry();
 157   void set_tbe(TBE a);
 158   void unset_tbe();
 159   void wakeUpBuffers(Addr a);
 160   void profileMsgDelay(int virtualNetworkType, Cycles c);
 161
 162   // inclusive cache, returns L2 entries only
 163   Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
 164     return static_cast(Entry, "pointer", L2cache[addr]);
 165   }
 166
 167   bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) {
 168     if (is_valid(cache_entry)) {
 169       return cache_entry.Sharers.isElement(requestor);
 170     } else {
 171       return false;
 172     }
 173   }
 174
 175   void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
 176     assert(is_valid(cache_entry));
 177     DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %#x\n",
 178             machineID, requestor, addr);
 179     cache_entry.Sharers.add(requestor);
 180   }
 181
 182   State getState(TBE tbe, Entry cache_entry, Addr addr) {
 183     if(is_valid(tbe)) {
 184       return tbe.TBEState;
 185     } else if (is_valid(cache_entry)) {
 186       return cache_entry.CacheState;
 187     }
 188     return State:NP;
 189   }
 190
 191   void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
 192     // MUST CHANGE
 193     if (is_valid(tbe)) {
 194       tbe.TBEState := state;
 195     }
 196
 197     if (is_valid(cache_entry)) {
 198       cache_entry.CacheState := state;
 199     }
 200   }
 201
 202   AccessPermission getAccessPermission(Addr addr) {
 203     TBE tbe := TBEs[addr];
 204     if(is_valid(tbe)) {
 205       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
 206       return L2Cache_State_to_permission(tbe.TBEState);
 207     }
 208
 209     Entry cache_entry := getCacheEntry(addr);
 210     if(is_valid(cache_entry)) {
 211       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
 212       return L2Cache_State_to_permission(cache_entry.CacheState);
 213     }
 214
 215     DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
 216     return AccessPermission:NotPresent;
 217   }
 218
 219   void functionalRead(Addr addr, Packet *pkt) {
 220     TBE tbe := TBEs[addr];
 221     if(is_valid(tbe)) {
 222       testAndRead(addr, tbe.DataBlk, pkt);
 223     } else {
 224       testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
 225     }
 226   }
 227
 228   int functionalWrite(Addr addr, Packet *pkt) {
 229     int num_functional_writes := 0;
 230
 231     TBE tbe := TBEs[addr];
 232     if(is_valid(tbe)) {
 233       num_functional_writes := num_functional_writes +
 234         testAndWrite(addr, tbe.DataBlk, pkt);
 235       return num_functional_writes;
 236     }
 237
 238     num_functional_writes := num_functional_writes +
 239         testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
 240     return num_functional_writes;
 241   }
 242
 243   void setAccessPermission(Entry cache_entry, Addr addr, State state) {
 244     if (is_valid(cache_entry)) {
 245       cache_entry.changePermission(L2Cache_State_to_permission(state));
 246     }
 247   }
 248
 249   Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr,
 250                                       MachineID requestor, Entry cache_entry) {
 251     if(type == CoherenceRequestType:GETS) {
 252       return Event:L1_GETS;
 253     } else if(type == CoherenceRequestType:GET_INSTR) {
 254       return Event:L1_GET_INSTR;
 255     } else if (type == CoherenceRequestType:GETX) {
 256       return Event:L1_GETX;
 257     } else if (type == CoherenceRequestType:UPGRADE) {
 258       if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
 259         return Event:L1_UPGRADE;
 260       } else {
 261         return Event:L1_GETX;
 262       }
 263     } else if (type == CoherenceRequestType:PUTX) {
 264       if (isSharer(addr, requestor, cache_entry)) {
 265         return Event:L1_PUTX;
 266       } else {
 267         return Event:L1_PUTX_old;
 268       }
 269     } else {
 270       DPRINTF(RubySlicc, "address: %#x, Request Type: %s\n", addr, type);
 271       error("Invalid L1 forwarded request type");
 272     }
 273   }
 274
 275   int getPendingAcks(TBE tbe) {
 276     return tbe.pendingAcks;
 277   }
 278
 279   bool isDirty(Entry cache_entry) {
 280     assert(is_valid(cache_entry));
 281     return cache_entry.Dirty;
 282   }
 283
 284   // ** OUT_PORTS **
 285
 286   out_port(L1RequestL2Network_out, RequestMsg, L1RequestFromL2Cache);
 287   out_port(DirRequestL2Network_out, RequestMsg, DirRequestFromL2Cache);
 288   out_port(responseL2Network_out, ResponseMsg, responseFromL2Cache);
 289
 290
 291   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
 292     if(L1unblockNetwork_in.isReady(clockEdge())) {
 293       peek(L1unblockNetwork_in,  ResponseMsg) {
 294         Entry cache_entry := getCacheEntry(in_msg.addr);
 295         TBE tbe := TBEs[in_msg.addr];
 296         DPRINTF(RubySlicc, "Addr: %#x State: %s Sender: %s Type: %s Dest: %s\n",
 297                 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
 298                 in_msg.Sender, in_msg.Type, in_msg.Destination);
 299
 300         assert(in_msg.Destination.isElement(machineID));
 301         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
 302           trigger(Event:Exclusive_Unblock, in_msg.addr, cache_entry, tbe);
 303         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
 304           trigger(Event:Unblock, in_msg.addr, cache_entry, tbe);
 305         } else {
 306           error("unknown unblock message");
 307         }
 308       }
 309     }
 310   }
 311
 312   // Response  L2 Network - response msg to this particular L2 bank
 313   in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
 314     if (responseL2Network_in.isReady(clockEdge())) {
 315       peek(responseL2Network_in, ResponseMsg) {
 316         // test wether it's from a local L1 or an off chip source
 317         assert(in_msg.Destination.isElement(machineID));
 318         Entry cache_entry := getCacheEntry(in_msg.addr);
 319         TBE tbe := TBEs[in_msg.addr];
 320
 321         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 322           if(in_msg.Type == CoherenceResponseType:DATA) {
 323             if (in_msg.Dirty) {
 324               trigger(Event:WB_Data, in_msg.addr, cache_entry, tbe);
 325             } else {
 326               trigger(Event:WB_Data_clean, in_msg.addr, cache_entry, tbe);
 327             }
 328           } else if (in_msg.Type == CoherenceResponseType:ACK) {
 329             if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
 330               trigger(Event:Ack_all, in_msg.addr, cache_entry, tbe);
 331             } else {
 332               trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
 333             }
 334           } else {
 335             error("unknown message type");
 336           }
 337
 338         } else { // external message
 339           if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
 340               trigger(Event:Mem_Data, in_msg.addr, cache_entry, tbe);
 341           } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
 342               trigger(Event:Mem_Ack, in_msg.addr, cache_entry, tbe);
 343           } else if(in_msg.Type == CoherenceResponseType:INV) {
 344               trigger(Event:MEM_Inv, in_msg.addr, cache_entry, tbe);
 345           } else {
 346             error("unknown message type");
 347           }
 348         }
 349       }
 350     }  // if not ready, do nothing
 351   }
 352
 353   // L1 Request
 354   in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
 355     if(L1RequestL2Network_in.isReady(clockEdge())) {
 356       peek(L1RequestL2Network_in,  RequestMsg) {
 357         Entry cache_entry := getCacheEntry(in_msg.addr);
 358         TBE tbe := TBEs[in_msg.addr];
 359
 360         DPRINTF(RubySlicc, "Addr: %#x State: %s Req: %s Type: %s Dest: %s\n",
 361                 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
 362                 in_msg.Requestor, in_msg.Type, in_msg.Destination);
 363
 364         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
 365         assert(in_msg.Destination.isElement(machineID));
 366
 367         if (is_valid(cache_entry)) {
 368           // The L2 contains the block, so proceeded with handling the request
 369           trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
 370                                                 in_msg.Requestor, cache_entry),
 371                   in_msg.addr, cache_entry, tbe);
 372         } else {
 373           if (L2cache.cacheAvail(in_msg.addr)) {
 374             // L2 does't have the line, but we have space for it in the L2
 375             trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.addr,
 376                                                   in_msg.Requestor, cache_entry),
 377                     in_msg.addr, cache_entry, tbe);
 378           } else {
 379             // No room in the L2, so we need to make room before handling the request
 380             Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.addr));
 381             if (isDirty(L2cache_entry)) {
 382               trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr),
 383                       L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
 384             } else {
 385               trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.addr),
 386                       L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.addr)]);
 387             }
 388           }
 389         }
 390       }
 391     }
 392   }
 393
 394
 395   // ACTIONS
 396
 397   action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
 398     peek(L1RequestL2Network_in, RequestMsg) {
 399       enqueue(DirRequestL2Network_out, RequestMsg, l2_request_latency) {
 400         out_msg.addr := address;
 401         out_msg.Type := CoherenceRequestType:GETS;
 402         out_msg.Requestor := machineID;
 403         out_msg.Destination.add(map_Address_to_Directory(address));
 404         out_msg.MessageSize := MessageSizeType:Control;
 405       }
 406     }
 407   }
 408
 409   action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
 410     peek(L1RequestL2Network_in, RequestMsg) {
 411       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 412         assert(is_valid(cache_entry));
 413         out_msg.addr := address;
 414         out_msg.Type := in_msg.Type;
 415         out_msg.Requestor := in_msg.Requestor;
 416         out_msg.Destination.add(cache_entry.Exclusive);
 417         out_msg.MessageSize := MessageSizeType:Request_Control;
 418       }
 419     }
 420   }
 421
 422   action(c_exclusiveReplacement, "c", desc="Send data to memory") {
 423     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 424       assert(is_valid(cache_entry));
 425       out_msg.addr := address;
 426       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 427       out_msg.Sender := machineID;
 428       out_msg.Destination.add(map_Address_to_Directory(address));
 429       out_msg.DataBlk := cache_entry.DataBlk;
 430       out_msg.Dirty := cache_entry.Dirty;
 431       out_msg.MessageSize := MessageSizeType:Response_Data;
 432     }
 433   }
 434
 435   action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
 436     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 437       out_msg.addr := address;
 438       out_msg.Type := CoherenceResponseType:ACK;
 439       out_msg.Sender := machineID;
 440       out_msg.Destination.add(map_Address_to_Directory(address));
 441       out_msg.MessageSize := MessageSizeType:Response_Control;
 442     }
 443   }
 444
 445   action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
 446     enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 447       assert(is_valid(tbe));
 448       out_msg.addr := address;
 449       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
 450       out_msg.Sender := machineID;
 451       out_msg.Destination.add(map_Address_to_Directory(address));
 452       out_msg.DataBlk := tbe.DataBlk;
 453       out_msg.Dirty := tbe.Dirty;
 454       out_msg.MessageSize := MessageSizeType:Response_Data;
 455     }
 456   }
 457
 458   action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
 459     peek(L1RequestL2Network_in, RequestMsg) {
 460       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 461         assert(is_valid(cache_entry));
 462         out_msg.addr := address;
 463         out_msg.Type := CoherenceResponseType:DATA;
 464         out_msg.Sender := machineID;
 465         out_msg.Destination.add(in_msg.Requestor);
 466         out_msg.DataBlk := cache_entry.DataBlk;
 467         out_msg.MessageSize := MessageSizeType:Response_Data;
 468
 469         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 470         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 471           out_msg.AckCount := out_msg.AckCount + 1;
 472         }
 473       }
 474     }
 475   }
 476
 477   action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
 478     peek(L1RequestL2Network_in, RequestMsg) {
 479       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 480         assert(is_valid(cache_entry));
 481         out_msg.addr := address;
 482         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 483         out_msg.Sender := machineID;
 484         out_msg.Destination.add(in_msg.Requestor);
 485         out_msg.DataBlk := cache_entry.DataBlk;
 486         out_msg.MessageSize := MessageSizeType:Response_Data;
 487
 488         out_msg.AckCount := 0 - cache_entry.Sharers.count();
 489         if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
 490           out_msg.AckCount := out_msg.AckCount + 1;
 491         }
 492       }
 493     }
 494   }
 495
 496   action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
 497     peek(L1RequestL2Network_in, RequestMsg) {
 498       enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {
 499         assert(is_valid(cache_entry));
 500         out_msg.addr := address;
 501         out_msg.Type := CoherenceResponseType:DATA;
 502         out_msg.Sender := machineID;
 503         out_msg.Destination.add(in_msg.Requestor);
 504         out_msg.DataBlk := cache_entry.DataBlk;
 505         out_msg.MessageSize := MessageSizeType:Response_Data;
 506         out_msg.AckCount := 0;
 507       }
 508     }
 509   }
 510
 511   action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
 512     assert(is_valid(tbe));
 513     assert(tbe.L1_GetS_IDs.count() > 0);
 514     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 515       assert(is_valid(cache_entry));
 516       out_msg.addr := address;
 517       out_msg.Type := CoherenceResponseType:DATA;
 518       out_msg.Sender := machineID;
 519       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 520       out_msg.DataBlk := cache_entry.DataBlk;
 521       out_msg.MessageSize := MessageSizeType:Response_Data;
 522     }
 523   }
 524
 525   action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
 526     assert(is_valid(tbe));
 527     assert(tbe.L1_GetS_IDs.count() == 1);
 528     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 529       assert(is_valid(cache_entry));
 530       out_msg.addr := address;
 531       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 532       out_msg.Sender := machineID;
 533       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
 534       out_msg.DataBlk := cache_entry.DataBlk;
 535       out_msg.MessageSize := MessageSizeType:Response_Data;
 536     }
 537   }
 538
 539   action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
 540     enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 541       assert(is_valid(tbe));
 542       assert(is_valid(cache_entry));
 543       out_msg.addr := address;
 544       out_msg.Type := CoherenceResponseType:DATA;
 545       out_msg.Sender := machineID;
 546       out_msg.Destination.add(tbe.L1_GetX_ID);
 547       DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
 548       out_msg.DataBlk := cache_entry.DataBlk;
 549       DPRINTF(RubySlicc, "Address: %#x, Destination: %s, DataBlock: %s\n",
 550               out_msg.addr, out_msg.Destination, out_msg.DataBlk);
 551       out_msg.MessageSize := MessageSizeType:Response_Data;
 552     }
 553   }
 554
 555   action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
 556     enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 557       assert(is_valid(cache_entry));
 558       out_msg.addr := address;
 559       out_msg.Type := CoherenceRequestType:INV;
 560       out_msg.Requestor := machineID;
 561       out_msg.Destination := cache_entry.Sharers;
 562       out_msg.MessageSize := MessageSizeType:Request_Control;
 563     }
 564   }
 565
 566   action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
 567     peek(L1RequestL2Network_in, RequestMsg) {
 568       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 569         assert(is_valid(cache_entry));
 570         out_msg.addr := address;
 571         out_msg.Type := CoherenceRequestType:INV;
 572         out_msg.Requestor := in_msg.Requestor;
 573         out_msg.Destination := cache_entry.Sharers;
 574         out_msg.MessageSize := MessageSizeType:Request_Control;
 575       }
 576     }
 577   }
 578
 579   action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
 580     peek(L1RequestL2Network_in, RequestMsg) {
 581       enqueue(L1RequestL2Network_out, RequestMsg, to_l1_latency) {
 582         assert(is_valid(cache_entry));
 583         out_msg.addr := address;
 584         out_msg.Type := CoherenceRequestType:INV;
 585         out_msg.Requestor := in_msg.Requestor;
 586         out_msg.Destination := cache_entry.Sharers;
 587         out_msg.Destination.remove(in_msg.Requestor);
 588         out_msg.MessageSize := MessageSizeType:Request_Control;
 589       }
 590     }
 591   }
 592
 593   // OTHER ACTIONS
 594   action(i_allocateTBE, "i", desc="Allocate TBE for request") {
 595     check_allocate(TBEs);
 596     assert(is_valid(cache_entry));
 597     TBEs.allocate(address);
 598     set_tbe(TBEs[address]);
 599     tbe.L1_GetS_IDs.clear();
 600     tbe.DataBlk := cache_entry.DataBlk;
 601     tbe.Dirty := cache_entry.Dirty;
 602     tbe.pendingAcks := cache_entry.Sharers.count();
 603   }
 604
 605   action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
 606     TBEs.deallocate(address);
 607     unset_tbe();
 608   }
 609
 610   action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
 611     Tick delay := L1RequestL2Network_in.dequeue(clockEdge());
 612     profileMsgDelay(0, ticksToCycles(delay));
 613   }
 614
 615   action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
 616     Tick delay := L1unblockNetwork_in.dequeue(clockEdge());
 617     profileMsgDelay(0, ticksToCycles(delay));
 618   }
 619
 620   action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
 621     Tick delay := responseL2Network_in.dequeue(clockEdge());
 622     profileMsgDelay(1, ticksToCycles(delay));
 623   }
 624
 625   action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
 626     peek(responseL2Network_in, ResponseMsg) {
 627       assert(is_valid(cache_entry));
 628       cache_entry.DataBlk := in_msg.DataBlk;
 629       if (in_msg.Dirty) {
 630         cache_entry.Dirty := in_msg.Dirty;
 631       }
 632     }
 633   }
 634
 635   action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
 636     peek(L1RequestL2Network_in, RequestMsg) {
 637       assert(is_valid(cache_entry));
 638       if (in_msg.Dirty) {
 639         cache_entry.DataBlk := in_msg.DataBlk;
 640         cache_entry.Dirty := in_msg.Dirty;
 641       }
 642     }
 643   }
 644
 645   action(q_updateAck, "q", desc="update pending ack count") {
 646     peek(responseL2Network_in, ResponseMsg) {
 647       assert(is_valid(tbe));
 648       tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
 649       APPEND_TRANSITION_COMMENT(in_msg.AckCount);
 650       APPEND_TRANSITION_COMMENT(" p: ");
 651       APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
 652     }
 653   }
 654
 655   action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
 656     peek(responseL2Network_in, ResponseMsg) {
 657       assert(is_valid(tbe));
 658       tbe.DataBlk := in_msg.DataBlk;
 659       tbe.Dirty := in_msg.Dirty;
 660     }
 661   }
 662
 663   action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
 664     peek(L1RequestL2Network_in, RequestMsg) {
 665       assert(is_valid(tbe));
 666       tbe.L1_GetS_IDs.add(in_msg.Requestor);
 667     }
 668   }
 669
 670   action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
 671     peek(L1RequestL2Network_in, RequestMsg) {
 672       assert(is_valid(tbe));
 673       tbe.L1_GetX_ID := in_msg.Requestor;
 674     }
 675   }
 676
 677   action(set_setMRU, "\set", desc="set the MRU entry") {
 678     L2cache.setMRU(address);
 679   }
 680
 681   action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
 682     if (is_invalid(cache_entry)) {
 683       set_cache_entry(L2cache.allocate(address, new Entry));
 684     }
 685   }
 686
 687   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
 688     L2cache.deallocate(address);
 689     unset_cache_entry();
 690   }
 691
 692   action(t_sendWBAck, "t", desc="Send writeback ACK") {
 693     peek(L1RequestL2Network_in, RequestMsg) {
 694       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 695         out_msg.addr := address;
 696         out_msg.Type := CoherenceResponseType:WB_ACK;
 697         out_msg.Sender := machineID;
 698         out_msg.Destination.add(in_msg.Requestor);
 699         out_msg.MessageSize := MessageSizeType:Response_Control;
 700       }
 701     }
 702   }
 703
 704   action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
 705     peek(L1RequestL2Network_in, RequestMsg) {
 706       enqueue(responseL2Network_out, ResponseMsg, to_l1_latency) {
 707         assert(is_valid(cache_entry));
 708         out_msg.addr := address;
 709         out_msg.Type := CoherenceResponseType:ACK;
 710         out_msg.Sender := machineID;
 711         out_msg.Destination.add(in_msg.Requestor);
 712         out_msg.MessageSize := MessageSizeType:Response_Control;
 713         // upgrader doesn't get ack from itself, hence the + 1
 714         out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
 715       }
 716     }
 717   }
 718
 719   action(uu_profileMiss, "\um", desc="Profile the demand miss") {
 720       ++L2cache.demand_misses;
 721   }
 722
 723   action(uu_profileHit, "\uh", desc="Profile the demand hit") {
 724       ++L2cache.demand_hits;
 725   }
 726
 727   action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
 728     peek(L1RequestL2Network_in, RequestMsg) {
 729       assert(is_valid(cache_entry));
 730       addSharer(address, in_msg.Requestor, cache_entry);
 731       APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
 732     }
 733   }
 734
 735   action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
 736     peek(L1unblockNetwork_in, ResponseMsg) {
 737       assert(is_valid(cache_entry));
 738       addSharer(address, in_msg.Sender, cache_entry);
 739     }
 740   }
 741
 742   action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
 743     peek(L1RequestL2Network_in, RequestMsg) {
 744       assert(is_valid(cache_entry));
 745       cache_entry.Sharers.remove(in_msg.Requestor);
 746     }
 747   }
 748
 749   action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
 750     peek(L1RequestL2Network_in, RequestMsg) {
 751       assert(is_valid(cache_entry));
 752       cache_entry.Sharers.clear();
 753     }
 754   }
 755
 756   action(mm_markExclusive, "\m", desc="set the exclusive owner") {
 757     peek(L1RequestL2Network_in, RequestMsg) {
 758       assert(is_valid(cache_entry));
 759       cache_entry.Sharers.clear();
 760       cache_entry.Exclusive := in_msg.Requestor;
 761       addSharer(address, in_msg.Requestor, cache_entry);
 762     }
 763   }
 764
 765   action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
 766     peek(L1unblockNetwork_in, ResponseMsg) {
 767       assert(is_valid(cache_entry));
 768       cache_entry.Sharers.clear();
 769       cache_entry.Exclusive := in_msg.Sender;
 770       addSharer(address, in_msg.Sender, cache_entry);
 771     }
 772   }
 773
 774   action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
 775     stall_and_wait(L1RequestL2Network_in, address);
 776   }
 777
 778   action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
 779     responseL2Network_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
 780   }
 781
 782   action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
 783     wakeUpBuffers(address);
 784   }
 785
 786   //*****************************************************
 787   // TRANSITIONS
 788   //*****************************************************
 789
 790
 791   //===============================================
 792   // BASE STATE - I
 793
 794   // Transitions from I (Idle)
 795   transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
 796     t_sendWBAck;
 797     jj_popL1RequestQueue;
 798   }
 799
 800   transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
 801     t_sendWBAck;
 802     jj_popL1RequestQueue;
 803   }
 804
 805   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
 806     zz_stallAndWaitL1RequestQueue;
 807   }
 808
 809   transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
 810     zn_recycleResponseNetwork;
 811   }
 812
 813   transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
 814     o_popIncomingResponseQueue;
 815   }
 816
 817
 818   transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
 819     zz_stallAndWaitL1RequestQueue;
 820   }
 821
 822
 823   transition(NP, L1_GETS,  ISS) {
 824     qq_allocateL2CacheBlock;
 825     ll_clearSharers;
 826     nn_addSharer;
 827     i_allocateTBE;
 828     ss_recordGetSL1ID;
 829     a_issueFetchToMemory;
 830     uu_profileMiss;
 831     jj_popL1RequestQueue;
 832   }
 833
 834   transition(NP, L1_GET_INSTR, IS) {
 835     qq_allocateL2CacheBlock;
 836     ll_clearSharers;
 837     nn_addSharer;
 838     i_allocateTBE;
 839     ss_recordGetSL1ID;
 840     a_issueFetchToMemory;
 841     uu_profileMiss;
 842     jj_popL1RequestQueue;
 843   }
 844
 845   transition(NP, L1_GETX, IM) {
 846     qq_allocateL2CacheBlock;
 847     ll_clearSharers;
 848     // nn_addSharer;
 849     i_allocateTBE;
 850     xx_recordGetXL1ID;
 851     a_issueFetchToMemory;
 852     uu_profileMiss;
 853     jj_popL1RequestQueue;
 854   }
 855
 856
 857   // transitions from IS/IM
 858
 859   transition(ISS, Mem_Data, MT_MB) {
 860     m_writeDataToCache;
 861     ex_sendExclusiveDataToGetSRequestors;
 862     s_deallocateTBE;
 863     o_popIncomingResponseQueue;
 864   }
 865
 866   transition(IS, Mem_Data, SS) {
 867     m_writeDataToCache;
 868     e_sendDataToGetSRequestors;
 869     s_deallocateTBE;
 870     o_popIncomingResponseQueue;
 871     kd_wakeUpDependents;
 872   }
 873
 874   transition(IM, Mem_Data, MT_MB) {
 875     m_writeDataToCache;
 876     ee_sendDataToGetXRequestor;
 877     s_deallocateTBE;
 878     o_popIncomingResponseQueue;
 879   }
 880
 881   transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
 882     nn_addSharer;
 883     ss_recordGetSL1ID;
 884     uu_profileMiss;
 885     jj_popL1RequestQueue;
 886   }
 887
 888   transition({IS, ISS}, L1_GETX) {
 889     zz_stallAndWaitL1RequestQueue;
 890   }
 891
 892   transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
 893     zz_stallAndWaitL1RequestQueue;
 894   }
 895
 896   // transitions from SS
 897   transition(SS, {L1_GETS, L1_GET_INSTR}) {
 898     ds_sendSharedDataToRequestor;
 899     nn_addSharer;
 900     set_setMRU;
 901     uu_profileHit;
 902     jj_popL1RequestQueue;
 903   }
 904
 905
 906   transition(SS, L1_GETX, SS_MB) {
 907     d_sendDataToRequestor;
 908     // fw_sendFwdInvToSharers;
 909     fwm_sendFwdInvToSharersMinusRequestor;
 910     set_setMRU;
 911     uu_profileHit;
 912     jj_popL1RequestQueue;
 913   }
 914
 915   transition(SS, L1_UPGRADE, SS_MB) {
 916     fwm_sendFwdInvToSharersMinusRequestor;
 917     ts_sendInvAckToUpgrader;
 918     set_setMRU;
 919     uu_profileHit;
 920     jj_popL1RequestQueue;
 921   }
 922
 923   transition(SS, L2_Replacement_clean, I_I) {
 924     i_allocateTBE;
 925     f_sendInvToSharers;
 926     rr_deallocateL2CacheBlock;
 927   }
 928
 929   transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
 930     i_allocateTBE;
 931     f_sendInvToSharers;
 932     rr_deallocateL2CacheBlock;
 933   }
 934
 935
 936   transition(M, L1_GETX, MT_MB) {
 937     d_sendDataToRequestor;
 938     set_setMRU;
 939     uu_profileHit;
 940     jj_popL1RequestQueue;
 941   }
 942
 943   transition(M, L1_GET_INSTR, SS) {
 944     d_sendDataToRequestor;
 945     nn_addSharer;
 946     set_setMRU;
 947     uu_profileHit;
 948     jj_popL1RequestQueue;
 949   }
 950
 951   transition(M, L1_GETS, MT_MB) {
 952     dd_sendExclusiveDataToRequestor;
 953     set_setMRU;
 954     uu_profileHit;
 955     jj_popL1RequestQueue;
 956   }
 957
 958   transition(M, {L2_Replacement, MEM_Inv}, M_I) {
 959     i_allocateTBE;
 960     c_exclusiveReplacement;
 961     rr_deallocateL2CacheBlock;
 962   }
 963
 964   transition(M, L2_Replacement_clean, M_I) {
 965     i_allocateTBE;
 966     c_exclusiveCleanReplacement;
 967     rr_deallocateL2CacheBlock;
 968   }
 969
 970
 971   // transitions from MT
 972
 973   transition(MT, L1_GETX, MT_MB) {
 974     b_forwardRequestToExclusive;
 975     uu_profileMiss;
 976     set_setMRU;
 977     jj_popL1RequestQueue;
 978   }
 979
 980
 981   transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
 982     b_forwardRequestToExclusive;
 983     uu_profileMiss;
 984     set_setMRU;
 985     jj_popL1RequestQueue;
 986   }
 987
 988   transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
 989     i_allocateTBE;
 990     f_sendInvToSharers;
 991     rr_deallocateL2CacheBlock;
 992   }
 993
 994   transition(MT, L2_Replacement_clean, MCT_I) {
 995     i_allocateTBE;
 996     f_sendInvToSharers;
 997     rr_deallocateL2CacheBlock;
 998   }
 999
1000   transition(MT, L1_PUTX, M) {
1001     ll_clearSharers;
1002     mr_writeDataToCacheFromRequest;
1003     t_sendWBAck;
1004     jj_popL1RequestQueue;
1005   }
1006
1007   transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
1008     // update actual directory
1009     mmu_markExclusiveFromUnblock;
1010     k_popUnblockQueue;
1011     kd_wakeUpDependents;
1012   }
1013
1014   transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
1015     zz_stallAndWaitL1RequestQueue;
1016   }
1017
1018   transition(MT_IIB, Unblock, MT_IB) {
1019     nnu_addSharerFromUnblock;
1020     k_popUnblockQueue;
1021   }
1022
1023   transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
1024     m_writeDataToCache;
1025     o_popIncomingResponseQueue;
1026   }
1027
1028   transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
1029     m_writeDataToCache;
1030     o_popIncomingResponseQueue;
1031     kd_wakeUpDependents;
1032   }
1033
1034   transition(MT_SB, Unblock, SS) {
1035     nnu_addSharerFromUnblock;
1036     k_popUnblockQueue;
1037     kd_wakeUpDependents;
1038   }
1039
1040   // writeback states
1041   transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
1042     zz_stallAndWaitL1RequestQueue;
1043   }
1044
1045   transition(I_I, Ack) {
1046     q_updateAck;
1047     o_popIncomingResponseQueue;
1048   }
1049
1050   transition(I_I, Ack_all, M_I) {
1051     c_exclusiveCleanReplacement;
1052     o_popIncomingResponseQueue;
1053   }
1054
1055   transition({MT_I, MCT_I}, WB_Data, M_I) {
1056     qq_writeDataToTBE;
1057     ct_exclusiveReplacementFromTBE;
1058     o_popIncomingResponseQueue;
1059   }
1060
1061   transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
1062     c_exclusiveCleanReplacement;
1063     o_popIncomingResponseQueue;
1064   }
1065
1066   transition(MCT_I,  {L1_PUTX, L1_PUTX_old}){
1067     zz_stallAndWaitL1RequestQueue;
1068   }
1069
1070   // L1 never changed Dirty data
1071   transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
1072     ct_exclusiveReplacementFromTBE;
1073     o_popIncomingResponseQueue;
1074   }
1075
1076   transition(MT_I, {L1_PUTX, L1_PUTX_old}){
1077     zz_stallAndWaitL1RequestQueue;
1078   }
1079
1080   // possible race between unblock and immediate replacement
1081   transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
1082     zz_stallAndWaitL1RequestQueue;
1083   }
1084
1085   transition(S_I, Ack) {
1086     q_updateAck;
1087     o_popIncomingResponseQueue;
1088   }
1089
1090   transition(S_I, Ack_all, M_I) {
1091     ct_exclusiveReplacementFromTBE;
1092     o_popIncomingResponseQueue;
1093   }
1094
1095   transition(M_I, Mem_Ack, NP) {
1096     s_deallocateTBE;
1097     o_popIncomingResponseQueue;
1098     kd_wakeUpDependents;
1099   }
1100 }