2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
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30 machine(MachineType:DMA, "DMA Controller")
31 : DMASequencer * dma_sequencer;
32 Cycles request_latency := 6;
34 MessageBuffer * responseFromDir, network="From", virtual_network="1",
36 MessageBuffer * requestToDir, network="To", virtual_network="0",
38 MessageBuffer * mandatoryQueue;
40 state_declaration(State, desc="DMA states", default="DMA_State_READY") {
41 READY, AccessPermission:Invalid, desc="Ready to accept a new request";
42 BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
43 BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
46 enumeration(Event, desc="DMA events") {
47 ReadRequest, desc="A new read request";
48 WriteRequest, desc="A new write request";
49 Data, desc="Data from a DMA memory read";
50 Ack, desc="DMA write to memory completed";
53 structure(TBE, desc="...") {
54 State TBEState, desc="Transient state";
55 DataBlock DataBlk, desc="Data";
58 structure(TBETable, external = "yes") {
61 void deallocate(Addr);
67 void wakeUpAllBuffers();
69 TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
72 MachineID mapAddressToMachine(Addr addr, MachineType mtype);
74 State getState(TBE tbe, Addr addr) {
82 void setState(TBE tbe, Addr addr, State state) {
84 tbe.TBEState := state;
88 AccessPermission getAccessPermission(Addr addr) {
89 return AccessPermission:NotPresent;
92 void setAccessPermission(Addr addr, State state) {
95 void functionalRead(Addr addr, Packet *pkt) {
96 error("DMA does not support functional read.");
99 int functionalWrite(Addr addr, Packet *pkt) {
100 error("DMA does not support functional write.");
103 out_port(requestToDir_out, RequestMsg, requestToDir, desc="...");
105 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
106 if (dmaRequestQueue_in.isReady(clockEdge())) {
107 peek(dmaRequestQueue_in, SequencerMsg) {
108 if (in_msg.Type == SequencerRequestType:LD ) {
109 trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
110 } else if (in_msg.Type == SequencerRequestType:ST) {
111 trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
113 error("Invalid request type");
119 in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
120 if (dmaResponseQueue_in.isReady(clockEdge())) {
121 peek( dmaResponseQueue_in, ResponseMsg) {
122 if (in_msg.Type == CoherenceResponseType:ACK) {
123 trigger(Event:Ack, makeLineAddress(in_msg.addr),
124 TBEs[makeLineAddress(in_msg.addr)]);
125 } else if (in_msg.Type == CoherenceResponseType:DATA) {
126 trigger(Event:Data, makeLineAddress(in_msg.addr),
127 TBEs[makeLineAddress(in_msg.addr)]);
129 error("Invalid response type");
135 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
136 peek(dmaRequestQueue_in, SequencerMsg) {
137 enqueue(requestToDir_out, RequestMsg, request_latency) {
138 out_msg.addr := in_msg.PhysicalAddress;
139 out_msg.Type := CoherenceRequestType:DMA_READ;
140 out_msg.Requestor := machineID;
141 out_msg.DataBlk := in_msg.DataBlk;
142 out_msg.Len := in_msg.Len;
143 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
144 out_msg.MessageSize := MessageSizeType:Writeback_Control;
149 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
150 peek(dmaRequestQueue_in, SequencerMsg) {
151 enqueue(requestToDir_out, RequestMsg, request_latency) {
152 out_msg.addr := in_msg.PhysicalAddress;
153 out_msg.Type := CoherenceRequestType:DMA_WRITE;
154 out_msg.Requestor := machineID;
155 out_msg.DataBlk := in_msg.DataBlk;
156 out_msg.Len := in_msg.Len;
157 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
158 out_msg.MessageSize := MessageSizeType:Writeback_Control;
163 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
164 dma_sequencer.ackCallback(address);
167 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
168 dma_sequencer.dataCallback(tbe.DataBlk, address);
171 action(t_updateTBEData, "t", desc="Update TBE Data") {
172 assert(is_valid(tbe));
173 peek( dmaResponseQueue_in, ResponseMsg) {
174 tbe.DataBlk := in_msg.DataBlk;
178 action(v_allocateTBE, "v", desc="Allocate TBE entry") {
179 TBEs.allocate(address);
180 set_tbe(TBEs[address]);
183 action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
184 TBEs.deallocate(address);
188 action(p_popRequestQueue, "p", desc="Pop request queue") {
189 dmaRequestQueue_in.dequeue(clockEdge());
192 action(p_popResponseQueue, "\p", desc="Pop request queue") {
193 dmaResponseQueue_in.dequeue(clockEdge());
196 action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
197 stall_and_wait(dmaRequestQueue_in, address);
200 action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
204 transition(READY, ReadRequest, BUSY_RD) {
210 transition(READY, WriteRequest, BUSY_WR) {
216 transition(BUSY_RD, Data, READY) {
221 wkad_wakeUpAllDependents;
224 transition(BUSY_WR, Ack, READY) {
228 wkad_wakeUpAllDependents;
231 transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
232 zz_stallAndWaitRequestQueue;