src/mem/protocol/MESI_Two_Level-dma.sm

   1 /*
   2  * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 machine(DMA, "DMA Controller")
  31 : DMASequencer * dma_sequencer;
  32   Cycles request_latency := 6;
  33
  34   MessageBuffer * responseFromDir, network="From", virtual_network="1",
  35         ordered="true", vnet_type="response";
  36   MessageBuffer * requestToDir, network="To", virtual_network="0",
  37         ordered="false", vnet_type="request";
  38 {
  39   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  40     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  41     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  42     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  43   }
  44
  45   enumeration(Event, desc="DMA events") {
  46     ReadRequest,  desc="A new read request";
  47     WriteRequest, desc="A new write request";
  48     Data,         desc="Data from a DMA memory read";
  49     Ack,          desc="DMA write to memory completed";
  50   }
  51
  52   structure(DMASequencer, external="yes") {
  53     void ackCallback();
  54     void dataCallback(DataBlock);
  55   }
  56
  57   MessageBuffer mandatoryQueue, ordered="false";
  58   State cur_state;
  59
  60   State getState(Address addr) {
  61     return cur_state;
  62   }
  63   void setState(Address addr, State state) {
  64   cur_state := state;
  65   }
  66
  67   AccessPermission getAccessPermission(Address addr) {
  68     return AccessPermission:NotPresent;
  69   }
  70
  71   void setAccessPermission(Address addr, State state) {
  72   }
  73
  74   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
  75     error("DMA does not support get data block.");
  76   }
  77
  78   out_port(requestToDir_out, RequestMsg, requestToDir, desc="...");
  79
  80   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  81     if (dmaRequestQueue_in.isReady()) {
  82       peek(dmaRequestQueue_in, SequencerMsg) {
  83         if (in_msg.Type == SequencerRequestType:LD ) {
  84           trigger(Event:ReadRequest, in_msg.LineAddress);
  85         } else if (in_msg.Type == SequencerRequestType:ST) {
  86           trigger(Event:WriteRequest, in_msg.LineAddress);
  87         } else {
  88           error("Invalid request type");
  89         }
  90       }
  91     }
  92   }
  93
  94   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
  95     if (dmaResponseQueue_in.isReady()) {
  96       peek( dmaResponseQueue_in, ResponseMsg) {
  97         if (in_msg.Type == CoherenceResponseType:ACK) {
  98           trigger(Event:Ack, makeLineAddress(in_msg.Addr));
  99         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 100           trigger(Event:Data, makeLineAddress(in_msg.Addr));
 101         } else {
 102           error("Invalid response type");
 103         }
 104       }
 105     }
 106   }
 107
 108   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 109     peek(dmaRequestQueue_in, SequencerMsg) {
 110       enqueue(requestToDir_out, RequestMsg, request_latency) {
 111         out_msg.Addr := in_msg.PhysicalAddress;
 112         out_msg.Type := CoherenceRequestType:DMA_READ;
 113         out_msg.DataBlk := in_msg.DataBlk;
 114         out_msg.Len := in_msg.Len;
 115         out_msg.Destination.add(map_Address_to_Directory(address));
 116         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 117       }
 118     }
 119   }
 120
 121   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 122     peek(dmaRequestQueue_in, SequencerMsg) {
 123       enqueue(requestToDir_out, RequestMsg, request_latency) {
 124           out_msg.Addr := in_msg.PhysicalAddress;
 125           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 126           out_msg.DataBlk := in_msg.DataBlk;
 127           out_msg.Len := in_msg.Len;
 128           out_msg.Destination.add(map_Address_to_Directory(address));
 129           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 130         }
 131       }
 132   }
 133
 134   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 135     dma_sequencer.ackCallback();
 136   }
 137
 138   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
 139     peek (dmaResponseQueue_in, ResponseMsg) {
 140       dma_sequencer.dataCallback(in_msg.DataBlk);
 141     }
 142   }
 143
 144   action(p_popRequestQueue, "p", desc="Pop request queue") {
 145     dmaRequestQueue_in.dequeue();
 146   }
 147
 148   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 149     dmaResponseQueue_in.dequeue();
 150   }
 151
 152   transition(READY, ReadRequest, BUSY_RD) {
 153     s_sendReadRequest;
 154     p_popRequestQueue;
 155   }
 156
 157   transition(READY, WriteRequest, BUSY_WR) {
 158     s_sendWriteRequest;
 159     p_popRequestQueue;
 160   }
 161
 162   transition(BUSY_RD, Data, READY) {
 163     d_dataCallback;
 164     p_popResponseQueue;
 165   }
 166
 167   transition(BUSY_WR, Ack, READY) {
 168     a_ackCallback;
 169     p_popResponseQueue;
 170   }
 171 }