src/mem/protocol/MI_example-cache.sm

   1
   2 machine(L1Cache, "MI Example L1 Cache")
   3 : Sequencer * sequencer,
   4   CacheMemory * cacheMemory,
   5   int cache_response_latency = 12,
   6   int issue_latency = 2
   7 {
   8
   9   // NETWORK BUFFERS
  10   MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true";
  11   MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true";
  12
  13   MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true";
  14   MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true";
  15
  16   // STATES
  17   state_declaration(State, desc="Cache states") {
  18     I, AccessPermission:Invalid, desc="Not Present/Invalid";
  19     II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
  20     M, AccessPermission:Read_Write, desc="Modified";
  21     MI, AccessPermission:Busy, desc="Modified, issued PUT";
  22     MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
  23
  24     IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
  25     IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
  26   }
  27
  28   // EVENTS
  29   enumeration(Event, desc="Cache events") {
  30     // From processor
  31
  32     Load,       desc="Load request from processor";
  33     Ifetch,     desc="Ifetch request from processor";
  34     Store,      desc="Store request from processor";
  35
  36     Data,       desc="Data from network";
  37     Fwd_GETX,        desc="Forward from network";
  38
  39     Inv,        desc="Invalidate request from dir";
  40
  41     Replacement,  desc="Replace a block";
  42     Writeback_Ack,   desc="Ack from the directory for a writeback";
  43     Writeback_Nack,   desc="Nack from the directory for a writeback";
  44   }
  45
  46   // STRUCTURE DEFINITIONS
  47
  48   MessageBuffer mandatoryQueue, ordered="false";
  49
  50   // CacheEntry
  51   structure(Entry, desc="...", interface="AbstractCacheEntry") {
  52     State CacheState,        desc="cache state";
  53     bool Dirty,              desc="Is the data dirty (different than memory)?";
  54     DataBlock DataBlk,       desc="Data in the block";
  55   }
  56
  57
  58   // TBE fields
  59   structure(TBE, desc="...") {
  60     State TBEState,          desc="Transient state";
  61     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
  62   }
  63
  64   external_type(TBETable) {
  65     TBE lookup(Address);
  66     void allocate(Address);
  67     void deallocate(Address);
  68     bool isPresent(Address);
  69   }
  70
  71
  72   // STRUCTURES
  73
  74   TBETable TBEs, template_hack="<L1Cache_TBE>";
  75
  76   // PROTOTYPES
  77   void set_cache_entry(AbstractCacheEntry a);
  78   void unset_cache_entry();
  79   void set_tbe(TBE b);
  80   void unset_tbe();
  81
  82   Entry getCacheEntry(Address address), return_by_pointer="yes" {
  83     return static_cast(Entry, "pointer", cacheMemory.lookup(address));
  84   }
  85
  86   // FUNCTIONS
  87   Event mandatory_request_type_to_event(CacheRequestType type) {
  88    if (type == CacheRequestType:LD) {
  89       return Event:Load;
  90     } else if (type == CacheRequestType:IFETCH) {
  91       return Event:Ifetch;
  92     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
  93       return Event:Store;
  94     } else {
  95       error("Invalid CacheRequestType");
  96     }
  97   }
  98
  99   State getState(TBE tbe, Entry cache_entry, Address addr) {
 100
 101     if (is_valid(tbe)) {
 102       return tbe.TBEState;
 103     }
 104     else if (is_valid(cache_entry)) {
 105       return cache_entry.CacheState;
 106     }
 107     else {
 108       return State:I;
 109     }
 110   }
 111
 112   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 113
 114     if (is_valid(tbe)) {
 115       tbe.TBEState := state;
 116     }
 117
 118     if (is_valid(cache_entry)) {
 119       cache_entry.CacheState := state;
 120     }
 121   }
 122
 123   GenericMachineType getNondirectHitMachType(MachineID sender) {
 124     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
 125       //
 126       // NOTE direct local hits should not call this
 127       //
 128       return GenericMachineType:L1Cache_wCC;
 129     } else {
 130       return ConvertMachToGenericMach(machineIDToMachineType(sender));
 131     }
 132   }
 133
 134
 135   // NETWORK PORTS
 136
 137   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 138   out_port(responseNetwork_out, ResponseMsg, responseFromCache);
 139
 140   in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
 141     if (forwardRequestNetwork_in.isReady()) {
 142       peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
 143
 144         Entry cache_entry := getCacheEntry(in_msg.Address);
 145         TBE tbe := TBEs[in_msg.Address];
 146
 147         if (in_msg.Type == CoherenceRequestType:GETX) {
 148           trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
 149         }
 150         else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 151           trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
 152         }
 153         else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 154           trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
 155         }
 156         else if (in_msg.Type == CoherenceRequestType:INV) {
 157           trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
 158         }
 159         else {
 160           error("Unexpected message");
 161         }
 162       }
 163     }
 164   }
 165
 166   in_port(responseNetwork_in, ResponseMsg, responseToCache) {
 167     if (responseNetwork_in.isReady()) {
 168       peek(responseNetwork_in, ResponseMsg, block_on="Address") {
 169
 170         Entry cache_entry := getCacheEntry(in_msg.Address);
 171         TBE tbe := TBEs[in_msg.Address];
 172
 173         if (in_msg.Type == CoherenceResponseType:DATA) {
 174           trigger(Event:Data, in_msg.Address, cache_entry, tbe);
 175         }
 176         else {
 177           error("Unexpected message");
 178         }
 179       }
 180     }
 181   }
 182
 183     // Mandatory Queue
 184   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 185     if (mandatoryQueue_in.isReady()) {
 186       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 187
 188         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
 189         if (is_invalid(cache_entry) &&
 190             cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
 191           // make room for the block
 192           trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
 193                   getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
 194                   TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
 195         }
 196         else {
 197           trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 198                   cache_entry, TBEs[in_msg.LineAddress]);
 199         }
 200       }
 201     }
 202   }
 203
 204   // ACTIONS
 205
 206   action(a_issueRequest, "a", desc="Issue a request") {
 207     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 208     out_msg.Address := address;
 209       out_msg.Type := CoherenceRequestType:GETX;
 210       out_msg.Requestor := machineID;
 211       out_msg.Destination.add(map_Address_to_Directory(address));
 212       out_msg.MessageSize := MessageSizeType:Control;
 213     }
 214   }
 215
 216   action(b_issuePUT, "b", desc="Issue a PUT request") {
 217     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
 218       assert(is_valid(cache_entry));
 219       out_msg.Address := address;
 220       out_msg.Type := CoherenceRequestType:PUTX;
 221       out_msg.Requestor := machineID;
 222       out_msg.Destination.add(map_Address_to_Directory(address));
 223       out_msg.DataBlk := cache_entry.DataBlk;
 224       out_msg.MessageSize := MessageSizeType:Data;
 225     }
 226   }
 227
 228
 229   action(e_sendData, "e", desc="Send data from cache to requestor") {
 230     peek(forwardRequestNetwork_in, RequestMsg) {
 231       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 232         assert(is_valid(cache_entry));
 233         out_msg.Address := address;
 234         out_msg.Type := CoherenceResponseType:DATA;
 235         out_msg.Sender := machineID;
 236         out_msg.Destination.add(in_msg.Requestor);
 237         out_msg.DataBlk := cache_entry.DataBlk;
 238         out_msg.MessageSize := MessageSizeType:Response_Data;
 239       }
 240     }
 241   }
 242
 243   action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
 244     peek(forwardRequestNetwork_in, RequestMsg) {
 245       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
 246         assert(is_valid(tbe));
 247         out_msg.Address := address;
 248         out_msg.Type := CoherenceResponseType:DATA;
 249         out_msg.Sender := machineID;
 250         out_msg.Destination.add(in_msg.Requestor);
 251         out_msg.DataBlk := tbe.DataBlk;
 252         out_msg.MessageSize := MessageSizeType:Response_Data;
 253       }
 254     }
 255   }
 256
 257   action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
 258     if (is_valid(cache_entry)) {
 259     } else {
 260       set_cache_entry(cacheMemory.allocate(address, new Entry));
 261     }
 262   }
 263
 264   action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
 265     if (is_valid(cache_entry)) {
 266       cacheMemory.deallocate(address);
 267       unset_cache_entry();
 268     }
 269   }
 270
 271   action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
 272     mandatoryQueue_in.dequeue();
 273   }
 274
 275   action(n_popResponseQueue, "n", desc="Pop the response queue") {
 276     profileMsgDelay(1, responseNetwork_in.dequeue_getDelayCycles());
 277   }
 278
 279   action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
 280     profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
 281   }
 282
 283   action(p_profileMiss, "p", desc="Profile cache miss") {
 284     peek(mandatoryQueue_in, CacheMsg) {
 285       cacheMemory.profileMiss(in_msg);
 286     }
 287   }
 288
 289   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
 290     assert(is_valid(cache_entry));
 291     DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 292     sequencer.readCallback(address,
 293                            GenericMachineType:L1Cache,
 294                            cache_entry.DataBlk);
 295   }
 296
 297   action(rx_load_hit, "rx", desc="External load completed.") {
 298     peek(responseNetwork_in, ResponseMsg) {
 299       assert(is_valid(cache_entry));
 300       DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 301       sequencer.readCallback(address,
 302                              getNondirectHitMachType(in_msg.Sender),
 303                              cache_entry.DataBlk);
 304     }
 305   }
 306
 307   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
 308     assert(is_valid(cache_entry));
 309     DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 310     sequencer.writeCallback(address,
 311                             GenericMachineType:L1Cache,
 312                             cache_entry.DataBlk);
 313   }
 314
 315   action(sx_store_hit, "sx", desc="External store completed.") {
 316     peek(responseNetwork_in, ResponseMsg) {
 317       assert(is_valid(cache_entry));
 318       DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 319       sequencer.writeCallback(address,
 320                               getNondirectHitMachType(in_msg.Sender),
 321                               cache_entry.DataBlk);
 322     }
 323   }
 324
 325   action(u_writeDataToCache, "u", desc="Write data to the cache") {
 326     peek(responseNetwork_in, ResponseMsg) {
 327       assert(is_valid(cache_entry));
 328       cache_entry.DataBlk := in_msg.DataBlk;
 329     }
 330   }
 331
 332
 333   action(v_allocateTBE, "v", desc="Allocate TBE") {
 334     TBEs.allocate(address);
 335     set_tbe(TBEs[address]);
 336   }
 337
 338
 339   action(w_deallocateTBE, "w", desc="Deallocate TBE") {
 340     TBEs.deallocate(address);
 341     unset_tbe();
 342   }
 343
 344   action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
 345     assert(is_valid(cache_entry));
 346     assert(is_valid(tbe));
 347     tbe.DataBlk := cache_entry.DataBlk;
 348   }
 349
 350   action(z_stall, "z", desc="stall") {
 351     // do nothing
 352   }
 353
 354   // TRANSITIONS
 355
 356   transition({IS, IM, MI, II}, {Load, Ifetch, Store, Replacement}) {
 357     z_stall;
 358   }
 359
 360   transition({IS, IM}, {Fwd_GETX, Inv}) {
 361     z_stall;
 362   }
 363
 364   transition(MI, Inv) {
 365     o_popForwardedRequestQueue;
 366   }
 367
 368   transition(M, Store) {
 369     s_store_hit;
 370     m_popMandatoryQueue;
 371   }
 372
 373   transition(M, {Load, Ifetch}) {
 374     r_load_hit;
 375     m_popMandatoryQueue;
 376   }
 377
 378   transition(I, Inv) {
 379     o_popForwardedRequestQueue;
 380   }
 381
 382   transition(I, Store, IM) {
 383     v_allocateTBE;
 384     i_allocateL1CacheBlock;
 385     a_issueRequest;
 386     p_profileMiss;
 387     m_popMandatoryQueue;
 388   }
 389
 390   transition(I, {Load, Ifetch}, IS) {
 391     v_allocateTBE;
 392     i_allocateL1CacheBlock;
 393     a_issueRequest;
 394     p_profileMiss;
 395     m_popMandatoryQueue;
 396   }
 397
 398   transition(IS, Data, M) {
 399     u_writeDataToCache;
 400     rx_load_hit;
 401     w_deallocateTBE;
 402     n_popResponseQueue;
 403   }
 404
 405   transition(IM, Data, M) {
 406     u_writeDataToCache;
 407     sx_store_hit;
 408     w_deallocateTBE;
 409     n_popResponseQueue;
 410   }
 411
 412   transition(M, Fwd_GETX, I) {
 413     e_sendData;
 414     o_popForwardedRequestQueue;
 415   }
 416
 417   transition(I, Replacement) {
 418      h_deallocateL1CacheBlock;
 419   }
 420
 421   transition(M, {Replacement,Inv},  MI) {
 422      v_allocateTBE;
 423      b_issuePUT;
 424      x_copyDataFromCacheToTBE;
 425      h_deallocateL1CacheBlock;
 426   }
 427
 428   transition(MI, Writeback_Ack, I) {
 429     w_deallocateTBE;
 430     o_popForwardedRequestQueue;
 431   }
 432
 433   transition(MI, Fwd_GETX, II) {
 434     ee_sendDataFromTBE;
 435     o_popForwardedRequestQueue;
 436   }
 437
 438   transition(MI, Writeback_Nack, MII) {
 439     o_popForwardedRequestQueue;
 440   }
 441
 442   transition(MII, Fwd_GETX, I) {
 443     ee_sendDataFromTBE;
 444     w_deallocateTBE;
 445     o_popForwardedRequestQueue;
 446   }
 447
 448   transition(II, Writeback_Nack, I) {
 449     w_deallocateTBE;
 450     o_popForwardedRequestQueue;
 451   }
 452 }
 453