2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
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30 machine(L1Cache, "MI Example L1 Cache")
31 : Sequencer * sequencer,
32 CacheMemory * cacheMemory,
33 Cycles cache_response_latency = 12,
34 Cycles issue_latency = 2,
39 MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true", vnet_type="request";
40 MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true", vnet_type="response";
42 MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true", vnet_type="forward";
43 MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true", vnet_type="response";
46 state_declaration(State, desc="Cache states") {
47 I, AccessPermission:Invalid, desc="Not Present/Invalid";
48 II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
49 M, AccessPermission:Read_Write, desc="Modified";
50 MI, AccessPermission:Busy, desc="Modified, issued PUT";
51 MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
53 IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
54 IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
58 enumeration(Event, desc="Cache events") {
61 Load, desc="Load request from processor";
62 Ifetch, desc="Ifetch request from processor";
63 Store, desc="Store request from processor";
65 Data, desc="Data from network";
66 Fwd_GETX, desc="Forward from network";
68 Inv, desc="Invalidate request from dir";
70 Replacement, desc="Replace a block";
71 Writeback_Ack, desc="Ack from the directory for a writeback";
72 Writeback_Nack, desc="Nack from the directory for a writeback";
75 // STRUCTURE DEFINITIONS
77 MessageBuffer mandatoryQueue, ordered="false";
80 structure(Entry, desc="...", interface="AbstractCacheEntry") {
81 State CacheState, desc="cache state";
82 bool Dirty, desc="Is the data dirty (different than memory)?";
83 DataBlock DataBlk, desc="Data in the block";
87 structure(TBE, desc="...") {
88 State TBEState, desc="Transient state";
89 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
92 structure(TBETable, external="yes") {
94 void allocate(Address);
95 void deallocate(Address);
96 bool isPresent(Address);
101 TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
104 void set_cache_entry(AbstractCacheEntry a);
105 void unset_cache_entry();
109 Entry getCacheEntry(Address address), return_by_pointer="yes" {
110 return static_cast(Entry, "pointer", cacheMemory.lookup(address));
114 Event mandatory_request_type_to_event(RubyRequestType type) {
115 if (type == RubyRequestType:LD) {
117 } else if (type == RubyRequestType:IFETCH) {
119 } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
122 error("Invalid RubyRequestType");
126 State getState(TBE tbe, Entry cache_entry, Address addr) {
131 else if (is_valid(cache_entry)) {
132 return cache_entry.CacheState;
139 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
142 tbe.TBEState := state;
145 if (is_valid(cache_entry)) {
146 cache_entry.CacheState := state;
150 AccessPermission getAccessPermission(Address addr) {
151 TBE tbe := TBEs[addr];
153 return L1Cache_State_to_permission(tbe.TBEState);
156 Entry cache_entry := getCacheEntry(addr);
157 if(is_valid(cache_entry)) {
158 return L1Cache_State_to_permission(cache_entry.CacheState);
161 return AccessPermission:NotPresent;
164 void setAccessPermission(Entry cache_entry, Address addr, State state) {
165 if (is_valid(cache_entry)) {
166 cache_entry.changePermission(L1Cache_State_to_permission(state));
170 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
171 TBE tbe := TBEs[addr];
176 return getCacheEntry(addr).DataBlk;
179 GenericMachineType getNondirectHitMachType(MachineID sender) {
180 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
182 // NOTE direct local hits should not call this
184 return GenericMachineType:L1Cache_wCC;
186 return ConvertMachToGenericMach(machineIDToMachineType(sender));
193 out_port(requestNetwork_out, RequestMsg, requestFromCache);
194 out_port(responseNetwork_out, ResponseMsg, responseFromCache);
196 in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
197 if (forwardRequestNetwork_in.isReady()) {
198 peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
200 Entry cache_entry := getCacheEntry(in_msg.Address);
201 TBE tbe := TBEs[in_msg.Address];
203 if (in_msg.Type == CoherenceRequestType:GETX) {
204 trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
206 else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
207 trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
209 else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
210 trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
212 else if (in_msg.Type == CoherenceRequestType:INV) {
213 trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
216 error("Unexpected message");
222 in_port(responseNetwork_in, ResponseMsg, responseToCache) {
223 if (responseNetwork_in.isReady()) {
224 peek(responseNetwork_in, ResponseMsg, block_on="Address") {
226 Entry cache_entry := getCacheEntry(in_msg.Address);
227 TBE tbe := TBEs[in_msg.Address];
229 if (in_msg.Type == CoherenceResponseType:DATA) {
230 trigger(Event:Data, in_msg.Address, cache_entry, tbe);
233 error("Unexpected message");
240 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
241 if (mandatoryQueue_in.isReady()) {
242 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
244 Entry cache_entry := getCacheEntry(in_msg.LineAddress);
245 if (is_invalid(cache_entry) &&
246 cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
247 // make room for the block
248 trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
249 getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
250 TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
253 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
254 cache_entry, TBEs[in_msg.LineAddress]);
262 action(a_issueRequest, "a", desc="Issue a request") {
263 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
264 out_msg.Address := address;
265 out_msg.Type := CoherenceRequestType:GETX;
266 out_msg.Requestor := machineID;
267 out_msg.Destination.add(map_Address_to_Directory(address));
268 out_msg.MessageSize := MessageSizeType:Control;
272 action(b_issuePUT, "b", desc="Issue a PUT request") {
273 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
274 assert(is_valid(cache_entry));
275 out_msg.Address := address;
276 out_msg.Type := CoherenceRequestType:PUTX;
277 out_msg.Requestor := machineID;
278 out_msg.Destination.add(map_Address_to_Directory(address));
279 out_msg.DataBlk := cache_entry.DataBlk;
280 out_msg.MessageSize := MessageSizeType:Data;
284 action(e_sendData, "e", desc="Send data from cache to requestor") {
285 peek(forwardRequestNetwork_in, RequestMsg) {
286 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
287 assert(is_valid(cache_entry));
288 out_msg.Address := address;
289 out_msg.Type := CoherenceResponseType:DATA;
290 out_msg.Sender := machineID;
291 out_msg.Destination.add(in_msg.Requestor);
292 out_msg.DataBlk := cache_entry.DataBlk;
293 out_msg.MessageSize := MessageSizeType:Response_Data;
298 action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
299 peek(forwardRequestNetwork_in, RequestMsg) {
300 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
301 assert(is_valid(tbe));
302 out_msg.Address := address;
303 out_msg.Type := CoherenceResponseType:DATA;
304 out_msg.Sender := machineID;
305 out_msg.Destination.add(in_msg.Requestor);
306 out_msg.DataBlk := tbe.DataBlk;
307 out_msg.MessageSize := MessageSizeType:Response_Data;
312 action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
313 if (is_valid(cache_entry)) {
315 set_cache_entry(cacheMemory.allocate(address, new Entry));
319 action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
320 if (is_valid(cache_entry)) {
321 cacheMemory.deallocate(address);
326 action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
327 mandatoryQueue_in.dequeue();
330 action(n_popResponseQueue, "n", desc="Pop the response queue") {
331 profileMsgDelay(1, responseNetwork_in.dequeue_getDelayCycles());
334 action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
335 profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
338 action(p_profileMiss, "p", desc="Profile cache miss") {
339 peek(mandatoryQueue_in, RubyRequest) {
340 cacheMemory.profileMiss(in_msg);
344 action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
345 assert(is_valid(cache_entry));
346 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
347 sequencer.readCallback(address,
348 GenericMachineType:L1Cache,
349 cache_entry.DataBlk);
352 action(rx_load_hit, "rx", desc="External load completed.") {
353 peek(responseNetwork_in, ResponseMsg) {
354 assert(is_valid(cache_entry));
355 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
356 sequencer.readCallback(address,
357 getNondirectHitMachType(in_msg.Sender),
358 cache_entry.DataBlk);
362 action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
363 assert(is_valid(cache_entry));
364 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
365 sequencer.writeCallback(address,
366 GenericMachineType:L1Cache,
367 cache_entry.DataBlk);
370 action(sx_store_hit, "sx", desc="External store completed.") {
371 peek(responseNetwork_in, ResponseMsg) {
372 assert(is_valid(cache_entry));
373 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
374 sequencer.writeCallback(address,
375 getNondirectHitMachType(in_msg.Sender),
376 cache_entry.DataBlk);
380 action(u_writeDataToCache, "u", desc="Write data to the cache") {
381 peek(responseNetwork_in, ResponseMsg) {
382 assert(is_valid(cache_entry));
383 cache_entry.DataBlk := in_msg.DataBlk;
387 action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
388 if (send_evictions) {
389 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
390 sequencer.evictionCallback(address);
394 action(v_allocateTBE, "v", desc="Allocate TBE") {
395 TBEs.allocate(address);
396 set_tbe(TBEs[address]);
399 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
400 TBEs.deallocate(address);
404 action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
405 assert(is_valid(cache_entry));
406 assert(is_valid(tbe));
407 tbe.DataBlk := cache_entry.DataBlk;
410 action(z_stall, "z", desc="stall") {
416 transition({IS, IM, MI, II}, {Load, Ifetch, Store, Replacement}) {
420 transition({IS, IM}, {Fwd_GETX, Inv}) {
424 transition(MI, Inv) {
425 o_popForwardedRequestQueue;
428 transition(M, Store) {
433 transition(M, {Load, Ifetch}) {
439 o_popForwardedRequestQueue;
442 transition(I, Store, IM) {
444 i_allocateL1CacheBlock;
450 transition(I, {Load, Ifetch}, IS) {
452 i_allocateL1CacheBlock;
458 transition(IS, Data, M) {
465 transition(IM, Data, M) {
472 transition(M, Fwd_GETX, I) {
474 forward_eviction_to_cpu;
475 o_popForwardedRequestQueue;
478 transition(I, Replacement) {
479 h_deallocateL1CacheBlock;
482 transition(M, {Replacement,Inv}, MI) {
485 x_copyDataFromCacheToTBE;
486 forward_eviction_to_cpu;
487 h_deallocateL1CacheBlock;
490 transition(MI, Writeback_Ack, I) {
492 o_popForwardedRequestQueue;
495 transition(MI, Fwd_GETX, II) {
497 o_popForwardedRequestQueue;
500 transition(MI, Writeback_Nack, MII) {
501 o_popForwardedRequestQueue;
504 transition(MII, Fwd_GETX, I) {
507 o_popForwardedRequestQueue;
510 transition(II, Writeback_Nack, I) {
512 o_popForwardedRequestQueue;