2 machine(L1Cache, "MI Example L1 Cache")
3 : Sequencer * sequencer,
4 CacheMemory * cacheMemory,
5 int cache_response_latency = 12,
10 MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true", vnet_type="request";
11 MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true", vnet_type="response";
13 MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true", vnet_type="forward";
14 MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true", vnet_type="response";
17 state_declaration(State, desc="Cache states") {
18 I, AccessPermission:Invalid, desc="Not Present/Invalid";
19 II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
20 M, AccessPermission:Read_Write, desc="Modified";
21 MI, AccessPermission:Busy, desc="Modified, issued PUT";
22 MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
24 IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
25 IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
29 enumeration(Event, desc="Cache events") {
32 Load, desc="Load request from processor";
33 Ifetch, desc="Ifetch request from processor";
34 Store, desc="Store request from processor";
36 Data, desc="Data from network";
37 Fwd_GETX, desc="Forward from network";
39 Inv, desc="Invalidate request from dir";
41 Replacement, desc="Replace a block";
42 Writeback_Ack, desc="Ack from the directory for a writeback";
43 Writeback_Nack, desc="Nack from the directory for a writeback";
46 // STRUCTURE DEFINITIONS
48 MessageBuffer mandatoryQueue, ordered="false";
51 structure(Entry, desc="...", interface="AbstractCacheEntry") {
52 State CacheState, desc="cache state";
53 bool Dirty, desc="Is the data dirty (different than memory)?";
54 DataBlock DataBlk, desc="Data in the block";
59 structure(TBE, desc="...") {
60 State TBEState, desc="Transient state";
61 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
64 structure(TBETable, external="yes") {
66 void allocate(Address);
67 void deallocate(Address);
68 bool isPresent(Address);
74 TBETable TBEs, template_hack="<L1Cache_TBE>";
77 void set_cache_entry(AbstractCacheEntry a);
78 void unset_cache_entry();
82 Entry getCacheEntry(Address address), return_by_pointer="yes" {
83 return static_cast(Entry, "pointer", cacheMemory.lookup(address));
87 Event mandatory_request_type_to_event(RubyRequestType type) {
88 if (type == RubyRequestType:LD) {
90 } else if (type == RubyRequestType:IFETCH) {
92 } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
95 error("Invalid RubyRequestType");
99 State getState(TBE tbe, Entry cache_entry, Address addr) {
104 else if (is_valid(cache_entry)) {
105 return cache_entry.CacheState;
112 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
115 tbe.TBEState := state;
118 if (is_valid(cache_entry)) {
119 cache_entry.CacheState := state;
123 AccessPermission getAccessPermission(Address addr) {
124 TBE tbe := TBEs[addr];
126 return L1Cache_State_to_permission(tbe.TBEState);
129 Entry cache_entry := getCacheEntry(addr);
130 if(is_valid(cache_entry)) {
131 return L1Cache_State_to_permission(cache_entry.CacheState);
134 return AccessPermission:NotPresent;
137 void setAccessPermission(Entry cache_entry, Address addr, State state) {
138 if (is_valid(cache_entry)) {
139 cache_entry.changePermission(L1Cache_State_to_permission(state));
143 GenericMachineType getNondirectHitMachType(MachineID sender) {
144 if (machineIDToMachineType(sender) == MachineType:L1Cache) {
146 // NOTE direct local hits should not call this
148 return GenericMachineType:L1Cache_wCC;
150 return ConvertMachToGenericMach(machineIDToMachineType(sender));
157 out_port(requestNetwork_out, RequestMsg, requestFromCache);
158 out_port(responseNetwork_out, ResponseMsg, responseFromCache);
160 in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
161 if (forwardRequestNetwork_in.isReady()) {
162 peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
164 Entry cache_entry := getCacheEntry(in_msg.Address);
165 TBE tbe := TBEs[in_msg.Address];
167 if (in_msg.Type == CoherenceRequestType:GETX) {
168 trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
170 else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
171 trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
173 else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
174 trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
176 else if (in_msg.Type == CoherenceRequestType:INV) {
177 trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
180 error("Unexpected message");
186 in_port(responseNetwork_in, ResponseMsg, responseToCache) {
187 if (responseNetwork_in.isReady()) {
188 peek(responseNetwork_in, ResponseMsg, block_on="Address") {
190 Entry cache_entry := getCacheEntry(in_msg.Address);
191 TBE tbe := TBEs[in_msg.Address];
193 if (in_msg.Type == CoherenceResponseType:DATA) {
194 trigger(Event:Data, in_msg.Address, cache_entry, tbe);
197 error("Unexpected message");
204 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
205 if (mandatoryQueue_in.isReady()) {
206 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
208 Entry cache_entry := getCacheEntry(in_msg.LineAddress);
209 if (is_invalid(cache_entry) &&
210 cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
211 // make room for the block
212 trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
213 getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
214 TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
217 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
218 cache_entry, TBEs[in_msg.LineAddress]);
226 action(a_issueRequest, "a", desc="Issue a request") {
227 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
228 out_msg.Address := address;
229 out_msg.Type := CoherenceRequestType:GETX;
230 out_msg.Requestor := machineID;
231 out_msg.Destination.add(map_Address_to_Directory(address));
232 out_msg.MessageSize := MessageSizeType:Control;
236 action(b_issuePUT, "b", desc="Issue a PUT request") {
237 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
238 assert(is_valid(cache_entry));
239 out_msg.Address := address;
240 out_msg.Type := CoherenceRequestType:PUTX;
241 out_msg.Requestor := machineID;
242 out_msg.Destination.add(map_Address_to_Directory(address));
243 out_msg.DataBlk := cache_entry.DataBlk;
244 out_msg.MessageSize := MessageSizeType:Data;
249 action(e_sendData, "e", desc="Send data from cache to requestor") {
250 peek(forwardRequestNetwork_in, RequestMsg) {
251 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
252 assert(is_valid(cache_entry));
253 out_msg.Address := address;
254 out_msg.Type := CoherenceResponseType:DATA;
255 out_msg.Sender := machineID;
256 out_msg.Destination.add(in_msg.Requestor);
257 out_msg.DataBlk := cache_entry.DataBlk;
258 out_msg.MessageSize := MessageSizeType:Response_Data;
263 action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
264 peek(forwardRequestNetwork_in, RequestMsg) {
265 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
266 assert(is_valid(tbe));
267 out_msg.Address := address;
268 out_msg.Type := CoherenceResponseType:DATA;
269 out_msg.Sender := machineID;
270 out_msg.Destination.add(in_msg.Requestor);
271 out_msg.DataBlk := tbe.DataBlk;
272 out_msg.MessageSize := MessageSizeType:Response_Data;
277 action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
278 if (is_valid(cache_entry)) {
280 set_cache_entry(cacheMemory.allocate(address, new Entry));
284 action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
285 if (is_valid(cache_entry)) {
286 cacheMemory.deallocate(address);
291 action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
292 mandatoryQueue_in.dequeue();
295 action(n_popResponseQueue, "n", desc="Pop the response queue") {
296 profileMsgDelay(1, responseNetwork_in.dequeue_getDelayCycles());
299 action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
300 profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
303 action(p_profileMiss, "p", desc="Profile cache miss") {
304 peek(mandatoryQueue_in, RubyRequest) {
305 cacheMemory.profileMiss(in_msg);
309 action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
310 assert(is_valid(cache_entry));
311 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
312 sequencer.readCallback(address,
313 GenericMachineType:L1Cache,
314 cache_entry.DataBlk);
317 action(rx_load_hit, "rx", desc="External load completed.") {
318 peek(responseNetwork_in, ResponseMsg) {
319 assert(is_valid(cache_entry));
320 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
321 sequencer.readCallback(address,
322 getNondirectHitMachType(in_msg.Sender),
323 cache_entry.DataBlk);
327 action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
328 assert(is_valid(cache_entry));
329 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
330 sequencer.writeCallback(address,
331 GenericMachineType:L1Cache,
332 cache_entry.DataBlk);
335 action(sx_store_hit, "sx", desc="External store completed.") {
336 peek(responseNetwork_in, ResponseMsg) {
337 assert(is_valid(cache_entry));
338 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
339 sequencer.writeCallback(address,
340 getNondirectHitMachType(in_msg.Sender),
341 cache_entry.DataBlk);
345 action(u_writeDataToCache, "u", desc="Write data to the cache") {
346 peek(responseNetwork_in, ResponseMsg) {
347 assert(is_valid(cache_entry));
348 cache_entry.DataBlk := in_msg.DataBlk;
353 action(v_allocateTBE, "v", desc="Allocate TBE") {
354 TBEs.allocate(address);
355 set_tbe(TBEs[address]);
359 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
360 TBEs.deallocate(address);
364 action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
365 assert(is_valid(cache_entry));
366 assert(is_valid(tbe));
367 tbe.DataBlk := cache_entry.DataBlk;
370 action(z_stall, "z", desc="stall") {
376 transition({IS, IM, MI, II}, {Load, Ifetch, Store, Replacement}) {
380 transition({IS, IM}, {Fwd_GETX, Inv}) {
384 transition(MI, Inv) {
385 o_popForwardedRequestQueue;
388 transition(M, Store) {
393 transition(M, {Load, Ifetch}) {
399 o_popForwardedRequestQueue;
402 transition(I, Store, IM) {
404 i_allocateL1CacheBlock;
410 transition(I, {Load, Ifetch}, IS) {
412 i_allocateL1CacheBlock;
418 transition(IS, Data, M) {
425 transition(IM, Data, M) {
432 transition(M, Fwd_GETX, I) {
434 o_popForwardedRequestQueue;
437 transition(I, Replacement) {
438 h_deallocateL1CacheBlock;
441 transition(M, {Replacement,Inv}, MI) {
444 x_copyDataFromCacheToTBE;
445 h_deallocateL1CacheBlock;
448 transition(MI, Writeback_Ack, I) {
450 o_popForwardedRequestQueue;
453 transition(MI, Fwd_GETX, II) {
455 o_popForwardedRequestQueue;
458 transition(MI, Writeback_Nack, MII) {
459 o_popForwardedRequestQueue;
462 transition(MII, Fwd_GETX, I) {
465 o_popForwardedRequestQueue;
468 transition(II, Writeback_Nack, I) {
470 o_popForwardedRequestQueue;