src/mem/protocol/MI_example-cache.sm

   1 /*
   2  * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 machine(L1Cache, "MI Example L1 Cache")
  31     : Sequencer * sequencer;
  32       CacheMemory * cacheMemory;
  33       Cycles cache_response_latency := 12;
  34       Cycles issue_latency := 2;
  35       bool send_evictions;
  36
  37       // NETWORK BUFFERS
  38       MessageBuffer * requestFromCache, network="To", virtual_network="2",
  39             ordered="true", vnet_type="request";
  40       MessageBuffer * responseFromCache, network="To", virtual_network="4",
  41             ordered="true", vnet_type="response";
  42
  43       MessageBuffer * forwardToCache, network="From", virtual_network="3",
  44             ordered="true", vnet_type="forward";
  45       MessageBuffer * responseToCache, network="From", virtual_network="4",
  46             ordered="true", vnet_type="response";
  47 {
  48   // STATES
  49   state_declaration(State, desc="Cache states") {
  50     I, AccessPermission:Invalid, desc="Not Present/Invalid";
  51     II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
  52     M, AccessPermission:Read_Write, desc="Modified";
  53     MI, AccessPermission:Busy, desc="Modified, issued PUT";
  54     MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
  55
  56     IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
  57     IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
  58   }
  59
  60   // EVENTS
  61   enumeration(Event, desc="Cache events") {
  62     // From processor
  63
  64     Load,       desc="Load request from processor";
  65     Ifetch,     desc="Ifetch request from processor";
  66     Store,      desc="Store request from processor";
  67
  68     Data,       desc="Data from network";
  69     Fwd_GETX,        desc="Forward from network";
  70
  71     Inv,        desc="Invalidate request from dir";
  72
  73     Replacement,  desc="Replace a block";
  74     Writeback_Ack,   desc="Ack from the directory for a writeback";
  75     Writeback_Nack,   desc="Nack from the directory for a writeback";
  76   }
  77
  78   // STRUCTURE DEFINITIONS
  79
  80   MessageBuffer mandatoryQueue, ordered="false";
  81
  82   // CacheEntry
  83   structure(Entry, desc="...", interface="AbstractCacheEntry") {
  84     State CacheState,        desc="cache state";
  85     bool Dirty,              desc="Is the data dirty (different than memory)?";
  86     DataBlock DataBlk,       desc="Data in the block";
  87   }
  88
  89   // TBE fields
  90   structure(TBE, desc="...") {
  91     State TBEState,          desc="Transient state";
  92     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
  93   }
  94
  95   structure(TBETable, external="yes") {
  96     TBE lookup(Address);
  97     void allocate(Address);
  98     void deallocate(Address);
  99     bool isPresent(Address);
 100   }
 101
 102
 103   // STRUCTURES
 104   TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 105
 106   // PROTOTYPES
 107   void set_cache_entry(AbstractCacheEntry a);
 108   void unset_cache_entry();
 109   void set_tbe(TBE b);
 110   void unset_tbe();
 111   void profileMsgDelay(int virtualNetworkType, Cycles b);
 112
 113   Entry getCacheEntry(Address address), return_by_pointer="yes" {
 114     return static_cast(Entry, "pointer", cacheMemory.lookup(address));
 115   }
 116
 117   // FUNCTIONS
 118   Event mandatory_request_type_to_event(RubyRequestType type) {
 119    if (type == RubyRequestType:LD) {
 120       return Event:Load;
 121     } else if (type == RubyRequestType:IFETCH) {
 122       return Event:Ifetch;
 123     } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
 124       return Event:Store;
 125     } else {
 126       error("Invalid RubyRequestType");
 127     }
 128   }
 129
 130   State getState(TBE tbe, Entry cache_entry, Address addr) {
 131
 132     if (is_valid(tbe)) {
 133       return tbe.TBEState;
 134     }
 135     else if (is_valid(cache_entry)) {
 136       return cache_entry.CacheState;
 137     }
 138     else {
 139       return State:I;
 140     }
 141   }
 142
 143   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 144
 145     if (is_valid(tbe)) {
 146       tbe.TBEState := state;
 147     }
 148
 149     if (is_valid(cache_entry)) {
 150       cache_entry.CacheState := state;
 151     }
 152   }
 153
 154   AccessPermission getAccessPermission(Address addr) {
 155     TBE tbe := TBEs[addr];
 156     if(is_valid(tbe)) {
 157       return L1Cache_State_to_permission(tbe.TBEState);
 158     }
 159
 160     Entry cache_entry := getCacheEntry(addr);
 161     if(is_valid(cache_entry)) {
 162       return L1Cache_State_to_permission(cache_entry.CacheState);
 163     }
 164
 165     return AccessPermission:NotPresent;
 166   }
 167
 168   void setAccessPermission(Entry cache_entry, Address addr, State state) {
 169     if (is_valid(cache_entry)) {
 170       cache_entry.changePermission(L1Cache_State_to_permission(state));
 171     }
 172   }
 173
 174   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
 175     TBE tbe := TBEs[addr];
 176     if(is_valid(tbe)) {
 177       return tbe.DataBlk;
 178     }
 179
 180     return getCacheEntry(addr).DataBlk;
 181   }
 182
 183   // NETWORK PORTS
 184
 185   out_port(requestNetwork_out, RequestMsg, requestFromCache);
 186   out_port(responseNetwork_out, ResponseMsg, responseFromCache);
 187
 188   in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
 189     if (forwardRequestNetwork_in.isReady()) {
 190       peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") {
 191
 192         Entry cache_entry := getCacheEntry(in_msg.Addr);
 193         TBE tbe := TBEs[in_msg.Addr];
 194
 195         if (in_msg.Type == CoherenceRequestType:GETX) {
 196           trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
 197         }
 198         else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 199           trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
 200         }
 201         else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 202           trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
 203         }
 204         else if (in_msg.Type == CoherenceRequestType:INV) {
 205           trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
 206         }
 207         else {
 208           error("Unexpected message");
 209         }
 210       }
 211     }
 212   }
 213
 214   in_port(responseNetwork_in, ResponseMsg, responseToCache) {
 215     if (responseNetwork_in.isReady()) {
 216       peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
 217
 218         Entry cache_entry := getCacheEntry(in_msg.Addr);
 219         TBE tbe := TBEs[in_msg.Addr];
 220
 221         if (in_msg.Type == CoherenceResponseType:DATA) {
 222           trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
 223         }
 224         else {
 225           error("Unexpected message");
 226         }
 227       }
 228     }
 229   }
 230
 231     // Mandatory Queue
 232   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 233     if (mandatoryQueue_in.isReady()) {
 234       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 235
 236         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
 237         if (is_invalid(cache_entry) &&
 238             cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
 239           // make room for the block
 240           trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
 241                   getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
 242                   TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
 243         }
 244         else {
 245           trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
 246                   cache_entry, TBEs[in_msg.LineAddress]);
 247         }
 248       }
 249     }
 250   }
 251
 252   // ACTIONS
 253
 254   action(a_issueRequest, "a", desc="Issue a request") {
 255     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 256     out_msg.Addr := address;
 257       out_msg.Type := CoherenceRequestType:GETX;
 258       out_msg.Requestor := machineID;
 259       out_msg.Destination.add(map_Address_to_Directory(address));
 260       out_msg.MessageSize := MessageSizeType:Control;
 261     }
 262   }
 263
 264   action(b_issuePUT, "b", desc="Issue a PUT request") {
 265     enqueue(requestNetwork_out, RequestMsg, issue_latency) {
 266       assert(is_valid(cache_entry));
 267       out_msg.Addr := address;
 268       out_msg.Type := CoherenceRequestType:PUTX;
 269       out_msg.Requestor := machineID;
 270       out_msg.Destination.add(map_Address_to_Directory(address));
 271       out_msg.DataBlk := cache_entry.DataBlk;
 272       out_msg.MessageSize := MessageSizeType:Data;
 273     }
 274   }
 275
 276   action(e_sendData, "e", desc="Send data from cache to requestor") {
 277     peek(forwardRequestNetwork_in, RequestMsg) {
 278       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 279         assert(is_valid(cache_entry));
 280         out_msg.Addr := address;
 281         out_msg.Type := CoherenceResponseType:DATA;
 282         out_msg.Sender := machineID;
 283         out_msg.Destination.add(in_msg.Requestor);
 284         out_msg.DataBlk := cache_entry.DataBlk;
 285         out_msg.MessageSize := MessageSizeType:Response_Data;
 286       }
 287     }
 288   }
 289
 290   action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
 291     peek(forwardRequestNetwork_in, RequestMsg) {
 292       enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
 293         assert(is_valid(tbe));
 294         out_msg.Addr := address;
 295         out_msg.Type := CoherenceResponseType:DATA;
 296         out_msg.Sender := machineID;
 297         out_msg.Destination.add(in_msg.Requestor);
 298         out_msg.DataBlk := tbe.DataBlk;
 299         out_msg.MessageSize := MessageSizeType:Response_Data;
 300       }
 301     }
 302   }
 303
 304   action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
 305     if (is_valid(cache_entry)) {
 306     } else {
 307       set_cache_entry(cacheMemory.allocate(address, new Entry));
 308     }
 309   }
 310
 311   action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
 312     if (is_valid(cache_entry)) {
 313       cacheMemory.deallocate(address);
 314       unset_cache_entry();
 315     }
 316   }
 317
 318   action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
 319     mandatoryQueue_in.dequeue();
 320   }
 321
 322   action(n_popResponseQueue, "n", desc="Pop the response queue") {
 323     profileMsgDelay(1, responseNetwork_in.dequeue());
 324   }
 325
 326   action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
 327     profileMsgDelay(2, forwardRequestNetwork_in.dequeue());
 328   }
 329
 330   action(p_profileMiss, "pi", desc="Profile cache miss") {
 331       ++cacheMemory.demand_misses;
 332   }
 333
 334   action(p_profileHit, "ph", desc="Profile cache miss") {
 335       ++cacheMemory.demand_hits;
 336   }
 337
 338   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
 339     assert(is_valid(cache_entry));
 340     DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 341     sequencer.readCallback(address, cache_entry.DataBlk, false);
 342   }
 343
 344   action(rx_load_hit, "rx", desc="External load completed.") {
 345     peek(responseNetwork_in, ResponseMsg) {
 346       assert(is_valid(cache_entry));
 347       DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 348       sequencer.readCallback(address, cache_entry.DataBlk, true,
 349                              machineIDToMachineType(in_msg.Sender));
 350     }
 351   }
 352
 353   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
 354     assert(is_valid(cache_entry));
 355     DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 356     sequencer.writeCallback(address, cache_entry.DataBlk, false);
 357   }
 358
 359   action(sx_store_hit, "sx", desc="External store completed.") {
 360     peek(responseNetwork_in, ResponseMsg) {
 361       assert(is_valid(cache_entry));
 362       DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
 363       sequencer.writeCallback(address, cache_entry.DataBlk, true,
 364                               machineIDToMachineType(in_msg.Sender));
 365     }
 366   }
 367
 368   action(u_writeDataToCache, "u", desc="Write data to the cache") {
 369     peek(responseNetwork_in, ResponseMsg) {
 370       assert(is_valid(cache_entry));
 371       cache_entry.DataBlk := in_msg.DataBlk;
 372     }
 373   }
 374
 375   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
 376     if (send_evictions) {
 377       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
 378       sequencer.evictionCallback(address);
 379     }
 380   }
 381
 382   action(v_allocateTBE, "v", desc="Allocate TBE") {
 383     TBEs.allocate(address);
 384     set_tbe(TBEs[address]);
 385   }
 386
 387   action(w_deallocateTBE, "w", desc="Deallocate TBE") {
 388     TBEs.deallocate(address);
 389     unset_tbe();
 390   }
 391
 392   action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
 393     assert(is_valid(cache_entry));
 394     assert(is_valid(tbe));
 395     tbe.DataBlk := cache_entry.DataBlk;
 396   }
 397
 398   action(z_stall, "z", desc="stall") {
 399     // do nothing
 400   }
 401
 402   // TRANSITIONS
 403
 404   transition({IS, IM, MI, II, MII}, {Load, Ifetch, Store, Replacement}) {
 405     z_stall;
 406   }
 407
 408   transition({IS, IM}, {Fwd_GETX, Inv}) {
 409     z_stall;
 410   }
 411
 412   transition(MI, Inv) {
 413     o_popForwardedRequestQueue;
 414   }
 415
 416   transition(M, Store) {
 417     s_store_hit;
 418     p_profileHit;
 419     m_popMandatoryQueue;
 420   }
 421
 422   transition(M, {Load, Ifetch}) {
 423     r_load_hit;
 424     p_profileHit;
 425     m_popMandatoryQueue;
 426   }
 427
 428   transition(I, Inv) {
 429     o_popForwardedRequestQueue;
 430   }
 431
 432   transition(I, Store, IM) {
 433     v_allocateTBE;
 434     i_allocateL1CacheBlock;
 435     a_issueRequest;
 436     p_profileMiss;
 437     m_popMandatoryQueue;
 438   }
 439
 440   transition(I, {Load, Ifetch}, IS) {
 441     v_allocateTBE;
 442     i_allocateL1CacheBlock;
 443     a_issueRequest;
 444     p_profileMiss;
 445     m_popMandatoryQueue;
 446   }
 447
 448   transition(IS, Data, M) {
 449     u_writeDataToCache;
 450     rx_load_hit;
 451     w_deallocateTBE;
 452     n_popResponseQueue;
 453   }
 454
 455   transition(IM, Data, M) {
 456     u_writeDataToCache;
 457     sx_store_hit;
 458     w_deallocateTBE;
 459     n_popResponseQueue;
 460   }
 461
 462   transition(M, Fwd_GETX, I) {
 463     e_sendData;
 464     forward_eviction_to_cpu;
 465     o_popForwardedRequestQueue;
 466   }
 467
 468   transition(I, Replacement) {
 469      h_deallocateL1CacheBlock;
 470   }
 471
 472   transition(M, {Replacement,Inv},  MI) {
 473      v_allocateTBE;
 474      b_issuePUT;
 475      x_copyDataFromCacheToTBE;
 476      forward_eviction_to_cpu;
 477      h_deallocateL1CacheBlock;
 478   }
 479
 480   transition(MI, Writeback_Ack, I) {
 481     w_deallocateTBE;
 482     o_popForwardedRequestQueue;
 483   }
 484
 485   transition(MI, Fwd_GETX, II) {
 486     ee_sendDataFromTBE;
 487     o_popForwardedRequestQueue;
 488   }
 489
 490   transition(MI, Writeback_Nack, MII) {
 491     o_popForwardedRequestQueue;
 492   }
 493
 494   transition(MII, Fwd_GETX, I) {
 495     ee_sendDataFromTBE;
 496     w_deallocateTBE;
 497     o_popForwardedRequestQueue;
 498   }
 499
 500   transition(II, Writeback_Nack, I) {
 501     w_deallocateTBE;
 502     o_popForwardedRequestQueue;
 503   }
 504 }