2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
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30 machine(L1Cache, "MI Example L1 Cache")
31 : Sequencer * sequencer,
32 CacheMemory * cacheMemory,
33 Cycles cache_response_latency = 12,
34 Cycles issue_latency = 2,
39 MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true", vnet_type="request";
40 MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true", vnet_type="response";
42 MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true", vnet_type="forward";
43 MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true", vnet_type="response";
46 state_declaration(State, desc="Cache states") {
47 I, AccessPermission:Invalid, desc="Not Present/Invalid";
48 II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
49 M, AccessPermission:Read_Write, desc="Modified";
50 MI, AccessPermission:Busy, desc="Modified, issued PUT";
51 MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
53 IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
54 IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
58 enumeration(Event, desc="Cache events") {
61 Load, desc="Load request from processor";
62 Ifetch, desc="Ifetch request from processor";
63 Store, desc="Store request from processor";
65 Data, desc="Data from network";
66 Fwd_GETX, desc="Forward from network";
68 Inv, desc="Invalidate request from dir";
70 Replacement, desc="Replace a block";
71 Writeback_Ack, desc="Ack from the directory for a writeback";
72 Writeback_Nack, desc="Nack from the directory for a writeback";
75 // STRUCTURE DEFINITIONS
77 MessageBuffer mandatoryQueue, ordered="false";
80 structure(Entry, desc="...", interface="AbstractCacheEntry") {
81 State CacheState, desc="cache state";
82 bool Dirty, desc="Is the data dirty (different than memory)?";
83 DataBlock DataBlk, desc="Data in the block";
87 structure(TBE, desc="...") {
88 State TBEState, desc="Transient state";
89 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
92 structure(TBETable, external="yes") {
94 void allocate(Address);
95 void deallocate(Address);
96 bool isPresent(Address);
101 TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
104 void set_cache_entry(AbstractCacheEntry a);
105 void unset_cache_entry();
108 void profileMsgDelay(int virtualNetworkType, Cycles b);
110 Entry getCacheEntry(Address address), return_by_pointer="yes" {
111 return static_cast(Entry, "pointer", cacheMemory.lookup(address));
115 Event mandatory_request_type_to_event(RubyRequestType type) {
116 if (type == RubyRequestType:LD) {
118 } else if (type == RubyRequestType:IFETCH) {
120 } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
123 error("Invalid RubyRequestType");
127 State getState(TBE tbe, Entry cache_entry, Address addr) {
132 else if (is_valid(cache_entry)) {
133 return cache_entry.CacheState;
140 void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
143 tbe.TBEState := state;
146 if (is_valid(cache_entry)) {
147 cache_entry.CacheState := state;
151 AccessPermission getAccessPermission(Address addr) {
152 TBE tbe := TBEs[addr];
154 return L1Cache_State_to_permission(tbe.TBEState);
157 Entry cache_entry := getCacheEntry(addr);
158 if(is_valid(cache_entry)) {
159 return L1Cache_State_to_permission(cache_entry.CacheState);
162 return AccessPermission:NotPresent;
165 void setAccessPermission(Entry cache_entry, Address addr, State state) {
166 if (is_valid(cache_entry)) {
167 cache_entry.changePermission(L1Cache_State_to_permission(state));
171 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
172 TBE tbe := TBEs[addr];
177 return getCacheEntry(addr).DataBlk;
182 out_port(requestNetwork_out, RequestMsg, requestFromCache);
183 out_port(responseNetwork_out, ResponseMsg, responseFromCache);
185 in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
186 if (forwardRequestNetwork_in.isReady()) {
187 peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") {
189 Entry cache_entry := getCacheEntry(in_msg.Addr);
190 TBE tbe := TBEs[in_msg.Addr];
192 if (in_msg.Type == CoherenceRequestType:GETX) {
193 trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
195 else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
196 trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
198 else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
199 trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
201 else if (in_msg.Type == CoherenceRequestType:INV) {
202 trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
205 error("Unexpected message");
211 in_port(responseNetwork_in, ResponseMsg, responseToCache) {
212 if (responseNetwork_in.isReady()) {
213 peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
215 Entry cache_entry := getCacheEntry(in_msg.Addr);
216 TBE tbe := TBEs[in_msg.Addr];
218 if (in_msg.Type == CoherenceResponseType:DATA) {
219 trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
222 error("Unexpected message");
229 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
230 if (mandatoryQueue_in.isReady()) {
231 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
233 Entry cache_entry := getCacheEntry(in_msg.LineAddress);
234 if (is_invalid(cache_entry) &&
235 cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
236 // make room for the block
237 trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
238 getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
239 TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
242 trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
243 cache_entry, TBEs[in_msg.LineAddress]);
251 action(a_issueRequest, "a", desc="Issue a request") {
252 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
253 out_msg.Addr := address;
254 out_msg.Type := CoherenceRequestType:GETX;
255 out_msg.Requestor := machineID;
256 out_msg.Destination.add(map_Address_to_Directory(address));
257 out_msg.MessageSize := MessageSizeType:Control;
261 action(b_issuePUT, "b", desc="Issue a PUT request") {
262 enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
263 assert(is_valid(cache_entry));
264 out_msg.Addr := address;
265 out_msg.Type := CoherenceRequestType:PUTX;
266 out_msg.Requestor := machineID;
267 out_msg.Destination.add(map_Address_to_Directory(address));
268 out_msg.DataBlk := cache_entry.DataBlk;
269 out_msg.MessageSize := MessageSizeType:Data;
273 action(e_sendData, "e", desc="Send data from cache to requestor") {
274 peek(forwardRequestNetwork_in, RequestMsg) {
275 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
276 assert(is_valid(cache_entry));
277 out_msg.Addr := address;
278 out_msg.Type := CoherenceResponseType:DATA;
279 out_msg.Sender := machineID;
280 out_msg.Destination.add(in_msg.Requestor);
281 out_msg.DataBlk := cache_entry.DataBlk;
282 out_msg.MessageSize := MessageSizeType:Response_Data;
287 action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
288 peek(forwardRequestNetwork_in, RequestMsg) {
289 enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
290 assert(is_valid(tbe));
291 out_msg.Addr := address;
292 out_msg.Type := CoherenceResponseType:DATA;
293 out_msg.Sender := machineID;
294 out_msg.Destination.add(in_msg.Requestor);
295 out_msg.DataBlk := tbe.DataBlk;
296 out_msg.MessageSize := MessageSizeType:Response_Data;
301 action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
302 if (is_valid(cache_entry)) {
304 set_cache_entry(cacheMemory.allocate(address, new Entry));
308 action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
309 if (is_valid(cache_entry)) {
310 cacheMemory.deallocate(address);
315 action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
316 mandatoryQueue_in.dequeue();
319 action(n_popResponseQueue, "n", desc="Pop the response queue") {
320 profileMsgDelay(1, responseNetwork_in.dequeue_getDelayCycles());
323 action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
324 profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
327 action(p_profileMiss, "pi", desc="Profile cache miss") {
328 ++cacheMemory.demand_misses;
331 action(p_profileHit, "ph", desc="Profile cache miss") {
332 ++cacheMemory.demand_hits;
335 action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
336 assert(is_valid(cache_entry));
337 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
338 sequencer.readCallback(address, cache_entry.DataBlk, false);
341 action(rx_load_hit, "rx", desc="External load completed.") {
342 peek(responseNetwork_in, ResponseMsg) {
343 assert(is_valid(cache_entry));
344 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
345 sequencer.readCallback(address, cache_entry.DataBlk, true,
346 machineIDToMachineType(in_msg.Sender));
350 action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
351 assert(is_valid(cache_entry));
352 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
353 sequencer.writeCallback(address, cache_entry.DataBlk, false);
356 action(sx_store_hit, "sx", desc="External store completed.") {
357 peek(responseNetwork_in, ResponseMsg) {
358 assert(is_valid(cache_entry));
359 DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
360 sequencer.writeCallback(address, cache_entry.DataBlk, true,
361 machineIDToMachineType(in_msg.Sender));
365 action(u_writeDataToCache, "u", desc="Write data to the cache") {
366 peek(responseNetwork_in, ResponseMsg) {
367 assert(is_valid(cache_entry));
368 cache_entry.DataBlk := in_msg.DataBlk;
372 action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
373 if (send_evictions) {
374 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
375 sequencer.evictionCallback(address);
379 action(v_allocateTBE, "v", desc="Allocate TBE") {
380 TBEs.allocate(address);
381 set_tbe(TBEs[address]);
384 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
385 TBEs.deallocate(address);
389 action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
390 assert(is_valid(cache_entry));
391 assert(is_valid(tbe));
392 tbe.DataBlk := cache_entry.DataBlk;
395 action(z_stall, "z", desc="stall") {
401 transition({IS, IM, MI, II, MII}, {Load, Ifetch, Store, Replacement}) {
405 transition({IS, IM}, {Fwd_GETX, Inv}) {
409 transition(MI, Inv) {
410 o_popForwardedRequestQueue;
413 transition(M, Store) {
419 transition(M, {Load, Ifetch}) {
426 o_popForwardedRequestQueue;
429 transition(I, Store, IM) {
431 i_allocateL1CacheBlock;
437 transition(I, {Load, Ifetch}, IS) {
439 i_allocateL1CacheBlock;
445 transition(IS, Data, M) {
452 transition(IM, Data, M) {
459 transition(M, Fwd_GETX, I) {
461 forward_eviction_to_cpu;
462 o_popForwardedRequestQueue;
465 transition(I, Replacement) {
466 h_deallocateL1CacheBlock;
469 transition(M, {Replacement,Inv}, MI) {
472 x_copyDataFromCacheToTBE;
473 forward_eviction_to_cpu;
474 h_deallocateL1CacheBlock;
477 transition(MI, Writeback_Ack, I) {
479 o_popForwardedRequestQueue;
482 transition(MI, Fwd_GETX, II) {
484 o_popForwardedRequestQueue;
487 transition(MI, Writeback_Nack, MII) {
488 o_popForwardedRequestQueue;
491 transition(MII, Fwd_GETX, I) {
494 o_popForwardedRequestQueue;
497 transition(II, Writeback_Nack, I) {
499 o_popForwardedRequestQueue;