2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 machine(Directory, "Directory protocol")
31 : DirectoryMemory * directory;
32 Cycles directory_latency := 12;
33 Cycles to_memory_controller_latency := 1;
35 MessageBuffer * forwardFromDir, network="To", virtual_network="3",
37 MessageBuffer * responseFromDir, network="To", virtual_network="4",
39 MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
42 MessageBuffer * requestToDir, network="From", virtual_network="2",
44 MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
48 state_declaration(State, desc="Directory states", default="Directory_State_I") {
50 I, AccessPermission:Read_Write, desc="Invalid";
51 M, AccessPermission:Invalid, desc="Modified";
53 M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA read";
54 M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA write";
56 M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
57 M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
59 IM, AccessPermission:Busy, desc="Intermediate state I-->M";
60 MI, AccessPermission:Busy, desc="Intermediate state M-->I";
61 ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
62 ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
66 enumeration(Event, desc="Directory events") {
68 GETX, desc="A GETX arrives";
69 GETS, desc="A GETS arrives";
70 PUTX, desc="A PUTX arrives";
71 PUTX_NotOwner, desc="A PUTX arrives";
74 DMA_READ, desc="A DMA Read memory request";
75 DMA_WRITE, desc="A DMA Write memory request";
78 Memory_Data, desc="Fetched data from memory arrives";
79 Memory_Ack, desc="Writeback Ack from memory arrives";
85 structure(Entry, desc="...", interface="AbstractEntry") {
86 State DirectoryState, desc="Directory state";
87 NetDest Sharers, desc="Sharers for this block";
88 NetDest Owner, desc="Owner of this block";
91 // TBE entries for DMA requests
92 structure(TBE, desc="TBE entries for outstanding DMA requests") {
93 Addr PhysicalAddress, desc="physical address";
94 State TBEState, desc="Transient State";
95 DataBlock DataBlk, desc="Data to be written (DMA write only)";
97 MachineID DmaRequestor, desc="DMA requestor";
100 structure(TBETable, external="yes") {
103 void deallocate(Addr);
104 bool isPresent(Addr);
108 TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
113 Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
114 Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
116 if (is_valid(dir_entry)) {
120 dir_entry := static_cast(Entry, "pointer",
121 directory.allocate(addr, new Entry));
125 State getState(TBE tbe, Addr addr) {
128 } else if (directory.isPresent(addr)) {
129 return getDirectoryEntry(addr).DirectoryState;
135 void setState(TBE tbe, Addr addr, State state) {
138 tbe.TBEState := state;
141 if (directory.isPresent(addr)) {
143 if (state == State:M) {
144 assert(getDirectoryEntry(addr).Owner.count() == 1);
145 assert(getDirectoryEntry(addr).Sharers.count() == 0);
148 getDirectoryEntry(addr).DirectoryState := state;
150 if (state == State:I) {
151 assert(getDirectoryEntry(addr).Owner.count() == 0);
152 assert(getDirectoryEntry(addr).Sharers.count() == 0);
157 AccessPermission getAccessPermission(Addr addr) {
158 TBE tbe := TBEs[addr];
160 return Directory_State_to_permission(tbe.TBEState);
163 if(directory.isPresent(addr)) {
164 return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
167 return AccessPermission:NotPresent;
170 void setAccessPermission(Addr addr, State state) {
171 if (directory.isPresent(addr)) {
172 getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
176 void functionalRead(Addr addr, Packet *pkt) {
177 TBE tbe := TBEs[addr];
179 testAndRead(addr, tbe.DataBlk, pkt);
181 functionalMemoryRead(pkt);
185 int functionalWrite(Addr addr, Packet *pkt) {
186 int num_functional_writes := 0;
188 TBE tbe := TBEs[addr];
190 num_functional_writes := num_functional_writes +
191 testAndWrite(addr, tbe.DataBlk, pkt);
194 num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
195 return num_functional_writes;
198 MessageBuffer responseFromMemory;
201 out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
202 out_port(responseNetwork_out, ResponseMsg, responseFromDir);
203 out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
204 out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
207 in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
208 if (dmaRequestQueue_in.isReady()) {
209 peek(dmaRequestQueue_in, DMARequestMsg) {
210 TBE tbe := TBEs[in_msg.LineAddress];
211 if (in_msg.Type == DMARequestType:READ) {
212 trigger(Event:DMA_READ, in_msg.LineAddress, tbe);
213 } else if (in_msg.Type == DMARequestType:WRITE) {
214 trigger(Event:DMA_WRITE, in_msg.LineAddress, tbe);
216 error("Invalid message");
222 in_port(requestQueue_in, RequestMsg, requestToDir) {
223 if (requestQueue_in.isReady()) {
224 peek(requestQueue_in, RequestMsg) {
225 TBE tbe := TBEs[in_msg.addr];
226 if (in_msg.Type == CoherenceRequestType:GETS) {
227 trigger(Event:GETS, in_msg.addr, tbe);
228 } else if (in_msg.Type == CoherenceRequestType:GETX) {
229 trigger(Event:GETX, in_msg.addr, tbe);
230 } else if (in_msg.Type == CoherenceRequestType:PUTX) {
231 if (getDirectoryEntry(in_msg.addr).Owner.isElement(in_msg.Requestor)) {
232 trigger(Event:PUTX, in_msg.addr, tbe);
234 trigger(Event:PUTX_NotOwner, in_msg.addr, tbe);
237 error("Invalid message");
244 // off-chip memory request/response is done
245 in_port(memQueue_in, MemoryMsg, responseFromMemory) {
246 if (memQueue_in.isReady()) {
247 peek(memQueue_in, MemoryMsg) {
248 TBE tbe := TBEs[in_msg.addr];
249 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
250 trigger(Event:Memory_Data, in_msg.addr, tbe);
251 } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
252 trigger(Event:Memory_Ack, in_msg.addr, tbe);
254 DPRINTF(RubySlicc,"%s\n", in_msg.Type);
255 error("Invalid message");
263 action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
264 peek(requestQueue_in, RequestMsg) {
265 enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
266 out_msg.addr := address;
267 out_msg.Type := CoherenceRequestType:WB_ACK;
268 out_msg.Requestor := in_msg.Requestor;
269 out_msg.Destination.add(in_msg.Requestor);
270 out_msg.MessageSize := MessageSizeType:Writeback_Control;
275 action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
276 peek(memQueue_in, MemoryMsg) {
277 enqueue(forwardNetwork_out, RequestMsg, 1) {
278 out_msg.addr := address;
279 out_msg.Type := CoherenceRequestType:WB_ACK;
280 out_msg.Requestor := in_msg.OriginalRequestorMachId;
281 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
282 out_msg.MessageSize := MessageSizeType:Writeback_Control;
287 action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
288 peek(requestQueue_in, RequestMsg) {
289 enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
290 out_msg.addr := address;
291 out_msg.Type := CoherenceRequestType:WB_NACK;
292 out_msg.Requestor := in_msg.Requestor;
293 out_msg.Destination.add(in_msg.Requestor);
294 out_msg.MessageSize := MessageSizeType:Writeback_Control;
299 action(c_clearOwner, "c", desc="Clear the owner field") {
300 getDirectoryEntry(address).Owner.clear();
303 action(d_sendData, "d", desc="Send data to requestor") {
304 peek(memQueue_in, MemoryMsg) {
305 enqueue(responseNetwork_out, ResponseMsg, 1) {
306 out_msg.addr := address;
307 out_msg.Type := CoherenceResponseType:DATA;
308 out_msg.Sender := machineID;
309 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
310 out_msg.DataBlk := in_msg.DataBlk;
311 out_msg.MessageSize := MessageSizeType:Response_Data;
316 action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
317 peek(memQueue_in, MemoryMsg) {
318 enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
319 assert(is_valid(tbe));
320 out_msg.PhysicalAddress := address;
321 out_msg.LineAddress := address;
322 out_msg.Type := DMAResponseType:DATA;
323 out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
324 out_msg.Destination.add(tbe.DmaRequestor);
325 out_msg.MessageSize := MessageSizeType:Response_Data;
332 action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
333 peek(requestQueue_in, RequestMsg) {
334 enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
335 assert(is_valid(tbe));
336 out_msg.PhysicalAddress := address;
337 out_msg.LineAddress := address;
338 out_msg.Type := DMAResponseType:DATA;
340 // we send the entire data block and rely on the dma controller
341 // to split it up if need be
342 out_msg.DataBlk := in_msg.DataBlk;
343 out_msg.Destination.add(tbe.DmaRequestor);
344 out_msg.MessageSize := MessageSizeType:Response_Data;
349 action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
350 enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
351 assert(is_valid(tbe));
352 out_msg.PhysicalAddress := address;
353 out_msg.LineAddress := address;
354 out_msg.Type := DMAResponseType:ACK;
355 out_msg.Destination.add(tbe.DmaRequestor);
356 out_msg.MessageSize := MessageSizeType:Writeback_Control;
360 action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
361 peek(requestQueue_in, RequestMsg) {
362 getDirectoryEntry(address).Owner.clear();
363 getDirectoryEntry(address).Owner.add(in_msg.Requestor);
367 action(f_forwardRequest, "f", desc="Forward request to owner") {
368 peek(requestQueue_in, RequestMsg) {
369 APPEND_TRANSITION_COMMENT("Own: ");
370 APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.addr).Owner);
371 APPEND_TRANSITION_COMMENT("Req: ");
372 APPEND_TRANSITION_COMMENT(in_msg.Requestor);
373 enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
374 out_msg.addr := address;
375 out_msg.Type := in_msg.Type;
376 out_msg.Requestor := in_msg.Requestor;
377 out_msg.Destination := getDirectoryEntry(in_msg.addr).Owner;
378 out_msg.MessageSize := MessageSizeType:Writeback_Control;
383 action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
384 peek(dmaRequestQueue_in, DMARequestMsg) {
385 enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
386 out_msg.addr := address;
387 out_msg.Type := CoherenceRequestType:INV;
388 out_msg.Requestor := machineID;
389 out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
390 out_msg.MessageSize := MessageSizeType:Writeback_Control;
395 action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
396 requestQueue_in.dequeue();
399 action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
400 dmaRequestQueue_in.dequeue();
403 action(v_allocateTBE, "v", desc="Allocate TBE") {
404 peek(dmaRequestQueue_in, DMARequestMsg) {
405 TBEs.allocate(address);
406 set_tbe(TBEs[address]);
407 tbe.DataBlk := in_msg.DataBlk;
408 tbe.PhysicalAddress := in_msg.PhysicalAddress;
409 tbe.Len := in_msg.Len;
410 tbe.DmaRequestor := in_msg.Requestor;
414 action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
415 peek(dmaRequestQueue_in, DMARequestMsg) {
416 TBEs.allocate(address);
417 set_tbe(TBEs[address]);
418 tbe.DmaRequestor := in_msg.Requestor;
422 action(v_allocateTBEFromRequestNet, "\v", desc="Allocate TBE") {
423 peek(requestQueue_in, RequestMsg) {
424 TBEs.allocate(address);
425 set_tbe(TBEs[address]);
426 tbe.DataBlk := in_msg.DataBlk;
430 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
431 TBEs.deallocate(address);
435 action(z_recycleRequestQueue, "z", desc="recycle request queue") {
436 requestQueue_in.recycle();
439 action(y_recycleDMARequestQueue, "y", desc="recycle dma request queue") {
440 dmaRequestQueue_in.recycle();
444 action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
445 peek(requestQueue_in, RequestMsg) {
446 queueMemoryRead(in_msg.Requestor, address, to_memory_controller_latency);
450 action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
451 peek(dmaRequestQueue_in, DMARequestMsg) {
452 queueMemoryRead(in_msg.Requestor, address, to_memory_controller_latency);
456 action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
457 peek(dmaRequestQueue_in, DMARequestMsg) {
458 queueMemoryWritePartial(in_msg.Requestor, address,
459 to_memory_controller_latency, in_msg.DataBlk,
464 action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
465 peek(requestQueue_in, RequestMsg) {
466 queueMemoryWritePartial(in_msg.Requestor, address,
467 to_memory_controller_latency, tbe.DataBlk,
472 action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
473 peek(requestQueue_in, RequestMsg) {
474 queueMemoryWrite(in_msg.Requestor, address, to_memory_controller_latency,
479 action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
480 memQueue_in.dequeue();
484 transition({M_DRD, M_DWR, M_DWRI, M_DRDI}, GETX) {
485 z_recycleRequestQueue;
488 transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) {
489 z_recycleRequestQueue;
492 transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) {
493 y_recycleDMARequestQueue;
497 transition(I, GETX, IM) {
499 qf_queueMemoryFetchRequest;
501 i_popIncomingRequestQueue;
504 transition(IM, Memory_Data, M) {
506 //e_ownerIsRequestor;
511 transition(I, DMA_READ, ID) {
513 r_allocateTbeForDmaRead;
514 qf_queueMemoryFetchRequestDMA;
515 p_popIncomingDMARequestQueue;
518 transition(ID, Memory_Data, I) {
520 //p_popIncomingDMARequestQueue;
527 transition(I, DMA_WRITE, ID_W) {
529 qw_queueMemoryWBRequest_partial;
530 p_popIncomingDMARequestQueue;
533 transition(ID_W, Memory_Ack, I) {
539 transition(M, DMA_READ, M_DRD) {
541 inv_sendCacheInvalidate;
542 p_popIncomingDMARequestQueue;
545 transition(M_DRD, PUTX, M_DRDI) {
548 l_queueMemoryWBRequest;
549 i_popIncomingRequestQueue;
552 transition(M_DRDI, Memory_Ack, I) {
559 transition(M, DMA_WRITE, M_DWR) {
561 inv_sendCacheInvalidate;
562 p_popIncomingDMARequestQueue;
565 transition(M_DWR, PUTX, M_DWRI) {
566 qw_queueMemoryWBRequest_partialTBE;
568 i_popIncomingRequestQueue;
571 transition(M_DWRI, Memory_Ack, I) {
578 transition(M, GETX, M) {
581 i_popIncomingRequestQueue;
584 transition(M, PUTX, MI) {
586 v_allocateTBEFromRequestNet;
587 l_queueMemoryWBRequest;
588 i_popIncomingRequestQueue;
591 transition(MI, Memory_Ack, I) {
597 transition(M, PUTX_NotOwner, M) {
599 i_popIncomingRequestQueue;
602 transition(I, PUTX_NotOwner, I) {
604 i_popIncomingRequestQueue;