2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
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14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 machine(Directory, "Directory protocol")
31 : DirectoryMemory * directory,
32 MemoryControl * memBuffer,
33 int directory_latency = 12
36 MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
37 MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false", vnet_type="response";
38 MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true", vnet_type="response";
40 MessageBuffer requestToDir, network="From", virtual_network="2", ordered="true", vnet_type="request";
41 MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true", vnet_type="request";
44 state_declaration(State, desc="Directory states", default="Directory_State_I") {
46 I, AccessPermission:Read_Write, desc="Invalid";
47 M, AccessPermission:Invalid, desc="Modified";
49 M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA read";
50 M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA write";
52 M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
53 M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
55 IM, AccessPermission:Busy, desc="Intermediate state I-->M";
56 MI, AccessPermission:Busy, desc="Intermediate state M-->I";
57 ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
58 ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
62 enumeration(Event, desc="Directory events") {
64 GETX, desc="A GETX arrives";
65 GETS, desc="A GETS arrives";
66 PUTX, desc="A PUTX arrives";
67 PUTX_NotOwner, desc="A PUTX arrives";
70 DMA_READ, desc="A DMA Read memory request";
71 DMA_WRITE, desc="A DMA Write memory request";
74 Memory_Data, desc="Fetched data from memory arrives";
75 Memory_Ack, desc="Writeback Ack from memory arrives";
81 structure(Entry, desc="...", interface="AbstractEntry") {
82 State DirectoryState, desc="Directory state";
83 DataBlock DataBlk, desc="data for the block";
84 NetDest Sharers, desc="Sharers for this block";
85 NetDest Owner, desc="Owner of this block";
88 // TBE entries for DMA requests
89 structure(TBE, desc="TBE entries for outstanding DMA requests") {
90 Address PhysicalAddress, desc="physical address";
91 State TBEState, desc="Transient State";
92 DataBlock DataBlk, desc="Data to be written (DMA write only)";
94 MachineID DmaRequestor, desc="DMA requestor";
97 structure(TBETable, external="yes") {
99 void allocate(Address);
100 void deallocate(Address);
101 bool isPresent(Address);
105 TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
110 Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
111 Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
113 if (is_valid(dir_entry)) {
117 dir_entry := static_cast(Entry, "pointer",
118 directory.allocate(addr, new Entry));
122 State getState(TBE tbe, Address addr) {
125 } else if (directory.isPresent(addr)) {
126 return getDirectoryEntry(addr).DirectoryState;
132 void setState(TBE tbe, Address addr, State state) {
135 tbe.TBEState := state;
138 if (directory.isPresent(addr)) {
140 if (state == State:M) {
141 assert(getDirectoryEntry(addr).Owner.count() == 1);
142 assert(getDirectoryEntry(addr).Sharers.count() == 0);
145 getDirectoryEntry(addr).DirectoryState := state;
147 if (state == State:I) {
148 assert(getDirectoryEntry(addr).Owner.count() == 0);
149 assert(getDirectoryEntry(addr).Sharers.count() == 0);
150 directory.invalidateBlock(addr);
155 AccessPermission getAccessPermission(Address addr) {
156 TBE tbe := TBEs[addr];
158 return Directory_State_to_permission(tbe.TBEState);
161 if(directory.isPresent(addr)) {
162 return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
165 return AccessPermission:NotPresent;
168 void setAccessPermission(Address addr, State state) {
169 if (directory.isPresent(addr)) {
170 getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
174 DataBlock getDataBlock(Address addr), return_by_ref="yes" {
175 TBE tbe := TBEs[addr];
180 return getDirectoryEntry(addr).DataBlk;
184 out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
185 out_port(responseNetwork_out, ResponseMsg, responseFromDir);
186 out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
187 out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
190 out_port(memQueue_out, MemoryMsg, memBuffer);
193 in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
194 if (dmaRequestQueue_in.isReady()) {
195 peek(dmaRequestQueue_in, DMARequestMsg) {
196 TBE tbe := TBEs[in_msg.LineAddress];
197 if (in_msg.Type == DMARequestType:READ) {
198 trigger(Event:DMA_READ, in_msg.LineAddress, tbe);
199 } else if (in_msg.Type == DMARequestType:WRITE) {
200 trigger(Event:DMA_WRITE, in_msg.LineAddress, tbe);
202 error("Invalid message");
208 in_port(requestQueue_in, RequestMsg, requestToDir) {
209 if (requestQueue_in.isReady()) {
210 peek(requestQueue_in, RequestMsg) {
211 TBE tbe := TBEs[in_msg.Address];
212 if (in_msg.Type == CoherenceRequestType:GETS) {
213 trigger(Event:GETS, in_msg.Address, tbe);
214 } else if (in_msg.Type == CoherenceRequestType:GETX) {
215 trigger(Event:GETX, in_msg.Address, tbe);
216 } else if (in_msg.Type == CoherenceRequestType:PUTX) {
217 if (getDirectoryEntry(in_msg.Address).Owner.isElement(in_msg.Requestor)) {
218 trigger(Event:PUTX, in_msg.Address, tbe);
220 trigger(Event:PUTX_NotOwner, in_msg.Address, tbe);
223 error("Invalid message");
230 // off-chip memory request/response is done
231 in_port(memQueue_in, MemoryMsg, memBuffer) {
232 if (memQueue_in.isReady()) {
233 peek(memQueue_in, MemoryMsg) {
234 TBE tbe := TBEs[in_msg.Address];
235 if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
236 trigger(Event:Memory_Data, in_msg.Address, tbe);
237 } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
238 trigger(Event:Memory_Ack, in_msg.Address, tbe);
240 DPRINTF(RubySlicc,"%s\n", in_msg.Type);
241 error("Invalid message");
249 action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
250 peek(requestQueue_in, RequestMsg) {
251 enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
252 out_msg.Address := address;
253 out_msg.Type := CoherenceRequestType:WB_ACK;
254 out_msg.Requestor := in_msg.Requestor;
255 out_msg.Destination.add(in_msg.Requestor);
256 out_msg.MessageSize := MessageSizeType:Writeback_Control;
261 action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
262 peek(memQueue_in, MemoryMsg) {
263 enqueue(forwardNetwork_out, RequestMsg, latency="1") {
264 out_msg.Address := address;
265 out_msg.Type := CoherenceRequestType:WB_ACK;
266 out_msg.Requestor := in_msg.OriginalRequestorMachId;
267 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
268 out_msg.MessageSize := MessageSizeType:Writeback_Control;
273 action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
274 peek(requestQueue_in, RequestMsg) {
275 enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
276 out_msg.Address := address;
277 out_msg.Type := CoherenceRequestType:WB_NACK;
278 out_msg.Requestor := in_msg.Requestor;
279 out_msg.Destination.add(in_msg.Requestor);
280 out_msg.MessageSize := MessageSizeType:Writeback_Control;
285 action(c_clearOwner, "c", desc="Clear the owner field") {
286 getDirectoryEntry(address).Owner.clear();
289 action(d_sendData, "d", desc="Send data to requestor") {
290 peek(memQueue_in, MemoryMsg) {
291 enqueue(responseNetwork_out, ResponseMsg, latency="1") {
292 out_msg.Address := address;
293 out_msg.Type := CoherenceResponseType:DATA;
294 out_msg.Sender := machineID;
295 out_msg.Destination.add(in_msg.OriginalRequestorMachId);
296 out_msg.DataBlk := in_msg.DataBlk;
297 out_msg.MessageSize := MessageSizeType:Response_Data;
302 action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
303 peek(memQueue_in, MemoryMsg) {
304 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
305 assert(is_valid(tbe));
306 out_msg.PhysicalAddress := address;
307 out_msg.LineAddress := address;
308 out_msg.Type := DMAResponseType:DATA;
309 out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
310 out_msg.Destination.add(tbe.DmaRequestor);
311 out_msg.MessageSize := MessageSizeType:Response_Data;
318 action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
319 peek(requestQueue_in, RequestMsg) {
320 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
321 assert(is_valid(tbe));
322 out_msg.PhysicalAddress := address;
323 out_msg.LineAddress := address;
324 out_msg.Type := DMAResponseType:DATA;
325 out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
326 out_msg.Destination.add(tbe.DmaRequestor);
327 out_msg.MessageSize := MessageSizeType:Response_Data;
332 action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
333 enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
334 assert(is_valid(tbe));
335 out_msg.PhysicalAddress := address;
336 out_msg.LineAddress := address;
337 out_msg.Type := DMAResponseType:ACK;
338 out_msg.Destination.add(tbe.DmaRequestor);
339 out_msg.MessageSize := MessageSizeType:Writeback_Control;
343 action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
344 peek(requestQueue_in, RequestMsg) {
345 getDirectoryEntry(address).Owner.clear();
346 getDirectoryEntry(address).Owner.add(in_msg.Requestor);
350 action(f_forwardRequest, "f", desc="Forward request to owner") {
351 peek(requestQueue_in, RequestMsg) {
352 APPEND_TRANSITION_COMMENT("Own: ");
353 APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Address).Owner);
354 APPEND_TRANSITION_COMMENT("Req: ");
355 APPEND_TRANSITION_COMMENT(in_msg.Requestor);
356 enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
357 out_msg.Address := address;
358 out_msg.Type := in_msg.Type;
359 out_msg.Requestor := in_msg.Requestor;
360 out_msg.Destination := getDirectoryEntry(in_msg.Address).Owner;
361 out_msg.MessageSize := MessageSizeType:Writeback_Control;
366 action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
367 peek(dmaRequestQueue_in, DMARequestMsg) {
368 enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
369 out_msg.Address := address;
370 out_msg.Type := CoherenceRequestType:INV;
371 out_msg.Requestor := machineID;
372 out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
373 out_msg.MessageSize := MessageSizeType:Writeback_Control;
378 action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
379 requestQueue_in.dequeue();
382 action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
383 dmaRequestQueue_in.dequeue();
386 action(l_writeDataToMemory, "pl", desc="Write PUTX data to memory") {
387 peek(requestQueue_in, RequestMsg) {
388 // assert(in_msg.Dirty);
389 // assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
390 getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
391 //getDirectoryEntry(in_msg.Address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
395 action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
396 assert(is_valid(tbe));
397 getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
400 action(v_allocateTBE, "v", desc="Allocate TBE") {
401 peek(dmaRequestQueue_in, DMARequestMsg) {
402 TBEs.allocate(address);
403 set_tbe(TBEs[address]);
404 tbe.DataBlk := in_msg.DataBlk;
405 tbe.PhysicalAddress := in_msg.PhysicalAddress;
406 tbe.Len := in_msg.Len;
407 tbe.DmaRequestor := in_msg.Requestor;
411 action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
412 peek(dmaRequestQueue_in, DMARequestMsg) {
413 TBEs.allocate(address);
414 set_tbe(TBEs[address]);
415 tbe.DmaRequestor := in_msg.Requestor;
419 action(v_allocateTBEFromRequestNet, "\v", desc="Allocate TBE") {
420 peek(requestQueue_in, RequestMsg) {
421 TBEs.allocate(address);
422 set_tbe(TBEs[address]);
423 tbe.DataBlk := in_msg.DataBlk;
427 action(w_deallocateTBE, "w", desc="Deallocate TBE") {
428 TBEs.deallocate(address);
432 action(z_recycleRequestQueue, "z", desc="recycle request queue") {
433 requestQueue_in.recycle();
436 action(y_recycleDMARequestQueue, "y", desc="recycle dma request queue") {
437 dmaRequestQueue_in.recycle();
441 action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
442 peek(requestQueue_in, RequestMsg) {
443 enqueue(memQueue_out, MemoryMsg, latency="1") {
444 out_msg.Address := address;
445 out_msg.Type := MemoryRequestType:MEMORY_READ;
446 out_msg.Sender := machineID;
447 out_msg.OriginalRequestorMachId := in_msg.Requestor;
448 out_msg.MessageSize := in_msg.MessageSize;
449 out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
450 DPRINTF(RubySlicc,"%s\n", out_msg);
455 action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
456 peek(dmaRequestQueue_in, DMARequestMsg) {
457 enqueue(memQueue_out, MemoryMsg, latency="1") {
458 out_msg.Address := address;
459 out_msg.Type := MemoryRequestType:MEMORY_READ;
460 out_msg.Sender := machineID;
461 //out_msg.OriginalRequestorMachId := machineID;
462 out_msg.MessageSize := in_msg.MessageSize;
463 out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
464 DPRINTF(RubySlicc,"%s\n", out_msg);
469 action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
470 peek(dmaRequestQueue_in, DMARequestMsg) {
471 enqueue(memQueue_out, MemoryMsg, latency="1") {
472 out_msg.Address := address;
473 out_msg.Type := MemoryRequestType:MEMORY_WB;
474 //out_msg.OriginalRequestorMachId := machineID;
475 //out_msg.DataBlk := in_msg.DataBlk;
476 out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len);
477 out_msg.MessageSize := in_msg.MessageSize;
478 //out_msg.Prefetch := in_msg.Prefetch;
480 DPRINTF(RubySlicc,"%s\n", out_msg);
485 action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
486 peek(requestQueue_in, RequestMsg) {
487 enqueue(memQueue_out, MemoryMsg, latency="1") {
488 assert(is_valid(tbe));
489 out_msg.Address := address;
490 out_msg.Type := MemoryRequestType:MEMORY_WB;
491 out_msg.OriginalRequestorMachId := in_msg.Requestor;
493 // out_msg.DataBlk := in_msg.DataBlk;
494 out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
495 out_msg.MessageSize := in_msg.MessageSize;
496 //out_msg.Prefetch := in_msg.Prefetch;
498 DPRINTF(RubySlicc,"%s\n", out_msg);
505 action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
506 peek(requestQueue_in, RequestMsg) {
507 enqueue(memQueue_out, MemoryMsg, latency="1") {
508 out_msg.Address := address;
509 out_msg.Type := MemoryRequestType:MEMORY_WB;
510 out_msg.Sender := machineID;
511 out_msg.OriginalRequestorMachId := in_msg.Requestor;
512 out_msg.DataBlk := in_msg.DataBlk;
513 out_msg.MessageSize := in_msg.MessageSize;
515 DPRINTF(RubySlicc,"%s\n", out_msg);
520 action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
521 memQueue_in.dequeue();
524 action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
525 assert(is_valid(tbe));
526 getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
531 transition({M_DRD, M_DWR, M_DWRI, M_DRDI}, GETX) {
532 z_recycleRequestQueue;
535 transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) {
536 z_recycleRequestQueue;
539 transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) {
540 y_recycleDMARequestQueue;
544 transition(I, GETX, IM) {
546 qf_queueMemoryFetchRequest;
548 i_popIncomingRequestQueue;
551 transition(IM, Memory_Data, M) {
553 //e_ownerIsRequestor;
558 transition(I, DMA_READ, ID) {
560 r_allocateTbeForDmaRead;
561 qf_queueMemoryFetchRequestDMA;
562 p_popIncomingDMARequestQueue;
565 transition(ID, Memory_Data, I) {
567 //p_popIncomingDMARequestQueue;
574 transition(I, DMA_WRITE, ID_W) {
576 qw_queueMemoryWBRequest_partial;
577 p_popIncomingDMARequestQueue;
580 transition(ID_W, Memory_Ack, I) {
581 dwt_writeDMADataFromTBE;
587 transition(M, DMA_READ, M_DRD) {
589 inv_sendCacheInvalidate;
590 p_popIncomingDMARequestQueue;
593 transition(M_DRD, PUTX, M_DRDI) {
597 l_queueMemoryWBRequest;
598 i_popIncomingRequestQueue;
601 transition(M_DRDI, Memory_Ack, I) {
608 transition(M, DMA_WRITE, M_DWR) {
610 inv_sendCacheInvalidate;
611 p_popIncomingDMARequestQueue;
614 transition(M_DWR, PUTX, M_DWRI) {
616 qw_queueMemoryWBRequest_partialTBE;
618 i_popIncomingRequestQueue;
621 transition(M_DWRI, Memory_Ack, I) {
622 w_writeDataToMemoryFromTBE;
629 transition(M, GETX, M) {
632 i_popIncomingRequestQueue;
635 transition(M, PUTX, MI) {
637 v_allocateTBEFromRequestNet;
638 l_queueMemoryWBRequest;
639 i_popIncomingRequestQueue;
642 transition(MI, Memory_Ack, I) {
643 w_writeDataToMemoryFromTBE;
649 transition(M, PUTX_NotOwner, M) {
651 i_popIncomingRequestQueue;
654 transition(I, PUTX_NotOwner, I) {
656 i_popIncomingRequestQueue;