2 * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 machine(DMA, "DMA Controller")
31 : DMASequencer * dma_sequencer;
32 Cycles request_latency := 6;
34 MessageBuffer * responseFromDir, network="From", virtual_network="1",
36 MessageBuffer * requestToDir, network="To", virtual_network="0",
38 MessageBuffer * mandatoryQueue;
40 state_declaration(State, desc="DMA states", default="DMA_State_READY") {
41 READY, AccessPermission:Invalid, desc="Ready to accept a new request";
42 BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
43 BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
46 enumeration(Event, desc="DMA events") {
47 ReadRequest, desc="A new read request";
48 WriteRequest, desc="A new write request";
49 Data, desc="Data from a DMA memory read";
50 Ack, desc="DMA write to memory completed";
56 Cycles ticksToCycles(Tick t);
58 State getState(Addr addr) {
62 void setState(Addr addr, State state) {
66 AccessPermission getAccessPermission(Addr addr) {
67 return AccessPermission:NotPresent;
70 void setAccessPermission(Addr addr, State state) {
73 void functionalRead(Addr addr, Packet *pkt) {
74 error("DMA does not support functional read.");
77 int functionalWrite(Addr addr, Packet *pkt) {
78 error("DMA does not support functional write.");
81 out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="...");
83 in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
84 if (dmaRequestQueue_in.isReady(clockEdge())) {
85 peek(dmaRequestQueue_in, SequencerMsg) {
86 if (in_msg.Type == SequencerRequestType:LD ) {
87 trigger(Event:ReadRequest, in_msg.LineAddress);
88 } else if (in_msg.Type == SequencerRequestType:ST) {
89 trigger(Event:WriteRequest, in_msg.LineAddress);
91 error("Invalid request type");
97 in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
98 if (dmaResponseQueue_in.isReady(clockEdge())) {
99 peek( dmaResponseQueue_in, DMAResponseMsg) {
100 if (in_msg.Type == DMAResponseType:ACK) {
101 trigger(Event:Ack, in_msg.LineAddress);
102 } else if (in_msg.Type == DMAResponseType:DATA) {
103 trigger(Event:Data, in_msg.LineAddress);
105 error("Invalid response type");
111 action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
112 peek(dmaRequestQueue_in, SequencerMsg) {
113 enqueue(requestToDir_out, DMARequestMsg, request_latency) {
114 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
115 out_msg.LineAddress := in_msg.LineAddress;
116 out_msg.Type := DMARequestType:READ;
117 out_msg.Requestor := machineID;
118 out_msg.DataBlk := in_msg.DataBlk;
119 out_msg.Len := in_msg.Len;
120 out_msg.Destination.add(map_Address_to_Directory(address));
121 out_msg.MessageSize := MessageSizeType:Writeback_Control;
126 action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
127 peek(dmaRequestQueue_in, SequencerMsg) {
128 enqueue(requestToDir_out, DMARequestMsg, request_latency) {
129 out_msg.PhysicalAddress := in_msg.PhysicalAddress;
130 out_msg.LineAddress := in_msg.LineAddress;
131 out_msg.Type := DMARequestType:WRITE;
132 out_msg.Requestor := machineID;
133 out_msg.DataBlk := in_msg.DataBlk;
134 out_msg.Len := in_msg.Len;
135 out_msg.Destination.add(map_Address_to_Directory(address));
136 out_msg.MessageSize := MessageSizeType:Writeback_Control;
141 action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
142 peek (dmaResponseQueue_in, DMAResponseMsg) {
143 dma_sequencer.ackCallback();
147 action(d_dataCallback, "d", desc="Write data to dma sequencer") {
148 peek (dmaResponseQueue_in, DMAResponseMsg) {
149 dma_sequencer.dataCallback(in_msg.DataBlk);
153 action(p_popRequestQueue, "p", desc="Pop request queue") {
154 dmaRequestQueue_in.dequeue(clockEdge());
157 action(p_popResponseQueue, "\p", desc="Pop request queue") {
158 dmaResponseQueue_in.dequeue(clockEdge());
161 transition(READY, ReadRequest, BUSY_RD) {
166 transition(READY, WriteRequest, BUSY_WR) {
171 transition(BUSY_RD, Data, READY) {
176 transition(BUSY_WR, Ack, READY) {