cpu: Add TraceCPU to playback elastic traces
[gem5.git] / src / mem / protocol / MI_example-msg.sm
1 /*
2 * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 // CoherenceRequestType
30 enumeration(CoherenceRequestType, desc="...") {
31 GETX, desc="Get eXclusive";
32 GETS, desc="Get Shared";
33 PUTX, desc="Put eXclusive";
34 WB_ACK, desc="Writeback ack";
35 WB_NACK, desc="Writeback neg. ack";
36 INV, desc="Invalidation";
37 }
38
39 // CoherenceResponseType
40 enumeration(CoherenceResponseType, desc="...") {
41 ACK, desc="ACKnowledgment, responder doesn't have a copy";
42 DATA, desc="Data";
43 DATA_EXCLUSIVE_CLEAN, desc="Data, no other processor has a copy, data is clean";
44 DATA_EXCLUSIVE_DIRTY, desc="Data, no other processor has a copy, data is dirty";
45 UNBLOCK, desc="Unblock";
46 UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
47 WRITEBACK_CLEAN, desc="Clean writeback (no data)";
48 WRITEBACK_DIRTY, desc="Dirty writeback (contains data)";
49 WRITEBACK, desc="Generic writeback (contains data)";
50 }
51
52 // RequestMsg (and also forwarded requests)
53 structure(RequestMsg, desc="...", interface="Message") {
54 Addr addr, desc="Physical address for this request";
55 CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
56 MachineID Requestor, desc="Node who initiated the request";
57 NetDest Destination, desc="Multicast destination mask";
58 DataBlock DataBlk, desc="data for the cache line";
59 MessageSizeType MessageSize, desc="size category of the message";
60
61 bool functionalRead(Packet *pkt) {
62 // Valid data block is only present in PUTX messages
63 if (Type == CoherenceRequestType:PUTX) {
64 return testAndRead(addr, DataBlk, pkt);
65 }
66 return false;
67 }
68
69 bool functionalWrite(Packet *pkt) {
70 // No check on message type required since the protocol should read
71 // data block from only those messages that contain valid data
72 return testAndWrite(addr, DataBlk, pkt);
73 }
74 }
75
76 // ResponseMsg (and also unblock requests)
77 structure(ResponseMsg, desc="...", interface="Message") {
78 Addr addr, desc="Physical address for this request";
79 CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
80 MachineID Sender, desc="Node who sent the data";
81 NetDest Destination, desc="Node to whom the data is sent";
82 DataBlock DataBlk, desc="data for the cache line";
83 bool Dirty, desc="Is the data dirty (different than memory)?";
84 MessageSizeType MessageSize, desc="size category of the message";
85
86 bool functionalRead(Packet *pkt) {
87 // A check on message type should appear here so that only those
88 // messages that contain data
89 return testAndRead(addr, DataBlk, pkt);
90 }
91
92 bool functionalWrite(Packet *pkt) {
93 // No check on message type required since the protocol should read
94 // data block from only those messages that contain valid data
95 return testAndWrite(addr, DataBlk, pkt);
96 }
97 }
98
99 enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") {
100 READ, desc="Memory Read";
101 WRITE, desc="Memory Write";
102 NULL, desc="Invalid";
103 }
104
105 enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
106 DATA, desc="DATA read";
107 ACK, desc="ACK write";
108 NULL, desc="Invalid";
109 }
110
111 structure(DMARequestMsg, desc="...", interface="Message") {
112 DMARequestType Type, desc="Request type (read/write)";
113 Addr PhysicalAddress, desc="Physical address for this request";
114 Addr LineAddress, desc="Line address for this request";
115 MachineID Requestor, desc="Node who initiated the request";
116 NetDest Destination, desc="Destination";
117 DataBlock DataBlk, desc="DataBlk attached to this request";
118 int Len, desc="The length of the request";
119 MessageSizeType MessageSize, desc="size category of the message";
120
121 bool functionalRead(Packet *pkt) {
122 return testAndRead(LineAddress, DataBlk, pkt);
123 }
124
125 bool functionalWrite(Packet *pkt) {
126 return testAndWrite(LineAddress, DataBlk, pkt);
127 }
128 }
129
130 structure(DMAResponseMsg, desc="...", interface="Message") {
131 DMAResponseType Type, desc="Response type (DATA/ACK)";
132 Addr PhysicalAddress, desc="Physical address for this request";
133 Addr LineAddress, desc="Line address for this request";
134 NetDest Destination, desc="Destination";
135 DataBlock DataBlk, desc="DataBlk attached to this request";
136 MessageSizeType MessageSize, desc="size category of the message";
137
138 bool functionalRead(Packet *pkt) {
139 return testAndRead(LineAddress, DataBlk, pkt);
140 }
141
142 bool functionalWrite(Packet *pkt) {
143 return testAndWrite(LineAddress, DataBlk, pkt);
144 }
145 }