src/mem/protocol/MOESI_AMD_Base-CorePair.sm

   1 /*
   2  * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: Lisa Hsu
  34  */
  35
  36 machine(MachineType:CorePair, "CP-like Core Coherence")
  37  : Sequencer * sequencer;
  38    Sequencer * sequencer1;
  39    CacheMemory * L1Icache;
  40    CacheMemory * L1D0cache;
  41    CacheMemory * L1D1cache;
  42    CacheMemory * L2cache;     // func mem logic looks in this CacheMemory
  43    bool send_evictions := "False";
  44    Cycles issue_latency := 5;  // time to send data down to NB
  45    Cycles l2_hit_latency := 18;
  46
  47   // BEGIN Core Buffers
  48
  49   // To the Network
  50   MessageBuffer * requestFromCore, network="To", virtual_network="0", vnet_type="request";
  51   MessageBuffer * responseFromCore, network="To", virtual_network="2", vnet_type="response";
  52   MessageBuffer * unblockFromCore, network="To", virtual_network="4", vnet_type="unblock";
  53
  54   // From the Network
  55   MessageBuffer * probeToCore, network="From", virtual_network="0", vnet_type="request";
  56   MessageBuffer * responseToCore, network="From", virtual_network="2", vnet_type="response";
  57
  58   MessageBuffer * mandatoryQueue;
  59
  60   MessageBuffer * triggerQueue, ordered="true";
  61
  62   // END Core Buffers
  63
  64 {
  65   // BEGIN STATES
  66   state_declaration(State, desc="Cache states", default="CorePair_State_I") {
  67
  68     // Base States
  69     I, AccessPermission:Invalid, desc="Invalid";
  70     S, AccessPermission:Read_Only, desc="Shared";
  71     E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership";
  72     E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership";
  73     Es, AccessPermission:Read_Write, desc="Exclusive in core";
  74     O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line";
  75     Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line";
  76     M0, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  77     M1, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  78
  79     // Transient States
  80     I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  81     I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  82     I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well";
  83     I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well";
  84     I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well";
  85     I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well";
  86     I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  87     I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  88     I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters";
  89
  90     IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive";
  91     IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive";
  92     IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills";
  93     IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  94     IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  95     F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received";
  96     F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received";
  97
  98     ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack";
  99     MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack";
 100     MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
 101     MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
 102     S_F0, AccessPermission:Read_Only,  desc="Shared, filling L1";
 103     S_F1, AccessPermission:Read_Only,  desc="Shared, filling L1";
 104     S_F, AccessPermission:Read_Only,   desc="Shared, filling L1";
 105     O_F0, AccessPermission:Read_Only,  desc="Owned, filling L1";
 106     O_F1, AccessPermission:Read_Only,  desc="Owned, filling L1";
 107     O_F,  AccessPermission:Read_Only,  desc="Owned, filling L1";
 108     Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache";
 109     Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache";
 110     S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 111     S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 112     O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 113     O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 114     S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response";
 115     S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response";
 116
 117     Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 118     Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 119     Es_F, AccessPermission:Read_Write,  desc="Es, other cluster read, filling";
 120     E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling";
 121     E1_F, AccessPermission:Read_Write, desc="...";
 122     E0_Es, AccessPermission:Read_Write, desc="...";
 123     E1_Es, AccessPermission:Read_Write, desc="...";
 124     Ms_F0, AccessPermission:Read_Write, desc="...";
 125     Ms_F1, AccessPermission:Read_Write, desc="...";
 126     Ms_F, AccessPermission:Read_Write,  desc="...";
 127     M0_F, AccessPermission:Read_Write, desc="...";
 128     M0_Ms, AccessPermission:Read_Write, desc="...";
 129     M1_F, AccessPermission:Read_Write, desc="...";
 130     M1_Ms, AccessPermission:Read_Write, desc="...";
 131
 132     I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback";
 133     S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 134     S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 135     S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck";
 136
 137   } // END STATES
 138
 139   // BEGIN EVENTS
 140   enumeration(Event, desc="CP Events") {
 141     // CP Initiated events
 142     C0_Load_L1miss,            desc="Cluster 0 load, L1 missed";
 143     C0_Load_L1hit,             desc="Cluster 0 load, L1 hit";
 144     C1_Load_L1miss,            desc="Cluster 1 load L1 missed";
 145     C1_Load_L1hit,             desc="Cluster 1 load L1 hit";
 146     Ifetch0_L1hit,             desc="Instruction fetch, hit in the L1";
 147     Ifetch1_L1hit,             desc="Instruction fetch, hit in the L1";
 148     Ifetch0_L1miss,            desc="Instruction fetch, missed in the L1";
 149     Ifetch1_L1miss,            desc="Instruction fetch, missed in the L1";
 150     C0_Store_L1miss,           desc="Cluster 0 store missed in L1";
 151     C0_Store_L1hit,            desc="Cluster 0 store hit in L1";
 152     C1_Store_L1miss,           desc="Cluster 1 store missed in L1";
 153     C1_Store_L1hit,            desc="Cluster 1 store hit in L1";
 154     // NB Initiated events
 155     NB_AckS,             desc="NB Ack to Core Request";
 156     NB_AckM,             desc="NB Ack to Core Request";
 157     NB_AckE,             desc="NB Ack to Core Request";
 158
 159     NB_AckWB,            desc="NB Ack for writeback";
 160
 161     // Memory System initiatied events
 162     L1I_Repl,           desc="Replace address from L1I"; // Presumed clean
 163     L1D0_Repl,           desc="Replace address from L1D0"; // Presumed clean
 164     L1D1_Repl,           desc="Replace address from L1D1"; // Presumed clean
 165     L2_Repl,            desc="Replace address from L2";
 166
 167     L2_to_L1D0,           desc="L1 fill from L2";
 168     L2_to_L1D1,           desc="L1 fill from L2";
 169     L2_to_L1I,           desc="L1 fill from L2";
 170
 171     // Probe Events
 172     PrbInvData,         desc="probe, return O or M data";
 173     PrbInv,             desc="probe, no need for data";
 174     PrbShrData,         desc="probe downgrade, return O or M data";
 175
 176   }  // END EVENTS
 177
 178   enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
 179     L1D0DataArrayRead,    desc="Read the data array";
 180     L1D0DataArrayWrite,   desc="Write the data array";
 181     L1D0TagArrayRead,     desc="Read the data array";
 182     L1D0TagArrayWrite,    desc="Write the data array";
 183     L1D1DataArrayRead,    desc="Read the data array";
 184     L1D1DataArrayWrite,   desc="Write the data array";
 185     L1D1TagArrayRead,     desc="Read the data array";
 186     L1D1TagArrayWrite,    desc="Write the data array";
 187     L1IDataArrayRead,     desc="Read the data array";
 188     L1IDataArrayWrite,    desc="Write the data array";
 189     L1ITagArrayRead,      desc="Read the data array";
 190     L1ITagArrayWrite,     desc="Write the data array";
 191     L2DataArrayRead,      desc="Read the data array";
 192     L2DataArrayWrite,     desc="Write the data array";
 193     L2TagArrayRead,       desc="Read the data array";
 194     L2TagArrayWrite,      desc="Write the data array";
 195   }
 196
 197
 198   // BEGIN STRUCTURE DEFINITIONS
 199
 200
 201   // Cache Entry
 202   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 203     State CacheState,           desc="cache state";
 204     bool Dirty,                 desc="Is the data dirty (diff than memory)?";
 205     DataBlock DataBlk,          desc="data for the block";
 206     bool FromL2, default="false", desc="block just moved from L2";
 207   }
 208
 209   structure(TBE, desc="...") {
 210     State TBEState,             desc="Transient state";
 211     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 212     bool Dirty,              desc="Is the data dirty (different than memory)?";
 213     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 214     bool Shared,             desc="Victim hit by shared probe";
 215    }
 216
 217   structure(TBETable, external="yes") {
 218     TBE lookup(Addr);
 219     void allocate(Addr);
 220     void deallocate(Addr);
 221     bool isPresent(Addr);
 222   }
 223
 224   TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
 225
 226   void set_cache_entry(AbstractCacheEntry b);
 227   void unset_cache_entry();
 228   void set_tbe(TBE b);
 229   void unset_tbe();
 230   void wakeUpAllBuffers();
 231   void wakeUpBuffers(Addr a);
 232   Cycles curCycle();
 233   MachineID mapAddressToMachine(Addr addr, MachineType mtype);
 234
 235   // END STRUCTURE DEFINITIONS
 236
 237   // BEGIN INTERNAL FUNCTIONS
 238
 239   Tick clockEdge();
 240   Tick cyclesToTicks(Cycles c);
 241
 242   bool addressInCore(Addr addr) {
 243     return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr));
 244   }
 245
 246   Entry getCacheEntry(Addr address), return_by_pointer="yes" {
 247     Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
 248     return L2cache_entry;
 249   }
 250
 251   DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
 252     TBE tbe := TBEs.lookup(addr);
 253     if(is_valid(tbe)) {
 254       return tbe.DataBlk;
 255     } else {
 256       return getCacheEntry(addr).DataBlk;
 257     }
 258   }
 259
 260   Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" {
 261     if (cluster == 0) {
 262       Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr));
 263       return L1D0_entry;
 264     } else {
 265       Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr));
 266       return L1D1_entry;
 267     }
 268   }
 269
 270   Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
 271     Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
 272     return c_entry;
 273   }
 274
 275   bool presentOrAvail2(Addr addr) {
 276     return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
 277   }
 278
 279   bool presentOrAvailI(Addr addr) {
 280     return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr);
 281   }
 282
 283   bool presentOrAvailD0(Addr addr) {
 284     return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr);
 285   }
 286
 287   bool presentOrAvailD1(Addr addr) {
 288     return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr);
 289   }
 290
 291   State getState(TBE tbe, Entry cache_entry, Addr addr) {
 292     if(is_valid(tbe)) {
 293       return tbe.TBEState;
 294     } else if (is_valid(cache_entry)) {
 295       return cache_entry.CacheState;
 296     }
 297     return State:I;
 298   }
 299
 300   void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
 301     if (is_valid(tbe)) {
 302       tbe.TBEState := state;
 303     }
 304
 305     if (is_valid(cache_entry)) {
 306       cache_entry.CacheState := state;
 307     }
 308   }
 309
 310   AccessPermission getAccessPermission(Addr addr) {
 311     TBE tbe := TBEs.lookup(addr);
 312     if(is_valid(tbe)) {
 313       return CorePair_State_to_permission(tbe.TBEState);
 314     }
 315
 316     Entry cache_entry := getCacheEntry(addr);
 317     if(is_valid(cache_entry)) {
 318       return CorePair_State_to_permission(cache_entry.CacheState);
 319     }
 320
 321     return AccessPermission:NotPresent;
 322   }
 323
 324   void functionalRead(Addr addr, Packet *pkt) {
 325     TBE tbe := TBEs.lookup(addr);
 326     if(is_valid(tbe)) {
 327       testAndRead(addr, tbe.DataBlk, pkt);
 328     } else {
 329       functionalMemoryRead(pkt);
 330     }
 331   }
 332
 333   int functionalWrite(Addr addr, Packet *pkt) {
 334     int num_functional_writes := 0;
 335
 336     TBE tbe := TBEs.lookup(addr);
 337     if(is_valid(tbe)) {
 338       num_functional_writes := num_functional_writes +
 339             testAndWrite(addr, tbe.DataBlk, pkt);
 340     }
 341
 342     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
 343     return num_functional_writes;
 344   }
 345
 346   void setAccessPermission(Entry cache_entry, Addr addr, State state) {
 347     if (is_valid(cache_entry)) {
 348       cache_entry.changePermission(CorePair_State_to_permission(state));
 349     }
 350   }
 351
 352   MachineType testAndClearLocalHit(Entry cache_entry) {
 353     assert(is_valid(cache_entry));
 354     if (cache_entry.FromL2) {
 355       cache_entry.FromL2 := false;
 356       return MachineType:L2Cache;
 357     } else {
 358       return MachineType:L1Cache;
 359     }
 360   }
 361
 362   void recordRequestType(RequestType request_type, Addr addr) {
 363     if (request_type == RequestType:L1D0DataArrayRead) {
 364         L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 365     } else if (request_type == RequestType:L1D0DataArrayWrite) {
 366         L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 367     } else if (request_type == RequestType:L1D0TagArrayRead) {
 368         L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 369     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 370         L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 371     } else if (request_type == RequestType:L1D1DataArrayRead) {
 372         L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 373     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 374         L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 375     } else if (request_type == RequestType:L1D1TagArrayRead) {
 376         L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 377     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 378         L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 379     } else if (request_type == RequestType:L1IDataArrayRead) {
 380         L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 381     } else if (request_type == RequestType:L1IDataArrayWrite) {
 382         L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 383     } else if (request_type == RequestType:L1ITagArrayRead) {
 384         L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 385     } else if (request_type == RequestType:L1ITagArrayWrite) {
 386         L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 387     } else if (request_type == RequestType:L2DataArrayRead) {
 388         L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 389     } else if (request_type == RequestType:L2DataArrayWrite) {
 390         L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 391     } else if (request_type == RequestType:L2TagArrayRead) {
 392         L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 393     } else if (request_type == RequestType:L2TagArrayWrite) {
 394         L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 395     }
 396   }
 397
 398   bool checkResourceAvailable(RequestType request_type, Addr addr) {
 399     if (request_type == RequestType:L2DataArrayRead) {
 400       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 401     } else if (request_type == RequestType:L2DataArrayWrite) {
 402       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 403     } else if (request_type == RequestType:L2TagArrayRead) {
 404       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 405     } else if (request_type == RequestType:L2TagArrayWrite) {
 406       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 407     } else if  (request_type == RequestType:L1D0DataArrayRead) {
 408       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 409     } else if (request_type == RequestType:L1D0DataArrayWrite) {
 410       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 411     } else if (request_type == RequestType:L1D0TagArrayRead) {
 412       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 413     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 414       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 415     } else if (request_type == RequestType:L1D1DataArrayRead) {
 416       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 417     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 418       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 419     } else if (request_type == RequestType:L1D1TagArrayRead) {
 420       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 421     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 422       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 423     } else if (request_type == RequestType:L1IDataArrayRead) {
 424       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 425     } else if (request_type == RequestType:L1IDataArrayWrite) {
 426       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 427     } else if (request_type == RequestType:L1ITagArrayRead) {
 428       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 429     } else if (request_type == RequestType:L1ITagArrayWrite) {
 430       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 431
 432     } else {
 433       return true;
 434     }
 435   }
 436
 437   // END INTERNAL FUNCTIONS
 438
 439   // ** OUT_PORTS **
 440
 441   out_port(requestNetwork_out, CPURequestMsg, requestFromCore);
 442   out_port(responseNetwork_out, ResponseMsg, responseFromCore);
 443   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 444   out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
 445
 446   // ** IN_PORTS **
 447
 448   in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") {
 449     if (triggerQueue_in.isReady(clockEdge())) {
 450       peek(triggerQueue_in, TriggerMsg) {
 451         Entry cache_entry := getCacheEntry(in_msg.addr);
 452         TBE tbe := TBEs.lookup(in_msg.addr);
 453
 454         if (in_msg.Type == TriggerType:L2_to_L1) {
 455           if (in_msg.Dest == CacheId:L1I) {
 456             trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe);
 457           } else if (in_msg.Dest == CacheId:L1D0) {
 458             trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe);
 459           } else if (in_msg.Dest == CacheId:L1D1) {
 460             trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe);
 461           } else {
 462             error("unexpected trigger dest");
 463           }
 464         }
 465       }
 466     }
 467   }
 468
 469
 470   in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) {
 471     if (probeNetwork_in.isReady(clockEdge())) {
 472       peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") {
 473         Entry cache_entry := getCacheEntry(in_msg.addr);
 474         TBE tbe := TBEs.lookup(in_msg.addr);
 475
 476         if (in_msg.Type == ProbeRequestType:PrbInv) {
 477           if (in_msg.ReturnData) {
 478             trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
 479           } else {
 480             trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
 481           }
 482         } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
 483           assert(in_msg.ReturnData);
 484           trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
 485         }
 486       }
 487     }
 488   }
 489
 490
 491   // ResponseNetwork
 492   in_port(responseToCore_in, ResponseMsg, responseToCore) {
 493     if (responseToCore_in.isReady(clockEdge())) {
 494       peek(responseToCore_in, ResponseMsg, block_on="addr") {
 495
 496         Entry cache_entry := getCacheEntry(in_msg.addr);
 497         TBE tbe := TBEs.lookup(in_msg.addr);
 498
 499         if (in_msg.Type == CoherenceResponseType:NBSysResp) {
 500           if (in_msg.State == CoherenceState:Modified) {
 501               trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe);
 502           } else if (in_msg.State == CoherenceState:Shared) {
 503             trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe);
 504           } else if (in_msg.State == CoherenceState:Exclusive) {
 505             trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe);
 506           }
 507         } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
 508           trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe);
 509         } else {
 510           error("Unexpected Response Message to Core");
 511         }
 512       }
 513     }
 514   }
 515
 516   // Nothing from the Unblock Network
 517
 518   // Mandatory Queue
 519   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 520     if (mandatoryQueue_in.isReady(clockEdge())) {
 521       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 522
 523         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
 524         TBE tbe := TBEs.lookup(in_msg.LineAddress);
 525
 526         if (in_msg.Type == RubyRequestType:IFETCH) {
 527           // FETCH ACCESS
 528
 529           if (L1Icache.isTagPresent(in_msg.LineAddress)) {
 530             if (mod(in_msg.contextId, 2) == 0) {
 531               trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe);
 532             } else {
 533               trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe);
 534             }
 535           } else {
 536             if (presentOrAvail2(in_msg.LineAddress)) {
 537               if (presentOrAvailI(in_msg.LineAddress)) {
 538                 if (mod(in_msg.contextId, 2) == 0) {
 539                   trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry,
 540                           tbe);
 541                 } else {
 542                   trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry,
 543                           tbe);
 544                 }
 545               } else {
 546                 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
 547                 trigger(Event:L1I_Repl, victim,
 548                         getCacheEntry(victim), TBEs.lookup(victim));
 549               }
 550             } else { // Not present or avail in L2
 551               Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 552               trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 553                       TBEs.lookup(victim));
 554             }
 555           }
 556         } else {
 557           // DATA ACCESS
 558           if (mod(in_msg.contextId, 2) == 1) {
 559             if (L1D1cache.isTagPresent(in_msg.LineAddress)) {
 560               if (in_msg.Type == RubyRequestType:LD) {
 561                 trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry,
 562                         tbe);
 563               } else {
 564                 // Stores must write through, make sure L2 avail.
 565                 if (presentOrAvail2(in_msg.LineAddress)) {
 566                   trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry,
 567                           tbe);
 568                 } else {
 569                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 570                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 571                           TBEs.lookup(victim));
 572                 }
 573               }
 574             } else {
 575               if (presentOrAvail2(in_msg.LineAddress)) {
 576                 if (presentOrAvailD1(in_msg.LineAddress)) {
 577                   if (in_msg.Type == RubyRequestType:LD) {
 578                     trigger(Event:C1_Load_L1miss, in_msg.LineAddress,
 579                             cache_entry, tbe);
 580                   } else {
 581                     trigger(Event:C1_Store_L1miss, in_msg.LineAddress,
 582                             cache_entry, tbe);
 583                   }
 584                 } else {
 585                   Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
 586                   trigger(Event:L1D1_Repl, victim,
 587                           getCacheEntry(victim), TBEs.lookup(victim));
 588                 }
 589               } else { // not present or avail in L2
 590                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 591                 trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
 592               }
 593             }
 594           } else {
 595             Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0);
 596             if (is_valid(L1D0cache_entry)) {
 597               if (in_msg.Type == RubyRequestType:LD) {
 598                 trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry,
 599                     tbe);
 600               } else {
 601                 if (presentOrAvail2(in_msg.LineAddress)) {
 602                   trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry,
 603                       tbe);
 604                 } else {
 605                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 606                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 607                       TBEs.lookup(victim));
 608                 }
 609               }
 610             } else {
 611               if (presentOrAvail2(in_msg.LineAddress)) {
 612                 if (presentOrAvailD0(in_msg.LineAddress)) {
 613                   if (in_msg.Type == RubyRequestType:LD) {
 614                     trigger(Event:C0_Load_L1miss, in_msg.LineAddress,
 615                         cache_entry, tbe);
 616                   } else {
 617                     trigger(Event:C0_Store_L1miss, in_msg.LineAddress,
 618                             cache_entry, tbe);
 619                   }
 620                 } else {
 621                   Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
 622                   trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
 623                           TBEs.lookup(victim));
 624                 }
 625               } else {
 626                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 627                 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 628                         TBEs.lookup(victim));
 629               }
 630             }
 631           }
 632         }
 633       }
 634     }
 635   }
 636
 637
 638   // ACTIONS
 639   action(ii_invIcache, "ii", desc="invalidate iCache") {
 640     if (L1Icache.isTagPresent(address)) {
 641       L1Icache.deallocate(address);
 642     }
 643   }
 644
 645   action(i0_invCluster, "i0", desc="invalidate cluster 0") {
 646     if (L1D0cache.isTagPresent(address)) {
 647       L1D0cache.deallocate(address);
 648     }
 649   }
 650
 651   action(i1_invCluster, "i1", desc="invalidate cluster 1") {
 652     if (L1D1cache.isTagPresent(address)) {
 653       L1D1cache.deallocate(address);
 654     }
 655   }
 656
 657   action(ib_invBothClusters, "ib", desc="invalidate both clusters") {
 658     if (L1D0cache.isTagPresent(address)) {
 659       L1D0cache.deallocate(address);
 660     }
 661     if (L1D1cache.isTagPresent(address)) {
 662       L1D1cache.deallocate(address);
 663     }
 664   }
 665
 666   action(i2_invL2, "i2", desc="invalidate L2") {
 667     if(is_valid(cache_entry)) {
 668         L2cache.deallocate(address);
 669     }
 670     unset_cache_entry();
 671   }
 672
 673   action(mru_setMRU, "mru", desc="Update LRU state") {
 674     L2cache.setMRU(address);
 675   }
 676
 677   action(mruD1_setD1cacheMRU, "mruD1", desc="Update LRU state") {
 678     L1D1cache.setMRU(address);
 679   }
 680
 681   action(mruD0_setD0cacheMRU, "mruD0", desc="Update LRU state") {
 682     L1D0cache.setMRU(address);
 683   }
 684
 685   action(mruI_setIcacheMRU, "mruI", desc="Update LRU state") {
 686     L1Icache.setMRU(address);
 687   }
 688
 689   action(n_issueRdBlk, "n", desc="Issue RdBlk") {
 690     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 691       out_msg.addr := address;
 692       out_msg.Type := CoherenceRequestType:RdBlk;
 693       out_msg.Requestor := machineID;
 694       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 695       DPRINTF(RubySlicc,"%s\n",out_msg.Destination);
 696       out_msg.MessageSize := MessageSizeType:Request_Control;
 697       out_msg.InitialRequestTime := curCycle();
 698     }
 699   }
 700
 701   action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") {
 702     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 703       out_msg.addr := address;
 704       out_msg.Type := CoherenceRequestType:RdBlkM;
 705       out_msg.Requestor := machineID;
 706       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 707       out_msg.MessageSize := MessageSizeType:Request_Control;
 708       out_msg.InitialRequestTime := curCycle();
 709     }
 710   }
 711
 712   action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
 713     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 714       out_msg.addr := address;
 715       out_msg.Type := CoherenceRequestType:RdBlkS;
 716       out_msg.Requestor := machineID;
 717       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 718       out_msg.MessageSize := MessageSizeType:Request_Control;
 719       out_msg.InitialRequestTime := curCycle();
 720     }
 721   }
 722
 723   action(vd_victim, "vd", desc="Victimize M/O L2 Data") {
 724     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 725       out_msg.addr := address;
 726       out_msg.Requestor := machineID;
 727       assert(is_valid(cache_entry));
 728       out_msg.DataBlk := cache_entry.DataBlk;
 729       assert(cache_entry.Dirty);
 730       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 731       out_msg.MessageSize := MessageSizeType:Request_Control;
 732       out_msg.Type := CoherenceRequestType:VicDirty;
 733       out_msg.InitialRequestTime := curCycle();
 734       if (cache_entry.CacheState == State:O) {
 735         out_msg.Shared := true;
 736       } else {
 737         out_msg.Shared := false;
 738       }
 739     }
 740   }
 741
 742   action(vc_victim, "vc", desc="Victimize E/S L2 Data") {
 743     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 744       out_msg.addr := address;
 745       out_msg.Requestor := machineID;
 746       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
 747       out_msg.MessageSize := MessageSizeType:Request_Control;
 748       out_msg.Type := CoherenceRequestType:VicClean;
 749       out_msg.InitialRequestTime := curCycle();
 750       if (cache_entry.CacheState == State:S) {
 751         out_msg.Shared := true;
 752       } else {
 753         out_msg.Shared := false;
 754       }
 755     }
 756   }
 757
 758   action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
 759     if (L1D0cache.isTagPresent(address) == false) {
 760       L1D0cache.allocateVoid(address, new Entry);
 761     }
 762   }
 763
 764   action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
 765     if (L1D1cache.isTagPresent(address) == false) {
 766       L1D1cache.allocateVoid(address, new Entry);
 767     }
 768   }
 769
 770   action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
 771     if (L1Icache.isTagPresent(address) == false) {
 772       L1Icache.allocateVoid(address, new Entry);
 773     }
 774   }
 775
 776   action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
 777     if (is_invalid(cache_entry)) {
 778       set_cache_entry(L2cache.allocate(address, new Entry));
 779     }
 780   }
 781
 782   action(t_allocateTBE, "t", desc="allocate TBE Entry") {
 783     check_allocate(TBEs);
 784     assert(is_valid(cache_entry));
 785     TBEs.allocate(address);
 786     set_tbe(TBEs.lookup(address));
 787     tbe.DataBlk := cache_entry.DataBlk;  // Data only used for WBs
 788     tbe.Dirty := cache_entry.Dirty;
 789     tbe.Shared := false;
 790   }
 791
 792   action(d_deallocateTBE, "d", desc="Deallocate TBE") {
 793     TBEs.deallocate(address);
 794     unset_tbe();
 795   }
 796
 797   action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
 798     mandatoryQueue_in.dequeue(clockEdge());
 799   }
 800
 801   action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
 802     responseToCore_in.dequeue(clockEdge());
 803   }
 804
 805   action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") {
 806     triggerQueue_in.dequeue(clockEdge());
 807   }
 808
 809   action(pp_popProbeQueue, "pp", desc="pop probe queue") {
 810     probeNetwork_in.dequeue(clockEdge());
 811   }
 812
 813   action(il0_loadDone, "il0", desc="Cluster 0 i load done") {
 814     Entry entry := getICacheEntry(address);
 815     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 816     assert(is_valid(entry));
 817     // L2 supplies data (functional accesses only look in L2, ok because L1
 818     //                   writes through to L2)
 819     sequencer.readCallback(address,
 820                            l2entry.DataBlk,
 821                            true,
 822                            testAndClearLocalHit(entry));
 823   }
 824
 825   action(il1_loadDone, "il1", desc="Cluster 1 i load done") {
 826     Entry entry := getICacheEntry(address);
 827     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 828     assert(is_valid(entry));
 829     // L2 supplies data (functional accesses only look in L2, ok because L1
 830     //                   writes through to L2)
 831     sequencer1.readCallback(address,
 832                             l2entry.DataBlk,
 833                             true,
 834                             testAndClearLocalHit(entry));
 835   }
 836
 837   action(l0_loadDone, "l0", desc="Cluster 0 load done") {
 838     Entry entry := getL1CacheEntry(address, 0);
 839     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 840     assert(is_valid(entry));
 841     // L2 supplies data (functional accesses only look in L2, ok because L1
 842     //                   writes through to L2)
 843     sequencer.readCallback(address,
 844                            l2entry.DataBlk,
 845                            true,
 846                            testAndClearLocalHit(entry));
 847   }
 848
 849   action(l1_loadDone, "l1", desc="Cluster 1 load done") {
 850     Entry entry := getL1CacheEntry(address, 1);
 851     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 852     assert(is_valid(entry));
 853     // L2 supplies data (functional accesses only look in L2, ok because L1
 854     //                   writes through to L2)
 855     sequencer1.readCallback(address,
 856                             l2entry.DataBlk,
 857                             true,
 858                             testAndClearLocalHit(entry));
 859   }
 860
 861   action(xl0_loadDone, "xl0", desc="Cluster 0 load done") {
 862     peek(responseToCore_in, ResponseMsg) {
 863       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 864               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 865       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 866       DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n", address, l2entry.DataBlk);
 867       // L2 supplies data (functional accesses only look in L2, ok because L1
 868       //                   writes through to L2)
 869       sequencer.readCallback(address,
 870                              l2entry.DataBlk,
 871                              false,
 872                              machineIDToMachineType(in_msg.Sender),
 873                              in_msg.InitialRequestTime,
 874                              in_msg.ForwardRequestTime,
 875                              in_msg.ProbeRequestStartTime);
 876     }
 877   }
 878
 879   action(xl1_loadDone, "xl1", desc="Cluster 1 load done") {
 880    peek(responseToCore_in, ResponseMsg) {
 881       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 882               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 883       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 884       // L2 supplies data (functional accesses only look in L2, ok because L1
 885       //                   writes through to L2)
 886       sequencer1.readCallback(address,
 887                               l2entry.DataBlk,
 888                               false,
 889                               machineIDToMachineType(in_msg.Sender),
 890                               in_msg.InitialRequestTime,
 891                               in_msg.ForwardRequestTime,
 892                               in_msg.ProbeRequestStartTime);
 893     }
 894   }
 895
 896   action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") {
 897     peek(responseToCore_in, ResponseMsg) {
 898       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 899               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 900       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 901       // L2 supplies data (functional accesses only look in L2, ok because L1
 902       //                   writes through to L2)
 903       sequencer.readCallback(address,
 904                              l2entry.DataBlk,
 905                              false,
 906                              machineIDToMachineType(in_msg.Sender),
 907                              in_msg.InitialRequestTime,
 908                              in_msg.ForwardRequestTime,
 909                              in_msg.ProbeRequestStartTime);
 910     }
 911   }
 912
 913   action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") {
 914     peek(responseToCore_in, ResponseMsg) {
 915       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 916               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 917       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 918       // L2 supplies data (functional accesses only look in L2, ok because L1
 919       //                   writes through to L2)
 920       sequencer1.readCallback(address,
 921                               l2entry.DataBlk,
 922                               false,
 923                               machineIDToMachineType(in_msg.Sender),
 924                               in_msg.InitialRequestTime,
 925                               in_msg.ForwardRequestTime,
 926                               in_msg.ProbeRequestStartTime);
 927     }
 928   }
 929
 930   action(s0_storeDone, "s0", desc="Cluster 0 store done") {
 931     Entry entry := getL1CacheEntry(address, 0);
 932     assert(is_valid(entry));
 933     assert(is_valid(cache_entry));
 934     sequencer.writeCallback(address,
 935                             cache_entry.DataBlk,
 936                             true,
 937                             testAndClearLocalHit(entry));
 938     cache_entry.Dirty := true;
 939     entry.DataBlk := cache_entry.DataBlk;
 940     entry.Dirty := true;
 941     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 942   }
 943
 944   action(s1_storeDone, "s1", desc="Cluster 1 store done") {
 945     Entry entry := getL1CacheEntry(address, 1);
 946     assert(is_valid(entry));
 947     assert(is_valid(cache_entry));
 948     sequencer1.writeCallback(address,
 949                              cache_entry.DataBlk,
 950                              true,
 951                              testAndClearLocalHit(entry));
 952     cache_entry.Dirty := true;
 953     entry.Dirty := true;
 954     entry.DataBlk := cache_entry.DataBlk;
 955     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 956   }
 957
 958   action(xs0_storeDone, "xs0", desc="Cluster 0 store done") {
 959     peek(responseToCore_in, ResponseMsg) {
 960       Entry entry := getL1CacheEntry(address, 0);
 961       assert(is_valid(entry));
 962       assert(is_valid(cache_entry));
 963       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 964              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 965       sequencer.writeCallback(address,
 966                               cache_entry.DataBlk,
 967                               false,
 968                               machineIDToMachineType(in_msg.Sender),
 969                               in_msg.InitialRequestTime,
 970                               in_msg.ForwardRequestTime,
 971                               in_msg.ProbeRequestStartTime);
 972       cache_entry.Dirty := true;
 973       entry.Dirty := true;
 974       entry.DataBlk := cache_entry.DataBlk;
 975       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 976     }
 977   }
 978
 979   action(xs1_storeDone, "xs1", desc="Cluster 1 store done") {
 980     peek(responseToCore_in, ResponseMsg) {
 981       Entry entry := getL1CacheEntry(address, 1);
 982       assert(is_valid(entry));
 983       assert(is_valid(cache_entry));
 984       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 985              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 986       sequencer1.writeCallback(address,
 987                                cache_entry.DataBlk,
 988                                false,
 989                                machineIDToMachineType(in_msg.Sender),
 990                                in_msg.InitialRequestTime,
 991                                in_msg.ForwardRequestTime,
 992                                in_msg.ProbeRequestStartTime);
 993       cache_entry.Dirty := true;
 994       entry.Dirty := true;
 995       entry.DataBlk := cache_entry.DataBlk;
 996       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 997     }
 998   }
 999
1000   action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") {
1001     if (send_evictions) {
1002       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1003       sequencer.evictionCallback(address);
1004     }
1005   }
1006
1007   action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") {
1008     if (send_evictions) {
1009       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1010       sequencer1.evictionCallback(address);
1011     }
1012   }
1013
1014   action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") {
1015     Entry entry := getICacheEntry(address);
1016     assert(is_valid(entry));
1017     assert(is_valid(cache_entry));
1018     entry.Dirty := cache_entry.Dirty;
1019     entry.DataBlk := cache_entry.DataBlk;
1020     entry.FromL2 := true;
1021   }
1022
1023   action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") {
1024     Entry entry := getL1CacheEntry(address, 0);
1025     assert(is_valid(entry));
1026     assert(is_valid(cache_entry));
1027     entry.Dirty := cache_entry.Dirty;
1028     entry.DataBlk := cache_entry.DataBlk;
1029     entry.FromL2 := true;
1030   }
1031
1032   action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") {
1033     Entry entry := getL1CacheEntry(address, 1);
1034     assert(is_valid(entry));
1035     assert(is_valid(cache_entry));
1036     entry.Dirty := cache_entry.Dirty;
1037     entry.DataBlk := cache_entry.DataBlk;
1038     entry.FromL2 := true;
1039   }
1040
1041   action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") {
1042     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1043       out_msg.addr := address;
1044       out_msg.Type := TriggerType:L2_to_L1;
1045       out_msg.Dest := CacheId:L1I;
1046     }
1047   }
1048
1049   action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") {
1050     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1051       out_msg.addr := address;
1052       out_msg.Type := TriggerType:L2_to_L1;
1053       out_msg.Dest := CacheId:L1D0;
1054     }
1055   }
1056
1057   action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") {
1058     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1059       out_msg.addr := address;
1060       out_msg.Type := TriggerType:L2_to_L1;
1061       out_msg.Dest := CacheId:L1D1;
1062     }
1063   }
1064
1065   action(wi_writeIcache, "wi", desc="write data to icache (and l2)") {
1066     peek(responseToCore_in, ResponseMsg) {
1067       Entry entry := getICacheEntry(address);
1068       assert(is_valid(entry));
1069       assert(is_valid(cache_entry));
1070       entry.DataBlk := in_msg.DataBlk;
1071       entry.Dirty := in_msg.Dirty;
1072       cache_entry.DataBlk := in_msg.DataBlk;
1073       cache_entry.Dirty := in_msg.Dirty;
1074     }
1075   }
1076
1077   action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") {
1078     peek(responseToCore_in, ResponseMsg) {
1079       Entry entry := getL1CacheEntry(address, 0);
1080       assert(is_valid(entry));
1081       assert(is_valid(cache_entry));
1082       DPRINTF(ProtocolTrace, "CP writeD0: address %s, data: %s\n", address, in_msg.DataBlk);
1083       entry.DataBlk := in_msg.DataBlk;
1084       entry.Dirty := in_msg.Dirty;
1085       cache_entry.DataBlk := in_msg.DataBlk;
1086       cache_entry.Dirty := in_msg.Dirty;
1087     }
1088   }
1089
1090   action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") {
1091     peek(responseToCore_in, ResponseMsg) {
1092       Entry entry := getL1CacheEntry(address, 1);
1093       assert(is_valid(entry));
1094       assert(is_valid(cache_entry));
1095       entry.DataBlk := in_msg.DataBlk;
1096       entry.Dirty := in_msg.Dirty;
1097       cache_entry.DataBlk := in_msg.DataBlk;
1098       cache_entry.Dirty := in_msg.Dirty;
1099     }
1100   }
1101
1102   action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
1103     peek(responseToCore_in, ResponseMsg) {
1104       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1105         out_msg.addr := address;
1106         out_msg.Type := CoherenceResponseType:StaleNotif;
1107         out_msg.Sender := machineID;
1108         out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1109         out_msg.MessageSize := MessageSizeType:Response_Control;
1110         DPRINTF(RubySlicc, "%s\n", out_msg);
1111       }
1112     }
1113   }
1114
1115   action(wb_data, "wb", desc="write back data") {
1116     peek(responseToCore_in, ResponseMsg) {
1117       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1118         out_msg.addr := address;
1119         out_msg.Type := CoherenceResponseType:CPUData;
1120         out_msg.Sender := machineID;
1121         out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1122         out_msg.DataBlk := tbe.DataBlk;
1123         out_msg.Dirty := tbe.Dirty;
1124         if (tbe.Shared) {
1125           out_msg.NbReqShared := true;
1126         } else {
1127           out_msg.NbReqShared := false;
1128         }
1129         out_msg.State := CoherenceState:Shared; // faux info
1130         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1131         DPRINTF(RubySlicc, "%s\n", out_msg);
1132       }
1133     }
1134   }
1135
1136   action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
1137     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1138       out_msg.addr := address;
1139       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1140       out_msg.Sender := machineID;
1141       // will this always be ok? probably not for multisocket
1142       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1143       out_msg.Dirty := false;
1144       out_msg.Hit := false;
1145       out_msg.Ntsl := true;
1146       out_msg.State := CoherenceState:NA;
1147       out_msg.MessageSize := MessageSizeType:Response_Control;
1148     }
1149   }
1150
1151   action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
1152     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1153       out_msg.addr := address;
1154       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1155       out_msg.Sender := machineID;
1156       // will this always be ok? probably not for multisocket
1157       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1158       out_msg.Dirty := false;
1159       out_msg.Ntsl := true;
1160       out_msg.Hit := false;
1161       out_msg.State := CoherenceState:NA;
1162       out_msg.MessageSize := MessageSizeType:Response_Control;
1163     }
1164   }
1165
1166   action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") {
1167     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1168       out_msg.addr := address;
1169       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1170       out_msg.Sender := machineID;
1171       // will this always be ok? probably not for multisocket
1172       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1173       assert(addressInCore(address) || is_valid(tbe));
1174       out_msg.Dirty := false;  // only true if sending back data i think
1175       out_msg.Hit := true;
1176       out_msg.Ntsl := false;
1177       out_msg.State := CoherenceState:NA;
1178       out_msg.MessageSize := MessageSizeType:Response_Control;
1179     }
1180   }
1181
1182   action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") {
1183     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1184       out_msg.addr := address;
1185       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1186       out_msg.Sender := machineID;
1187       // will this always be ok? probably not for multisocket
1188       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1189       if (addressInCore(address)) {
1190         out_msg.Hit := true;
1191       } else {
1192         out_msg.Hit := false;
1193       }
1194       out_msg.Dirty := false;  // not sending back data, so def. not dirty
1195       out_msg.Ntsl := false;
1196       out_msg.State := CoherenceState:NA;
1197       out_msg.MessageSize := MessageSizeType:Response_Control;
1198     }
1199   }
1200
1201   action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
1202     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1203       assert(is_valid(cache_entry));
1204       out_msg.addr := address;
1205       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1206       out_msg.Sender := machineID;
1207       // will this always be ok? probably not for multisocket
1208       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1209       out_msg.DataBlk := cache_entry.DataBlk;
1210       assert(cache_entry.Dirty);
1211       out_msg.Dirty := true;
1212       out_msg.Hit := true;
1213       out_msg.State := CoherenceState:NA;
1214       out_msg.MessageSize := MessageSizeType:Response_Data;
1215     }
1216   }
1217
1218   action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
1219     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1220       assert(is_valid(cache_entry));
1221       out_msg.addr := address;
1222       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1223       out_msg.Sender := machineID;
1224       // will this always be ok? probably not for multisocket
1225       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1226       out_msg.DataBlk := cache_entry.DataBlk;
1227       assert(cache_entry.Dirty);
1228       out_msg.Dirty := true;
1229       out_msg.Hit := true;
1230       out_msg.State := CoherenceState:NA;
1231       out_msg.MessageSize := MessageSizeType:Response_Data;
1232     }
1233   }
1234
1235   action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
1236     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1237       assert(is_valid(tbe));
1238       out_msg.addr := address;
1239       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1240       out_msg.Sender := machineID;
1241       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1242       out_msg.DataBlk := tbe.DataBlk;
1243       assert(tbe.Dirty);
1244       out_msg.Dirty := true;
1245       out_msg.Hit := true;
1246       out_msg.State := CoherenceState:NA;
1247       out_msg.MessageSize := MessageSizeType:Response_Data;
1248     }
1249   }
1250
1251   action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") {
1252     assert(is_valid(tbe));
1253     tbe.Shared := true;
1254   }
1255
1256   action(uu_sendUnblock, "uu", desc="state changed, unblock") {
1257     enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
1258       out_msg.addr := address;
1259       out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1260       out_msg.MessageSize := MessageSizeType:Unblock_Control;
1261       DPRINTF(RubySlicc, "%s\n", out_msg);
1262     }
1263   }
1264
1265   action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
1266     ++L2cache.demand_misses;
1267   }
1268
1269   action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
1270     ++L1D0cache.demand_misses;
1271   }
1272
1273   action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
1274     ++L1D1cache.demand_misses;
1275   }
1276
1277   action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
1278     ++L1Icache.demand_misses;
1279   }
1280
1281   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
1282     probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1283   }
1284
1285   action(xx_recycleResponseQueue, "xx", desc="recycle response queue") {
1286     responseToCore_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1287   }
1288
1289   action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
1290     mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1291   }
1292
1293   // END ACTIONS
1294
1295   // BEGIN TRANSITIONS
1296
1297   // transitions from base
1298   transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} {
1299     // track misses, if implemented
1300     // since in I state, L2 miss as well
1301     l2m_profileMiss;
1302     l10m_profileMiss;
1303     a0_allocateL1D;
1304     a2_allocateL2;
1305     i1_invCluster;
1306     ii_invIcache;
1307     n_issueRdBlk;
1308     p_popMandatoryQueue;
1309   }
1310
1311   transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} {
1312     // track misses, if implemented
1313     // since in I state, L2 miss as well
1314     l2m_profileMiss;
1315     l11m_profileMiss;
1316     a1_allocateL1D;
1317     a2_allocateL2;
1318     i0_invCluster;
1319     ii_invIcache;
1320     n_issueRdBlk;
1321     p_popMandatoryQueue;
1322   }
1323
1324   transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead,L2TagArrayRead} {
1325     // track misses, if implemented
1326     // L2 miss as well
1327     l2m_profileMiss;
1328     l1im_profileMiss;
1329     ai_allocateL1I;
1330     a2_allocateL2;
1331     ib_invBothClusters;
1332     nS_issueRdBlkS;
1333     p_popMandatoryQueue;
1334   }
1335
1336   transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1337     // track misses, if implemented
1338     // L2 miss as well
1339     l2m_profileMiss;
1340     l1im_profileMiss;
1341     ai_allocateL1I;
1342     a2_allocateL2;
1343     ib_invBothClusters;
1344     nS_issueRdBlkS;
1345     p_popMandatoryQueue;
1346   }
1347
1348   transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1349     l2m_profileMiss;
1350     l10m_profileMiss;
1351     a0_allocateL1D;
1352     a2_allocateL2;
1353     i1_invCluster;
1354     ii_invIcache;
1355     nM_issueRdBlkM;
1356     p_popMandatoryQueue;
1357   }
1358
1359   transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} {
1360     l2m_profileMiss;
1361     l11m_profileMiss;
1362     a1_allocateL1D;
1363     a2_allocateL2;
1364     i0_invCluster;
1365     ii_invIcache;
1366     nM_issueRdBlkM;
1367     p_popMandatoryQueue;
1368   }
1369
1370   transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1371     l10m_profileMiss;
1372     a0_allocateL1D;
1373     f0_L2ToL1;
1374     mru_setMRU;
1375     p_popMandatoryQueue;
1376   }
1377
1378   transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1379     l11m_profileMiss;
1380     a1_allocateL1D;
1381     f1_L2ToL1;
1382     mru_setMRU;
1383     p_popMandatoryQueue;
1384   }
1385
1386   transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1387     l1im_profileMiss;
1388     ai_allocateL1I;
1389     fi_L2ToL1;
1390     mru_setMRU;
1391     p_popMandatoryQueue;
1392   }
1393
1394   transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1395     l1im_profileMiss;
1396     ai_allocateL1I;
1397     fi_L2ToL1;
1398     mru_setMRU;
1399     p_popMandatoryQueue;
1400   }
1401
1402   transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1403     l2m_profileMiss;
1404     l10m_profileMiss;
1405     a0_allocateL1D;
1406     mruD0_setD0cacheMRU;
1407     i1_invCluster;
1408     ii_invIcache;
1409     nM_issueRdBlkM;
1410     p_popMandatoryQueue;
1411   }
1412
1413   transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1414     l2m_profileMiss;
1415     l11m_profileMiss;
1416     a1_allocateL1D;
1417     mruD1_setD1cacheMRU;
1418     i0_invCluster;
1419     ii_invIcache;
1420     nM_issueRdBlkM;
1421     p_popMandatoryQueue;
1422   }
1423
1424   transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1425     a0_allocateL1D;
1426     l10m_profileMiss;
1427     f0_L2ToL1;
1428     mru_setMRU;
1429     p_popMandatoryQueue;
1430   }
1431
1432   transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1433     l11m_profileMiss;
1434     a1_allocateL1D;
1435     f1_L2ToL1;
1436     mru_setMRU;
1437     p_popMandatoryQueue;
1438   }
1439
1440   transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L1ITagArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1441     l1im_profileMiss;
1442     i2_invL2;
1443     ai_allocateL1I;
1444     a2_allocateL2;
1445     ib_invBothClusters;
1446     nS_issueRdBlkS;
1447     p_popMandatoryQueue;
1448   }
1449
1450   transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1451     l1im_profileMiss;
1452     i2_invL2;
1453     ai_allocateL1I;
1454     a2_allocateL2;
1455     ib_invBothClusters;
1456     nS_issueRdBlkS;
1457     p_popMandatoryQueue;
1458   }
1459
1460   // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW
1461   transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1462     a0_allocateL1D;
1463     i1_invCluster;
1464     s0_storeDone;   // instantaneous L1/L2 dirty - no writethrough delay
1465     mruD0_setD0cacheMRU;
1466     mru_setMRU;
1467     p_popMandatoryQueue;
1468   }
1469
1470   transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1471     a1_allocateL1D;
1472     i0_invCluster;
1473     s1_storeDone;
1474     mruD1_setD1cacheMRU;
1475     mru_setMRU;
1476     p_popMandatoryQueue;
1477   }
1478
1479   transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1480     l10m_profileMiss;
1481     a0_allocateL1D;
1482     f0_L2ToL1;
1483     mru_setMRU;
1484     p_popMandatoryQueue;
1485   }
1486
1487   transition(E0, C1_Load_L1miss, E0_Es) {L1D1TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1488     l11m_profileMiss;
1489     a1_allocateL1D;
1490     f1_L2ToL1;
1491     mru_setMRU;
1492     p_popMandatoryQueue;
1493   }
1494
1495   transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1496     l2m_profileMiss; // permissions miss, still issue RdBlkS
1497     l1im_profileMiss;
1498     i2_invL2;
1499     ai_allocateL1I;
1500     a2_allocateL2;
1501     i0_invCluster;
1502     nS_issueRdBlkS;
1503     p_popMandatoryQueue;
1504   }
1505
1506   transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} {
1507     l2m_profileMiss; // permissions miss, still issue RdBlkS
1508     l1im_profileMiss;
1509     i2_invL2;
1510     ai_allocateL1I;
1511     a2_allocateL2;
1512     i0_invCluster;
1513     nS_issueRdBlkS;
1514     p_popMandatoryQueue;
1515   }
1516
1517   transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1518     a0_allocateL1D;
1519     s0_storeDone;
1520     mruD0_setD0cacheMRU;
1521     mru_setMRU;
1522     p_popMandatoryQueue;
1523   }
1524
1525   transition(E0, C1_Store_L1miss, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1526     l11m_profileMiss;
1527     a1_allocateL1D;
1528     i0_invCluster;
1529     s1_storeDone;
1530     mru_setMRU;
1531     p_popMandatoryQueue;
1532   }
1533
1534   transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1535      l11m_profileMiss;
1536     a1_allocateL1D;
1537     f1_L2ToL1;
1538     mru_setMRU;
1539     p_popMandatoryQueue;
1540   }
1541
1542   transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1543     l11m_profileMiss;
1544     a0_allocateL1D;
1545     f0_L2ToL1;
1546     mru_setMRU;
1547     p_popMandatoryQueue;
1548   }
1549
1550   transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead,  L1ITagArrayRead} {
1551     l2m_profileMiss; // permissions miss, still issue RdBlkS
1552     l1im_profileMiss;
1553     i2_invL2;
1554     ai_allocateL1I;
1555     a2_allocateL2;
1556     i1_invCluster;
1557     nS_issueRdBlkS;
1558     p_popMandatoryQueue;
1559   }
1560
1561   transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1562     l2m_profileMiss; // permissions miss, still issue RdBlkS
1563     l1im_profileMiss;
1564     i2_invL2;
1565     ai_allocateL1I;
1566     a2_allocateL2;
1567     i1_invCluster;
1568     nS_issueRdBlkS;
1569     p_popMandatoryQueue;
1570   }
1571
1572   transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite} {
1573     a1_allocateL1D;
1574     s1_storeDone;
1575     mruD1_setD1cacheMRU;
1576     mru_setMRU;
1577     p_popMandatoryQueue;
1578   }
1579
1580   transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite} {
1581      l10m_profileMiss;
1582     a0_allocateL1D;
1583     i1_invCluster;
1584     s0_storeDone;
1585     mru_setMRU;
1586     p_popMandatoryQueue;
1587   }
1588
1589   transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead,L2TagArrayRead} {
1590     l2m_profileMiss; // permissions miss, still issue CtoD
1591     l10m_profileMiss;
1592     a0_allocateL1D;
1593     mruD0_setD0cacheMRU;
1594     i1_invCluster;
1595     ii_invIcache;
1596     nM_issueRdBlkM;
1597     p_popMandatoryQueue;
1598   }
1599
1600   transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1601     l2m_profileMiss; // permissions miss, still issue RdBlkS
1602      l11m_profileMiss;
1603     a1_allocateL1D;
1604     mruD1_setD1cacheMRU;
1605     i0_invCluster;
1606     ii_invIcache;
1607     nM_issueRdBlkM;
1608     p_popMandatoryQueue;
1609   }
1610
1611   transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1612     l10m_profileMiss;
1613     a0_allocateL1D;
1614     f0_L2ToL1;
1615     mru_setMRU;
1616     p_popMandatoryQueue;
1617   }
1618
1619   transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1620      l11m_profileMiss;
1621     a1_allocateL1D;
1622     f1_L2ToL1;
1623     mru_setMRU;
1624     p_popMandatoryQueue;
1625   }
1626
1627   transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1628     l10m_profileMiss;
1629     a0_allocateL1D;
1630     f0_L2ToL1;
1631     mru_setMRU;
1632     p_popMandatoryQueue;
1633   }
1634
1635   transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1636     l11m_profileMiss;
1637     a1_allocateL1D;
1638     f1_L2ToL1;
1639     mru_setMRU;
1640     p_popMandatoryQueue;
1641   }
1642
1643   transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead, L2DataArrayRead, L2TagArrayRead} {
1644     l2m_profileMiss;  // permissions miss
1645     l1im_profileMiss;
1646     ai_allocateL1I;
1647     t_allocateTBE;
1648     ib_invBothClusters;
1649     vd_victim;
1650 //    i2_invL2;
1651     p_popMandatoryQueue;
1652   }
1653
1654   transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead } {
1655     l2m_profileMiss;  // permissions miss
1656      l1im_profileMiss;
1657     ai_allocateL1I;
1658     t_allocateTBE;
1659     ib_invBothClusters;
1660     vd_victim;
1661 //    i2_invL2;
1662     p_popMandatoryQueue;
1663   }
1664
1665   transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1666     a0_allocateL1D;
1667     i1_invCluster;
1668     s0_storeDone;
1669     mruD0_setD0cacheMRU;
1670     mru_setMRU;
1671     p_popMandatoryQueue;
1672   }
1673
1674   transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1675     a1_allocateL1D;
1676     i0_invCluster;
1677     s1_storeDone;
1678     mruD1_setD1cacheMRU;
1679     mru_setMRU;
1680     p_popMandatoryQueue;
1681   }
1682
1683   transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1684      l10m_profileMiss;
1685     a0_allocateL1D;
1686     f0_L2ToL1;
1687     mru_setMRU;
1688     p_popMandatoryQueue;
1689   }
1690
1691   transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D0TagArrayRead} {
1692     l11m_profileMiss;
1693     a1_allocateL1D;
1694     f1_L2ToL1;
1695     mru_setMRU;
1696     p_popMandatoryQueue;
1697   }
1698
1699   transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead,L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} {
1700     a0_allocateL1D;
1701     s0_storeDone;
1702     mruD0_setD0cacheMRU;
1703     mru_setMRU;
1704     p_popMandatoryQueue;
1705   }
1706
1707   transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1708     a1_allocateL1D;
1709     i0_invCluster;
1710     s1_storeDone;
1711     mruD1_setD1cacheMRU;
1712     mru_setMRU;
1713     p_popMandatoryQueue;
1714   }
1715
1716   transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1717     l10m_profileMiss;
1718     a0_allocateL1D;
1719     f0_L2ToL1;
1720     mru_setMRU;
1721     p_popMandatoryQueue;
1722   }
1723
1724   transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1725     a1_allocateL1D;
1726     f1_L2ToL1;
1727     mru_setMRU;
1728     p_popMandatoryQueue;
1729   }
1730
1731   transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1732     a0_allocateL1D;
1733     i1_invCluster;
1734     s0_storeDone;
1735     mruD0_setD0cacheMRU;
1736     mru_setMRU;
1737     p_popMandatoryQueue;
1738   }
1739
1740   transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayWrite} {
1741     a1_allocateL1D;
1742     s1_storeDone;
1743     mruD1_setD1cacheMRU;
1744     mru_setMRU;
1745     p_popMandatoryQueue;
1746   }
1747
1748   // end transitions from base
1749
1750   // Begin simple hit transitions
1751   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es,
1752           Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} {
1753     // track hits, if implemented
1754     l0_loadDone;
1755     mruD0_setD0cacheMRU;
1756     p_popMandatoryQueue;
1757   }
1758
1759   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es,
1760           Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} {
1761     // track hits, if implemented
1762     l1_loadDone;
1763     mruD1_setD1cacheMRU;
1764     p_popMandatoryQueue;
1765   }
1766
1767   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} {
1768     // track hits, if implemented
1769     il0_loadDone;
1770     mruI_setIcacheMRU;
1771     p_popMandatoryQueue;
1772   }
1773
1774   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} {
1775     // track hits, if implemented
1776     il1_loadDone;
1777     mruI_setIcacheMRU;
1778     p_popMandatoryQueue;
1779   }
1780
1781   // end simple hit transitions
1782
1783   // Transitions from transient states
1784
1785   // recycles
1786   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1787           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1788           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} {
1789     zz_recycleMandatoryQueue;
1790   }
1791
1792   transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1,
1793           O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} {
1794     zz_recycleMandatoryQueue;
1795   }
1796
1797   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1798           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1799           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} {
1800     zz_recycleMandatoryQueue;
1801   }
1802
1803   transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0,
1804           O_M0, S0, S1, I_C, S0_C, S1_C, S_C},  C1_Load_L1miss) {} {
1805     zz_recycleMandatoryQueue;
1806   }
1807
1808   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} {
1809     zz_recycleMandatoryQueue;
1810   }
1811
1812   transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES,
1813           IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F,
1814           O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F,
1815           E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C,
1816           S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} {
1817     zz_recycleMandatoryQueue;
1818   }
1819
1820   transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1,
1821           Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms,
1822           M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} {
1823     zz_recycleMandatoryQueue;
1824   }
1825
1826   transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0,
1827           Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F,
1828           M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} {
1829     zz_recycleMandatoryQueue;
1830   }
1831
1832   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1833           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} {
1834     zz_recycleMandatoryQueue;
1835   }
1836
1837   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1838           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1,
1839           O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F,
1840           M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} {
1841     zz_recycleMandatoryQueue;
1842   }
1843
1844   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1845           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1846           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} {
1847     zz_recycleMandatoryQueue;
1848   }
1849
1850   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1851           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1852           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} {
1853     zz_recycleMandatoryQueue;
1854   }
1855
1856   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} {
1857     zz_recycleMandatoryQueue;
1858   }
1859
1860   transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} {
1861     zz_recycleMandatoryQueue;
1862   }
1863
1864   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS,
1865           PrbInvData, PrbInv, PrbShrData}) {} {
1866     yy_recycleProbeQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1867   }
1868
1869   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} {
1870     xx_recycleResponseQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1871   }
1872
1873   transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} {
1874     l10m_profileMiss;
1875     a0_allocateL1D;
1876     f0_L2ToL1;
1877     p_popMandatoryQueue;
1878   }
1879
1880   transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} {
1881     l10m_profileMiss;
1882     a0_allocateL1D;
1883     f0_L2ToL1;
1884     p_popMandatoryQueue;
1885   }
1886
1887   transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} {
1888     l10m_profileMiss;
1889     a0_allocateL1D;
1890     f0_L2ToL1;
1891     p_popMandatoryQueue;
1892   }
1893
1894   transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} {
1895     l10m_profileMiss;
1896     a0_allocateL1D;
1897     f0_L2ToL1;
1898     p_popMandatoryQueue;
1899   }
1900
1901   transition(I_M0, C1_Load_L1miss, I_M0Ms) {} {
1902     l2m_profileMiss;
1903     l11m_profileMiss;
1904     a1_allocateL1D;
1905     mru_setMRU;
1906     p_popMandatoryQueue;
1907   }
1908
1909   transition(I_M1, C0_Load_L1miss, I_M1Ms) {} {
1910     l2m_profileMiss;
1911     l10m_profileMiss;
1912     a0_allocateL1D;
1913     mru_setMRU;
1914     p_popMandatoryQueue;
1915   }
1916
1917   transition(I_M0, C1_Store_L1miss, I_M0M1) {} {
1918     l2m_profileMiss;
1919     l11m_profileMiss;
1920     a1_allocateL1D;
1921     mru_setMRU;
1922     p_popMandatoryQueue;
1923   }
1924
1925   transition(I_M1, C0_Store_L1miss, I_M1M0) {} {
1926     l2m_profileMiss;
1927     l10m_profileMiss;
1928     a0_allocateL1D;
1929     mru_setMRU;
1930     p_popMandatoryQueue;
1931   }
1932
1933   transition(I_E0S, C1_Load_L1miss, I_ES) {} {
1934     l2m_profileMiss;
1935     l11m_profileMiss;
1936     a1_allocateL1D;
1937     p_popMandatoryQueue;
1938   }
1939
1940   transition(I_E1S, C0_Load_L1miss, I_ES) {} {
1941     l2m_profileMiss;
1942     l10m_profileMiss;
1943     a0_allocateL1D;
1944     p_popMandatoryQueue;
1945   }
1946
1947   transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} {
1948     l11m_profileMiss;
1949     a1_allocateL1D;
1950     f1_L2ToL1;
1951     p_popMandatoryQueue;
1952   }
1953
1954   transition(S_F0, C1_Load_L1miss, S_F) {L2DataArrayRead} {
1955     l11m_profileMiss;
1956     a1_allocateL1D;
1957     f1_L2ToL1;
1958     p_popMandatoryQueue;
1959   }
1960
1961   transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} {
1962     l11m_profileMiss;
1963     a1_allocateL1D;
1964     f1_L2ToL1;
1965     p_popMandatoryQueue;
1966   }
1967
1968   transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) { L2DataArrayRead} {
1969     l11m_profileMiss;
1970     a1_allocateL1D;
1971     f1_L2ToL1;
1972     p_popMandatoryQueue;
1973   }
1974
1975   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} {
1976     i0_invCluster;
1977   }
1978
1979   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} {
1980     i1_invCluster;
1981   }
1982
1983   transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} {
1984     ii_invIcache;
1985   }
1986
1987   transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} {
1988     forward_eviction_to_cpu0;
1989     forward_eviction_to_cpu1;
1990     t_allocateTBE;
1991     vc_victim;
1992     ib_invBothClusters;
1993     i2_invL2;
1994     ii_invIcache;
1995   }
1996
1997   transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead, L1D1TagArrayRead} {
1998     forward_eviction_to_cpu0;
1999     forward_eviction_to_cpu1;
2000     t_allocateTBE;
2001     vd_victim;
2002     i2_invL2;
2003     ib_invBothClusters;  // nothing will happen for D0 on M1, vice versa
2004   }
2005
2006   transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2007     wi_writeIcache;
2008     xi0_loadDone;
2009     uu_sendUnblock;
2010     pr_popResponseQueue;
2011   }
2012
2013   transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2014     wi_writeIcache;
2015     xi1_loadDone;
2016     uu_sendUnblock;
2017     pr_popResponseQueue;
2018   }
2019
2020   transition(S0_C, NB_AckS, S_C) {L1D0DataArrayWrite,L2DataArrayWrite} {
2021     wi_writeIcache;
2022     xi0_loadDone;
2023     uu_sendUnblock;
2024     pr_popResponseQueue;
2025   }
2026
2027   transition(S1_C, NB_AckS, S_C) {L1D1DataArrayWrite, L2DataArrayWrite} {
2028     wi_writeIcache;
2029     xi1_loadDone;
2030     uu_sendUnblock;
2031     pr_popResponseQueue;
2032   }
2033
2034   transition(I_M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2035     w0_writeDcache;
2036     xs0_storeDone;
2037     uu_sendUnblock;
2038     pr_popResponseQueue;
2039   }
2040
2041   transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2042     w1_writeDcache;
2043     xs1_storeDone;
2044     uu_sendUnblock;
2045     pr_popResponseQueue;
2046   }
2047
2048   // THESE MO->M1 should not be instantaneous but oh well for now.
2049   transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2050     w0_writeDcache;
2051     xs0_storeDone;
2052     uu_sendUnblock;
2053     i0_invCluster;
2054     s1_storeDone;
2055     pr_popResponseQueue;
2056   }
2057
2058   transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2059     w1_writeDcache;
2060     xs1_storeDone;
2061     uu_sendUnblock;
2062     i1_invCluster;
2063     s0_storeDone;
2064     pr_popResponseQueue;
2065   }
2066
2067   // Above shoudl be more like this, which has some latency to xfer to L1
2068   transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} {
2069     w0_writeDcache;
2070     xs0_storeDone;
2071     uu_sendUnblock;
2072     f1_L2ToL1;
2073     pr_popResponseQueue;
2074   }
2075
2076   transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite, L2DataArrayWrite} {
2077     w1_writeDcache;
2078     xs1_storeDone;
2079     uu_sendUnblock;
2080     f0_L2ToL1;
2081     pr_popResponseQueue;
2082   }
2083
2084   transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2085     w0_writeDcache;
2086     xl0_loadDone;
2087     uu_sendUnblock;
2088     pr_popResponseQueue;
2089   }
2090
2091   transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2092     w1_writeDcache;
2093     xl1_loadDone;
2094     uu_sendUnblock;
2095     pr_popResponseQueue;
2096   }
2097
2098   transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } {
2099     w0_writeDcache;
2100     xl0_loadDone;
2101     w1_writeDcache;
2102     xl1_loadDone;
2103     uu_sendUnblock;
2104     pr_popResponseQueue;
2105   }
2106
2107   transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2108     w0_writeDcache;
2109     xl0_loadDone;
2110     uu_sendUnblock;
2111     pr_popResponseQueue;
2112   }
2113
2114   transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2115     w1_writeDcache;
2116     xl1_loadDone;
2117     uu_sendUnblock;
2118     pr_popResponseQueue;
2119   }
2120
2121   transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite,  L2DataArrayWrite} {
2122     w0_writeDcache;
2123     xl0_loadDone;
2124     w1_writeDcache;
2125     xl1_loadDone;
2126     uu_sendUnblock;
2127     pr_popResponseQueue;
2128   }
2129
2130   transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2131     c0_copyL2ToL1;
2132     mru_setMRU;
2133     l0_loadDone;
2134     pt_popTriggerQueue;
2135   }
2136
2137   transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2138     c1_copyL2ToL1;
2139     mru_setMRU;
2140     l1_loadDone;
2141     pt_popTriggerQueue;
2142   }
2143
2144   transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2145     ci_copyL2ToL1;
2146     mru_setMRU;
2147     il0_loadDone;
2148     pt_popTriggerQueue;
2149   }
2150
2151   transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2152     ci_copyL2ToL1;
2153     mru_setMRU;
2154     il1_loadDone;
2155     pt_popTriggerQueue;
2156   }
2157
2158   transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2159     c0_copyL2ToL1;
2160     mru_setMRU;
2161     l0_loadDone;
2162     pt_popTriggerQueue;
2163   }
2164
2165   transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2166     c1_copyL2ToL1;
2167     mru_setMRU;
2168     l1_loadDone;
2169     pt_popTriggerQueue;
2170   }
2171
2172   transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2173     c0_copyL2ToL1;
2174     mru_setMRU;
2175     l0_loadDone;
2176     pt_popTriggerQueue;
2177   }
2178
2179   transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2180     c1_copyL2ToL1;
2181     mru_setMRU;
2182     l1_loadDone;
2183     pt_popTriggerQueue;
2184   }
2185
2186   transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2187     c0_copyL2ToL1;
2188     mru_setMRU;
2189     l0_loadDone;
2190     pt_popTriggerQueue;
2191   }
2192
2193   transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2194     c1_copyL2ToL1;
2195     mru_setMRU;
2196     l1_loadDone;
2197     pt_popTriggerQueue;
2198   }
2199
2200   transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2201     c1_copyL2ToL1;
2202     mru_setMRU;
2203     l1_loadDone;
2204     pt_popTriggerQueue;
2205   }
2206
2207   transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2208     c0_copyL2ToL1;
2209     mru_setMRU;
2210     l0_loadDone;
2211     pt_popTriggerQueue;
2212   }
2213
2214   transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2215     c0_copyL2ToL1;
2216     mru_setMRU;
2217     l0_loadDone;
2218     pt_popTriggerQueue;
2219   }
2220
2221   transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2222     c1_copyL2ToL1;
2223     mru_setMRU;
2224     l1_loadDone;
2225     pt_popTriggerQueue;
2226   }
2227
2228   transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} {
2229     c0_copyL2ToL1;
2230     mru_setMRU;
2231     l0_loadDone;
2232     pt_popTriggerQueue;
2233   }
2234
2235   transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} {
2236     c1_copyL2ToL1;
2237     mru_setMRU;
2238     l1_loadDone;
2239     pt_popTriggerQueue;
2240   }
2241
2242   transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2243     c0_copyL2ToL1;
2244     mru_setMRU;
2245     l0_loadDone;
2246     pt_popTriggerQueue;
2247   }
2248
2249   transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2250     c1_copyL2ToL1;
2251     mru_setMRU;
2252     l1_loadDone;
2253     pt_popTriggerQueue;
2254   }
2255
2256   transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2257     c0_copyL2ToL1;
2258     mru_setMRU;
2259     l0_loadDone;
2260     pt_popTriggerQueue;
2261   }
2262
2263   transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2264     c1_copyL2ToL1;
2265     mru_setMRU;
2266     l1_loadDone;
2267     pt_popTriggerQueue;
2268   }
2269
2270   transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} {
2271     c0_copyL2ToL1;
2272     mru_setMRU;
2273     l0_loadDone;
2274     pt_popTriggerQueue;
2275   }
2276
2277   transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} {
2278     c1_copyL2ToL1;
2279     mru_setMRU;
2280     l1_loadDone;
2281     pt_popTriggerQueue;
2282   }
2283
2284   transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} {
2285     c0_copyL2ToL1;
2286     mru_setMRU;
2287     l0_loadDone;
2288     pt_popTriggerQueue;
2289   }
2290
2291   transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} {
2292     c1_copyL2ToL1;
2293     mru_setMRU;
2294     l1_loadDone;
2295     pt_popTriggerQueue;
2296   }
2297
2298   transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} {
2299     c0_copyL2ToL1;
2300     mru_setMRU;
2301     l0_loadDone;
2302     pt_popTriggerQueue;
2303   }
2304
2305   transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} {
2306     c1_copyL2ToL1;
2307     mru_setMRU;
2308     l1_loadDone;
2309     pt_popTriggerQueue;
2310   }
2311
2312   transition(IF_E0S, L2_to_L1D0, I_E0S) {} {
2313     pt_popTriggerQueue;
2314   }
2315
2316   transition(IF_E1S, L2_to_L1D1, I_E1S) {} {
2317     pt_popTriggerQueue;
2318   }
2319
2320   transition(IF_ES, L2_to_L1D0, IF1_ES) {} {
2321     pt_popTriggerQueue;
2322   }
2323
2324   transition(IF_ES, L2_to_L1D1, IF0_ES) {} {
2325     pt_popTriggerQueue;
2326   }
2327
2328   transition(IF0_ES, L2_to_L1D0, I_ES) {} {
2329     pt_popTriggerQueue;
2330   }
2331
2332   transition(IF1_ES, L2_to_L1D1, I_ES) {} {
2333     pt_popTriggerQueue;
2334   }
2335
2336   transition(F_S0, L2_to_L1I, S0) {} {
2337     pt_popTriggerQueue;
2338   }
2339
2340   transition(F_S1, L2_to_L1I, S1) {} {
2341     pt_popTriggerQueue;
2342   }
2343
2344   transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2345     mru_setMRU;
2346     xs0_storeDone;
2347     uu_sendUnblock;
2348     pr_popResponseQueue;
2349   }
2350
2351   transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2352     mru_setMRU;
2353     xs1_storeDone;
2354     uu_sendUnblock;
2355     pr_popResponseQueue;
2356   }
2357
2358   transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} {
2359     wb_data;
2360     d_deallocateTBE;
2361     pr_popResponseQueue;
2362   }
2363
2364   transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} {
2365     wb_data;
2366     d_deallocateTBE;
2367     pr_popResponseQueue;
2368   }
2369
2370   transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} {
2371     wb_data;
2372     i2_invL2;
2373     a2_allocateL2;
2374     d_deallocateTBE; // FOO
2375     nS_issueRdBlkS;
2376     pr_popResponseQueue;
2377   }
2378
2379   transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} {
2380     wb_data;
2381     i2_invL2;
2382     a2_allocateL2;
2383     d_deallocateTBE; // FOO
2384     nS_issueRdBlkS;
2385     pr_popResponseQueue;
2386   }
2387
2388   // Writeback cancel "ack"
2389   transition(I_C, NB_AckWB, I) {L2TagArrayWrite} {
2390     ss_sendStaleNotification;
2391     d_deallocateTBE;
2392     pr_popResponseQueue;
2393   }
2394
2395   transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} {
2396     ss_sendStaleNotification;
2397     pr_popResponseQueue;
2398   }
2399
2400   transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} {
2401     ss_sendStaleNotification;
2402     pr_popResponseQueue;
2403   }
2404
2405   transition(S_C, NB_AckWB, S) {L2TagArrayWrite} {
2406     ss_sendStaleNotification;
2407     pr_popResponseQueue;
2408   }
2409
2410   // Begin Probe Transitions
2411
2412   transition({Ms, M0, M1, O}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2413     forward_eviction_to_cpu0;
2414     forward_eviction_to_cpu1;
2415     pd_sendProbeResponseData;
2416     i2_invL2;
2417     ib_invBothClusters;
2418     pp_popProbeQueue;
2419   }
2420
2421   transition({Es, E0, E1, S, I}, PrbInvData, I) {L2TagArrayRead, L2TagArrayWrite} {
2422     forward_eviction_to_cpu0;
2423     forward_eviction_to_cpu1;
2424     pi_sendProbeResponseInv;
2425     i2_invL2;
2426     ib_invBothClusters;
2427     ii_invIcache;  // only relevant for S
2428     pp_popProbeQueue;
2429   }
2430
2431   transition(S_C, PrbInvData, I_C) {L2TagArrayWrite} {
2432     t_allocateTBE;
2433     forward_eviction_to_cpu0;
2434     forward_eviction_to_cpu1;
2435     pi_sendProbeResponseInv;
2436     i2_invL2;
2437     ib_invBothClusters;
2438     ii_invIcache;
2439     pp_popProbeQueue;
2440   }
2441
2442   transition(I_C, PrbInvData, I_C) {} {
2443     pi_sendProbeResponseInv;
2444     ib_invBothClusters;
2445     pp_popProbeQueue;
2446   }
2447
2448   transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} {
2449     forward_eviction_to_cpu0;
2450     forward_eviction_to_cpu1;
2451     pi_sendProbeResponseInv;
2452     i2_invL2; // nothing will happen in I
2453     ib_invBothClusters;
2454     ii_invIcache;
2455     pp_popProbeQueue;
2456   }
2457
2458   transition(S_C, PrbInv, I_C) {L2TagArrayWrite} {
2459     t_allocateTBE;
2460     forward_eviction_to_cpu0;
2461     forward_eviction_to_cpu1;
2462     pi_sendProbeResponseInv;
2463     i2_invL2;
2464     ib_invBothClusters;
2465     ii_invIcache;
2466     pp_popProbeQueue;
2467   }
2468
2469   transition(I_C, PrbInv, I_C) {} {
2470     pi_sendProbeResponseInv;
2471     ib_invBothClusters;
2472     ii_invIcache;
2473     pp_popProbeQueue;
2474   }
2475
2476   transition({Ms, M0, M1, O}, PrbShrData, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2477     pd_sendProbeResponseData;
2478     pp_popProbeQueue;
2479   }
2480
2481   transition({Es, E0, E1, S}, PrbShrData, S) {L2TagArrayRead, L2TagArrayWrite} {
2482     ph_sendProbeResponseHit;
2483     pp_popProbeQueue;
2484   }
2485
2486   transition(S_C, PrbShrData) {} {
2487     ph_sendProbeResponseHit;
2488     pp_popProbeQueue;
2489   }
2490
2491   transition({I, I_C}, PrbShrData) {L2TagArrayRead} {
2492     pb_sendProbeResponseBackprobe;
2493     pp_popProbeQueue;
2494   }
2495
2496   transition({I_M0, I_E0S}, {PrbInv, PrbInvData}) {} {
2497     pi_sendProbeResponseInv;
2498     ib_invBothClusters;  // must invalidate current data (only relevant for I_M0)
2499     a0_allocateL1D;  // but make sure there is room for incoming data when it arrives
2500     pp_popProbeQueue;
2501   }
2502
2503   transition({I_M1, I_E1S}, {PrbInv, PrbInvData}) {} {
2504     pi_sendProbeResponseInv;
2505     ib_invBothClusters; // must invalidate current data (only relevant for I_M1)
2506     a1_allocateL1D;  // but make sure there is room for incoming data when it arrives
2507     pp_popProbeQueue;
2508   }
2509
2510   transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbShrData}) {} {
2511     pi_sendProbeResponseInv;
2512     ib_invBothClusters;
2513     a0_allocateL1D;
2514     a1_allocateL1D;
2515     pp_popProbeQueue;
2516   }
2517
2518   transition({I_M0, I_E0S, I_M1, I_E1S}, PrbShrData) {} {
2519     pb_sendProbeResponseBackprobe;
2520     pp_popProbeQueue;
2521   }
2522
2523   transition(ES_I, PrbInvData, I_C) {} {
2524     pi_sendProbeResponseInv;
2525     ib_invBothClusters;
2526     ii_invIcache;
2527     pp_popProbeQueue;
2528   }
2529
2530   transition(MO_I, PrbInvData, I_C) {} {
2531     pdt_sendProbeResponseDataFromTBE;
2532     ib_invBothClusters;
2533     ii_invIcache;
2534     pp_popProbeQueue;
2535   }
2536
2537   transition(MO_I, PrbInv, I_C) {} {
2538     pi_sendProbeResponseInv;
2539     ib_invBothClusters;
2540     ii_invIcache;
2541     pp_popProbeQueue;
2542   }
2543
2544   transition(ES_I, PrbInv, I_C) {} {
2545     pi_sendProbeResponseInv;
2546     ib_invBothClusters;
2547     ii_invIcache;
2548     pp_popProbeQueue;
2549   }
2550
2551   transition(ES_I, PrbShrData, ES_I) {} {
2552     ph_sendProbeResponseHit;
2553     s_setSharedFlip;
2554     pp_popProbeQueue;
2555   }
2556
2557   transition(MO_I, PrbShrData, MO_I) {} {
2558     pdt_sendProbeResponseDataFromTBE;
2559     s_setSharedFlip;
2560     pp_popProbeQueue;
2561   }
2562
2563   transition(MO_S0, PrbInvData, S0_C) {L2TagArrayWrite} {
2564     forward_eviction_to_cpu0;
2565     forward_eviction_to_cpu1;
2566     pdt_sendProbeResponseDataFromTBE;
2567     i2_invL2;
2568     a2_allocateL2;
2569     d_deallocateTBE;
2570     nS_issueRdBlkS;
2571     pp_popProbeQueue;
2572   }
2573
2574   transition(MO_S1, PrbInvData, S1_C) {L2TagArrayWrite} {
2575     forward_eviction_to_cpu0;
2576     forward_eviction_to_cpu1;
2577     pdt_sendProbeResponseDataFromTBE;
2578     i2_invL2;
2579     a2_allocateL2;
2580     d_deallocateTBE;
2581     nS_issueRdBlkS;
2582     pp_popProbeQueue;
2583   }
2584
2585   transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} {
2586     forward_eviction_to_cpu0;
2587     forward_eviction_to_cpu1;
2588     pi_sendProbeResponseInv;
2589     i2_invL2;
2590     a2_allocateL2;
2591     d_deallocateTBE;
2592     nS_issueRdBlkS;
2593     pp_popProbeQueue;
2594   }
2595
2596   transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} {
2597     forward_eviction_to_cpu0;
2598     forward_eviction_to_cpu1;
2599     pi_sendProbeResponseInv;
2600     i2_invL2;
2601     a2_allocateL2;
2602     d_deallocateTBE;
2603     nS_issueRdBlkS;
2604     pp_popProbeQueue;
2605   }
2606
2607   transition({MO_S0, MO_S1}, PrbShrData) {} {
2608     pdt_sendProbeResponseDataFromTBE;
2609     s_setSharedFlip;
2610     pp_popProbeQueue;
2611   }
2612
2613   transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInv}, IF_E0S) {}{
2614     forward_eviction_to_cpu0;
2615     forward_eviction_to_cpu1;
2616     pi_sendProbeResponseInv;
2617     // invalidate everything you've got
2618     ib_invBothClusters;
2619     ii_invIcache;
2620     i2_invL2;
2621     // but make sure you have room for what you need from the fill
2622     a0_allocateL1D;
2623     a2_allocateL2;
2624     n_issueRdBlk;
2625     pp_popProbeQueue;
2626   }
2627
2628   transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInv}, IF_E1S) {} {
2629     forward_eviction_to_cpu0;
2630     forward_eviction_to_cpu1;
2631     pi_sendProbeResponseInv;
2632     // invalidate everything you've got
2633     ib_invBothClusters;
2634     ii_invIcache;
2635     i2_invL2;
2636     // but make sure you have room for what you need from the fill
2637     a1_allocateL1D;
2638     a2_allocateL2;
2639     n_issueRdBlk;
2640     pp_popProbeQueue;
2641   }
2642
2643   transition({S_F, Es_F}, {PrbInvData, PrbInv}, IF_ES) {} {
2644     forward_eviction_to_cpu0;
2645     forward_eviction_to_cpu1;
2646     pi_sendProbeResponseInv;
2647     // invalidate everything you've got
2648     ib_invBothClusters;
2649     ii_invIcache;
2650     i2_invL2;
2651     // but make sure you have room for what you need from the fill
2652     a0_allocateL1D;
2653     a1_allocateL1D;
2654     a2_allocateL2;
2655     n_issueRdBlk;
2656     pp_popProbeQueue;
2657   }
2658
2659   transition(Si_F0, {PrbInvData, PrbInv}, F_S0) {} {
2660     forward_eviction_to_cpu0;
2661     forward_eviction_to_cpu1;
2662     pi_sendProbeResponseInv;
2663     ib_invBothClusters;
2664     ii_invIcache;
2665     i2_invL2;
2666     ai_allocateL1I;
2667     a2_allocateL2;
2668     nS_issueRdBlkS;
2669     pp_popProbeQueue;
2670   }
2671
2672   transition(Si_F1, {PrbInvData, PrbInv}, F_S1) {} {
2673     forward_eviction_to_cpu0;
2674     forward_eviction_to_cpu1;
2675     pi_sendProbeResponseInv;
2676     ib_invBothClusters;
2677     ii_invIcache;
2678     i2_invL2;
2679     ai_allocateL1I;
2680     a2_allocateL2;
2681     nS_issueRdBlkS;
2682     pp_popProbeQueue;
2683   }
2684
2685   transition({Es_F0, E0_F, E1_Es}, PrbShrData, S_F0) {} {
2686     ph_sendProbeResponseHit;
2687     pp_popProbeQueue;
2688   }
2689
2690   transition({Es_F1, E1_F, E0_Es}, PrbShrData, S_F1) {} {
2691     ph_sendProbeResponseHit;
2692     pp_popProbeQueue;
2693   }
2694
2695   transition(Es_F, PrbShrData, S_F) {} {
2696     ph_sendProbeResponseHit;
2697     pp_popProbeQueue;
2698   }
2699
2700   transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, PrbShrData) {} {
2701     ph_sendProbeResponseHit;
2702     pp_popProbeQueue;
2703   }
2704
2705   transition(S_M0, PrbInvData, I_M0) {} {
2706     forward_eviction_to_cpu0;
2707     forward_eviction_to_cpu1;
2708     pim_sendProbeResponseInvMs;
2709     ib_invBothClusters;
2710     ii_invIcache;
2711     i2_invL2;
2712     a0_allocateL1D;
2713     a2_allocateL2;
2714     pp_popProbeQueue;
2715   }
2716
2717   transition(O_M0, PrbInvData, I_M0) {L2DataArrayRead} {
2718     forward_eviction_to_cpu0;
2719     forward_eviction_to_cpu1;
2720     pdm_sendProbeResponseDataMs;
2721     ib_invBothClusters;
2722     ii_invIcache;
2723     i2_invL2;
2724     a0_allocateL1D;
2725     a2_allocateL2;
2726     pp_popProbeQueue;
2727   }
2728
2729   transition({S_M0, O_M0}, {PrbInv}, I_M0) {} {
2730     forward_eviction_to_cpu0;
2731     forward_eviction_to_cpu1;
2732     pim_sendProbeResponseInvMs;
2733     ib_invBothClusters;
2734     ii_invIcache;
2735     i2_invL2;
2736     a0_allocateL1D;
2737     a2_allocateL2;
2738     pp_popProbeQueue;
2739   }
2740
2741   transition(S_M1, PrbInvData, I_M1) {} {
2742     forward_eviction_to_cpu0;
2743     forward_eviction_to_cpu1;
2744     pim_sendProbeResponseInvMs;
2745     ib_invBothClusters;
2746     ii_invIcache;
2747     i2_invL2;
2748     a1_allocateL1D;
2749     a2_allocateL2;
2750     pp_popProbeQueue;
2751   }
2752
2753   transition(O_M1, PrbInvData, I_M1) {} {
2754     forward_eviction_to_cpu0;
2755     forward_eviction_to_cpu1;
2756     pdm_sendProbeResponseDataMs;
2757     ib_invBothClusters;
2758     ii_invIcache;
2759     i2_invL2;
2760     a1_allocateL1D;
2761     a2_allocateL2;
2762     pp_popProbeQueue;
2763   }
2764
2765   transition({S_M1, O_M1}, {PrbInv}, I_M1) {} {
2766     forward_eviction_to_cpu0;
2767     forward_eviction_to_cpu1;
2768     pim_sendProbeResponseInvMs;
2769     ib_invBothClusters;
2770     ii_invIcache;
2771     i2_invL2;
2772     a1_allocateL1D;
2773     a2_allocateL2;
2774     pp_popProbeQueue;
2775   }
2776
2777   transition({S0, S0_C}, {PrbInvData, PrbInv}) {} {
2778     forward_eviction_to_cpu0;
2779     forward_eviction_to_cpu1;
2780     pi_sendProbeResponseInv;
2781     ib_invBothClusters;
2782     ii_invIcache;
2783     i2_invL2;
2784     ai_allocateL1I;
2785     a2_allocateL2;
2786     pp_popProbeQueue;
2787   }
2788
2789   transition({S1, S1_C}, {PrbInvData, PrbInv}) {}  {
2790     forward_eviction_to_cpu0;
2791     forward_eviction_to_cpu1;
2792     pi_sendProbeResponseInv;
2793     ib_invBothClusters;
2794     ii_invIcache;
2795     i2_invL2;
2796     ai_allocateL1I;
2797     a2_allocateL2;
2798     pp_popProbeQueue;
2799   }
2800
2801   transition({S_M0, S_M1}, PrbShrData) {} {
2802     ph_sendProbeResponseHit;
2803     pp_popProbeQueue;
2804   }
2805
2806   transition({O_M0, O_M1}, PrbShrData) {L2DataArrayRead} {
2807     pd_sendProbeResponseData;
2808     pp_popProbeQueue;
2809   }
2810
2811   transition({S0, S1, S0_C, S1_C}, PrbShrData) {} {
2812     pb_sendProbeResponseBackprobe;
2813     pp_popProbeQueue;
2814   }
2815
2816   transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInvData, IF_E0S) { L2DataArrayRead} {
2817     forward_eviction_to_cpu0;
2818     forward_eviction_to_cpu1;
2819     pd_sendProbeResponseData;
2820     ib_invBothClusters;
2821     i2_invL2;
2822     a0_allocateL1D;
2823     a2_allocateL2;
2824     n_issueRdBlk;
2825     pp_popProbeQueue;
2826   }
2827
2828   transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInvData, IF_E1S) {L2DataArrayRead} {
2829     forward_eviction_to_cpu0;
2830     forward_eviction_to_cpu1;
2831     pd_sendProbeResponseData;
2832     ib_invBothClusters;
2833     i2_invL2;
2834     a1_allocateL1D;
2835     a2_allocateL2;
2836     n_issueRdBlk;
2837     pp_popProbeQueue;
2838   }
2839
2840   transition({Ms_F, O_F}, PrbInvData, IF_ES) {L2DataArrayRead} {
2841     forward_eviction_to_cpu0;
2842     forward_eviction_to_cpu1;
2843     pd_sendProbeResponseData;
2844     ib_invBothClusters;
2845     i2_invL2;
2846     a0_allocateL1D;
2847     a1_allocateL1D;
2848     a2_allocateL2;
2849     n_issueRdBlk;
2850     pp_popProbeQueue;
2851   }
2852
2853   transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} {
2854     forward_eviction_to_cpu0;
2855     forward_eviction_to_cpu1;
2856     pi_sendProbeResponseInv;
2857     ib_invBothClusters;
2858     i2_invL2;
2859     a0_allocateL1D;
2860     a2_allocateL2;
2861     n_issueRdBlk;
2862     pp_popProbeQueue;
2863   }
2864
2865   transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} {
2866     forward_eviction_to_cpu0;
2867     forward_eviction_to_cpu1;
2868     pi_sendProbeResponseInv;
2869     ib_invBothClusters;
2870     i2_invL2;
2871     a1_allocateL1D;
2872     a2_allocateL2;
2873     n_issueRdBlk;
2874     pp_popProbeQueue;
2875   }
2876
2877   transition({Ms_F, O_F}, PrbInv, IF_ES) {} {
2878     forward_eviction_to_cpu0;
2879     forward_eviction_to_cpu1;
2880     pi_sendProbeResponseInv;
2881     ib_invBothClusters;
2882     i2_invL2;
2883     a0_allocateL1D;
2884     a1_allocateL1D;
2885     a2_allocateL2;
2886     n_issueRdBlk;
2887     pp_popProbeQueue;
2888   }
2889
2890   transition({Ms_F0, M0_F, M1_Ms}, PrbShrData, O_F0) {L2DataArrayRead} {
2891     pd_sendProbeResponseData;
2892     pp_popProbeQueue;
2893   }
2894
2895   transition({Ms_F1, M1_F, M0_Ms}, PrbShrData, O_F1) {} {
2896   }
2897
2898   transition({Ms_F}, PrbShrData, O_F) {L2DataArrayRead} {
2899     pd_sendProbeResponseData;
2900     pp_popProbeQueue;
2901   }
2902
2903   transition({O_F0, O_F1, O_F}, PrbShrData) {L2DataArrayRead} {
2904     pd_sendProbeResponseData;
2905     pp_popProbeQueue;
2906   }
2907
2908   // END TRANSITIONS
2909 }
2910
2911