2 * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
5 * For use for simulation and test purposes only
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36 machine(MachineType:CorePair, "CP-like Core Coherence")
37 : Sequencer * sequencer;
38 Sequencer * sequencer1;
39 CacheMemory * L1Icache;
40 CacheMemory * L1D0cache;
41 CacheMemory * L1D1cache;
42 CacheMemory * L2cache;
44 bool send_evictions := "False";
45 Cycles issue_latency := 5;
46 Cycles l2_hit_latency := 18;
51 MessageBuffer * requestFromCore, network="To", virtual_network="0", ordered="true", vnet_type="request";
52 MessageBuffer * responseFromCore, network="To", virtual_network="2", ordered="false", vnet_type="response";
53 MessageBuffer * unblockFromCore, network="To", virtual_network="4", ordered="false", vnet_type="unblock";
56 MessageBuffer * probeToCore, network="From", virtual_network="0", ordered="false", vnet_type="request";
57 MessageBuffer * responseToCore, network="From", virtual_network="2", ordered="false", vnet_type="response";
59 MessageBuffer * mandatoryQueue, ordered="false";
60 MessageBuffer * triggerQueue, ordered="true";
66 state_declaration(State, desc="Cache states", default="CorePair_State_I") {
68 I, AccessPermission:Invalid, desc="Invalid";
69 S, AccessPermission:Read_Only, desc="Shared";
70 E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership";
71 E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership";
72 Es, AccessPermission:Read_Write, desc="Exclusive in core";
73 O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line";
74 Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line";
75 M0, AccessPermission:Read_Write, desc="Modified with cluster ownership";
76 M1, AccessPermission:Read_Write, desc="Modified with cluster ownership";
79 I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
80 I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
81 I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well";
82 I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well";
83 I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well";
84 I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well";
85 I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
86 I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
87 I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters";
89 IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive";
90 IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive";
91 IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills";
92 IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
93 IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
94 F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received";
95 F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received";
97 ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack";
98 MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack";
99 MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
100 MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
101 S_F0, AccessPermission:Read_Only, desc="Shared, filling L1";
102 S_F1, AccessPermission:Read_Only, desc="Shared, filling L1";
103 S_F, AccessPermission:Read_Only, desc="Shared, filling L1";
104 O_F0, AccessPermission:Read_Only, desc="Owned, filling L1";
105 O_F1, AccessPermission:Read_Only, desc="Owned, filling L1";
106 O_F, AccessPermission:Read_Only, desc="Owned, filling L1";
107 Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache";
108 Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache";
109 S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
110 S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
111 O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
112 O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
113 S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response";
114 S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response";
116 Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
117 Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
118 Es_F, AccessPermission:Read_Write, desc="Es, other cluster read, filling";
119 E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling";
120 E1_F, AccessPermission:Read_Write, desc="...";
121 E0_Es, AccessPermission:Read_Write, desc="...";
122 E1_Es, AccessPermission:Read_Write, desc="...";
123 Ms_F0, AccessPermission:Read_Write, desc="...";
124 Ms_F1, AccessPermission:Read_Write, desc="...";
125 Ms_F, AccessPermission:Read_Write, desc="...";
126 M0_F, AccessPermission:Read_Write, desc="...";
127 M0_Ms, AccessPermission:Read_Write, desc="...";
128 M1_F, AccessPermission:Read_Write, desc="...";
129 M1_Ms, AccessPermission:Read_Write, desc="...";
131 I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback";
132 S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
133 S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
134 S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck";
139 enumeration(Event, desc="CP Events") {
140 // CP Initiated events
141 C0_Load_L1miss, desc="Cluster 0 load, L1 missed";
142 C0_Load_L1hit, desc="Cluster 0 load, L1 hit";
143 C1_Load_L1miss, desc="Cluster 1 load L1 missed";
144 C1_Load_L1hit, desc="Cluster 1 load L1 hit";
145 Ifetch0_L1hit, desc="Instruction fetch, hit in the L1";
146 Ifetch1_L1hit, desc="Instruction fetch, hit in the L1";
147 Ifetch0_L1miss, desc="Instruction fetch, missed in the L1";
148 Ifetch1_L1miss, desc="Instruction fetch, missed in the L1";
149 C0_Store_L1miss, desc="Cluster 0 store missed in L1";
150 C0_Store_L1hit, desc="Cluster 0 store hit in L1";
151 C1_Store_L1miss, desc="Cluster 1 store missed in L1";
152 C1_Store_L1hit, desc="Cluster 1 store hit in L1";
153 // NB Initiated events
154 NB_AckS, desc="NB Ack to Core Request";
155 NB_AckM, desc="NB Ack to Core Request";
156 NB_AckE, desc="NB Ack to Core Request";
158 NB_AckWB, desc="NB Ack for writeback";
160 // Memory System initiatied events
161 L1I_Repl, desc="Replace address from L1I"; // Presumed clean
162 L1D0_Repl, desc="Replace address from L1D0"; // Presumed clean
163 L1D1_Repl, desc="Replace address from L1D1"; // Presumed clean
164 L2_Repl, desc="Replace address from L2";
166 L2_to_L1D0, desc="L1 fill from L2";
167 L2_to_L1D1, desc="L1 fill from L2";
168 L2_to_L1I, desc="L1 fill from L2";
171 PrbInvData, desc="probe, return O or M data";
172 PrbInvDataDemand, desc="probe, return O or M data. Demand request";
173 PrbInv, desc="probe, no need for data";
174 PrbShrData, desc="probe downgrade, return O or M data";
175 PrbShrDataDemand, desc="probe downgrade, return O or M data. Demand request";
176 ForceRepl, desc="probe from r-buf. Act as though a repl";
177 ForceDowngrade, desc="probe from r-buf. Act as though a repl";
181 enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
182 L1D0DataArrayRead, desc="Read the data array";
183 L1D0DataArrayWrite, desc="Write the data array";
184 L1D0TagArrayRead, desc="Read the data array";
185 L1D0TagArrayWrite, desc="Write the data array";
186 L1D1DataArrayRead, desc="Read the data array";
187 L1D1DataArrayWrite, desc="Write the data array";
188 L1D1TagArrayRead, desc="Read the data array";
189 L1D1TagArrayWrite, desc="Write the data array";
190 L1IDataArrayRead, desc="Read the data array";
191 L1IDataArrayWrite, desc="Write the data array";
192 L1ITagArrayRead, desc="Read the data array";
193 L1ITagArrayWrite, desc="Write the data array";
194 L2DataArrayRead, desc="Read the data array";
195 L2DataArrayWrite, desc="Write the data array";
196 L2TagArrayRead, desc="Read the data array";
197 L2TagArrayWrite, desc="Write the data array";
201 // BEGIN STRUCTURE DEFINITIONS
205 structure(Entry, desc="...", interface="AbstractCacheEntry") {
206 State CacheState, desc="cache state";
207 bool Dirty, desc="Is the data dirty (diff than memory)?";
208 DataBlock DataBlk, desc="data for the block";
209 bool FromL2, default="false", desc="block just moved from L2";
212 structure(TBE, desc="...") {
213 State TBEState, desc="Transient state";
214 DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
215 bool Dirty, desc="Is the data dirty (different than memory)?";
216 int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";
217 bool Shared, desc="Victim hit by shared probe";
218 bool AckNeeded, desc="True if need to ack r-dir";
221 structure(TBETable, external="yes") {
224 void deallocate(Addr);
225 bool isPresent(Addr);
228 TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
231 Tick cyclesToTicks(Cycles c);
233 void set_cache_entry(AbstractCacheEntry b);
234 void unset_cache_entry();
237 void wakeUpAllBuffers();
238 void wakeUpBuffers(Addr a);
240 MachineID mapAddressToMachine(Addr addr, MachineType mtype);
242 // END STRUCTURE DEFINITIONS
244 // BEGIN INTERNAL FUNCTIONS
246 MachineID getPeer(MachineID mach) {
247 return createMachineID(MachineType:RegionBuffer, intToID(regionBufferNum));
250 bool addressInCore(Addr addr) {
251 return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr));
254 Entry getCacheEntry(Addr address), return_by_pointer="yes" {
255 Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
256 return L2cache_entry;
259 DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
260 TBE tbe := TBEs.lookup(addr);
264 return getCacheEntry(addr).DataBlk;
268 Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" {
270 Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr));
273 Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr));
278 Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
279 Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
283 bool presentOrAvail2(Addr addr) {
284 return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
287 bool presentOrAvailI(Addr addr) {
288 return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr);
291 bool presentOrAvailD0(Addr addr) {
292 return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr);
295 bool presentOrAvailD1(Addr addr) {
296 return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr);
299 State getState(TBE tbe, Entry cache_entry, Addr addr) {
302 } else if (is_valid(cache_entry)) {
303 return cache_entry.CacheState;
308 void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
310 tbe.TBEState := state;
313 if (is_valid(cache_entry)) {
314 cache_entry.CacheState := state;
318 AccessPermission getAccessPermission(Addr addr) {
319 TBE tbe := TBEs.lookup(addr);
321 return CorePair_State_to_permission(tbe.TBEState);
324 Entry cache_entry := getCacheEntry(addr);
325 if(is_valid(cache_entry)) {
326 return CorePair_State_to_permission(cache_entry.CacheState);
329 return AccessPermission:NotPresent;
332 void functionalRead(Addr addr, Packet *pkt) {
333 TBE tbe := TBEs.lookup(addr);
335 testAndRead(addr, tbe.DataBlk, pkt);
337 functionalMemoryRead(pkt);
341 int functionalWrite(Addr addr, Packet *pkt) {
342 int num_functional_writes := 0;
344 TBE tbe := TBEs.lookup(addr);
346 num_functional_writes := num_functional_writes +
347 testAndWrite(addr, tbe.DataBlk, pkt);
350 num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
351 return num_functional_writes;
354 bool isValid(Addr addr) {
355 AccessPermission perm := getAccessPermission(addr);
356 if (perm == AccessPermission:NotPresent ||
357 perm == AccessPermission:Invalid ||
358 perm == AccessPermission:Busy) {
365 void setAccessPermission(Entry cache_entry, Addr addr, State state) {
366 if (is_valid(cache_entry)) {
367 cache_entry.changePermission(CorePair_State_to_permission(state));
371 MachineType testAndClearLocalHit(Entry cache_entry) {
372 assert(is_valid(cache_entry));
373 if (cache_entry.FromL2) {
374 cache_entry.FromL2 := false;
375 return MachineType:L2Cache;
377 return MachineType:L1Cache;
381 void recordRequestType(RequestType request_type, Addr addr) {
382 if (request_type == RequestType:L1D0DataArrayRead) {
383 L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
384 } else if (request_type == RequestType:L1D0DataArrayWrite) {
385 L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
386 } else if (request_type == RequestType:L1D0TagArrayRead) {
387 L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
388 } else if (request_type == RequestType:L1D0TagArrayWrite) {
389 L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
390 } else if (request_type == RequestType:L1D1DataArrayRead) {
391 L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
392 } else if (request_type == RequestType:L1D1DataArrayWrite) {
393 L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
394 } else if (request_type == RequestType:L1D1TagArrayRead) {
395 L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
396 } else if (request_type == RequestType:L1D1TagArrayWrite) {
397 L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
398 } else if (request_type == RequestType:L1IDataArrayRead) {
399 L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr);
400 } else if (request_type == RequestType:L1IDataArrayWrite) {
401 L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
402 } else if (request_type == RequestType:L1ITagArrayRead) {
403 L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr);
404 } else if (request_type == RequestType:L1ITagArrayWrite) {
405 L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
406 } else if (request_type == RequestType:L2DataArrayRead) {
407 L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
408 } else if (request_type == RequestType:L2DataArrayWrite) {
409 L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
410 } else if (request_type == RequestType:L2TagArrayRead) {
411 L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
412 } else if (request_type == RequestType:L2TagArrayWrite) {
413 L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
417 bool checkResourceAvailable(RequestType request_type, Addr addr) {
418 if (request_type == RequestType:L2DataArrayRead) {
419 return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
420 } else if (request_type == RequestType:L2DataArrayWrite) {
421 return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
422 } else if (request_type == RequestType:L2TagArrayRead) {
423 return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
424 } else if (request_type == RequestType:L2TagArrayWrite) {
425 return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
426 } else if (request_type == RequestType:L1D0DataArrayRead) {
427 return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
428 } else if (request_type == RequestType:L1D0DataArrayWrite) {
429 return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
430 } else if (request_type == RequestType:L1D0TagArrayRead) {
431 return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
432 } else if (request_type == RequestType:L1D0TagArrayWrite) {
433 return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
434 } else if (request_type == RequestType:L1D1DataArrayRead) {
435 return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
436 } else if (request_type == RequestType:L1D1DataArrayWrite) {
437 return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
438 } else if (request_type == RequestType:L1D1TagArrayRead) {
439 return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
440 } else if (request_type == RequestType:L1D1TagArrayWrite) {
441 return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
442 } else if (request_type == RequestType:L1IDataArrayRead) {
443 return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
444 } else if (request_type == RequestType:L1IDataArrayWrite) {
445 return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
446 } else if (request_type == RequestType:L1ITagArrayRead) {
447 return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
448 } else if (request_type == RequestType:L1ITagArrayWrite) {
449 return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
455 // END INTERNAL FUNCTIONS
459 out_port(requestNetwork_out, CPURequestMsg, requestFromCore);
460 out_port(responseNetwork_out, ResponseMsg, responseFromCore);
461 out_port(triggerQueue_out, TriggerMsg, triggerQueue);
462 out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
466 in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") {
467 if (triggerQueue_in.isReady(clockEdge())) {
468 peek(triggerQueue_in, TriggerMsg) {
469 Entry cache_entry := getCacheEntry(in_msg.addr);
470 TBE tbe := TBEs.lookup(in_msg.addr);
472 if (in_msg.Type == TriggerType:L2_to_L1) {
473 if (in_msg.Dest == CacheId:L1I) {
474 trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe);
475 } else if (in_msg.Dest == CacheId:L1D0) {
476 trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe);
477 } else if (in_msg.Dest == CacheId:L1D1) {
478 trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe);
480 error("unexpected trigger dest");
488 in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) {
489 if (probeNetwork_in.isReady(clockEdge())) {
490 peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") {
491 Entry cache_entry := getCacheEntry(in_msg.addr);
492 TBE tbe := TBEs.lookup(in_msg.addr);
494 if (in_msg.Type == ProbeRequestType:PrbInv) {
495 if (in_msg.DemandRequest) {
496 trigger(Event:PrbInvDataDemand, in_msg.addr, cache_entry, tbe);
497 } else if (in_msg.ReturnData) {
498 trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
500 trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
502 } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
503 if (in_msg.DemandRequest) {
504 trigger(Event:PrbShrDataDemand, in_msg.addr, cache_entry, tbe);
506 assert(in_msg.ReturnData);
507 trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
509 } else if (in_msg.Type == ProbeRequestType:PrbRepl) {
510 trigger(Event:ForceRepl, in_msg.addr, cache_entry, tbe);
511 } else if (in_msg.Type == ProbeRequestType:PrbRegDowngrade) {
512 trigger(Event:ForceDowngrade, in_msg.addr, cache_entry, tbe);
514 error("Unknown probe request");
522 in_port(responseToCore_in, ResponseMsg, responseToCore) {
523 if (responseToCore_in.isReady(clockEdge())) {
524 peek(responseToCore_in, ResponseMsg, block_on="addr") {
526 Entry cache_entry := getCacheEntry(in_msg.addr);
527 TBE tbe := TBEs.lookup(in_msg.addr);
529 if (in_msg.Type == CoherenceResponseType:NBSysResp) {
530 if (in_msg.State == CoherenceState:Modified) {
531 trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe);
532 } else if (in_msg.State == CoherenceState:Shared) {
533 trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe);
534 } else if (in_msg.State == CoherenceState:Exclusive) {
535 trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe);
537 } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
538 trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe);
540 error("Unexpected Response Message to Core");
546 // Nothing from the Unblock Network
549 in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
550 if (mandatoryQueue_in.isReady(clockEdge())) {
551 peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
553 Entry cache_entry := getCacheEntry(in_msg.LineAddress);
554 TBE tbe := TBEs.lookup(in_msg.LineAddress);
556 if (in_msg.Type == RubyRequestType:IFETCH) {
559 if (L1Icache.isTagPresent(in_msg.LineAddress)) {
560 if (mod(in_msg.contextId, 2) == 0) {
561 trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe);
563 trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe);
566 if (presentOrAvail2(in_msg.LineAddress)) {
567 if (presentOrAvailI(in_msg.LineAddress)) {
568 if (mod(in_msg.contextId, 2) == 0) {
569 trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry,
572 trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry,
576 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
577 trigger(Event:L1I_Repl, victim,
578 getCacheEntry(victim), TBEs.lookup(victim));
580 } else { // Not present or avail in L2
581 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
582 DPRINTF(RubySlicc, "Victim for %s L2_Repl(0) is %s\n", in_msg.LineAddress, victim);
583 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
584 TBEs.lookup(victim));
589 if (mod(in_msg.contextId, 2) == 1) {
590 if (L1D1cache.isTagPresent(in_msg.LineAddress)) {
591 if (in_msg.Type == RubyRequestType:LD) {
592 trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry,
595 // Stores must write through, make sure L2 avail.
596 if (presentOrAvail2(in_msg.LineAddress)) {
597 trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry,
600 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
601 DPRINTF(RubySlicc, "Victim for %s L2_Repl(1) is %s\n", in_msg.LineAddress, victim);
602 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
603 TBEs.lookup(victim));
607 if (presentOrAvail2(in_msg.LineAddress)) {
608 if (presentOrAvailD1(in_msg.LineAddress)) {
609 if (in_msg.Type == RubyRequestType:LD) {
610 trigger(Event:C1_Load_L1miss, in_msg.LineAddress,
613 trigger(Event:C1_Store_L1miss, in_msg.LineAddress,
617 Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
618 DPRINTF(RubySlicc, "Victim for %s L1D1_Repl is %s\n", in_msg.LineAddress, victim);
619 trigger(Event:L1D1_Repl, victim,
620 getCacheEntry(victim), TBEs.lookup(victim));
622 } else { // not present or avail in L2
623 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
624 DPRINTF(RubySlicc, "Victim for %s L2_Repl(2) is %s\n", in_msg.LineAddress, victim);
625 trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
629 Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0);
630 if (is_valid(L1D0cache_entry)) {
631 if (in_msg.Type == RubyRequestType:LD) {
632 trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry,
635 if (presentOrAvail2(in_msg.LineAddress)) {
636 trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry,
639 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
640 DPRINTF(RubySlicc, "Victim for %s L2_Repl(3) is %s\n", in_msg.LineAddress, victim);
641 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
642 TBEs.lookup(victim));
646 if (presentOrAvail2(in_msg.LineAddress)) {
647 if (presentOrAvailD0(in_msg.LineAddress)) {
648 if (in_msg.Type == RubyRequestType:LD) {
649 trigger(Event:C0_Load_L1miss, in_msg.LineAddress,
652 trigger(Event:C0_Store_L1miss, in_msg.LineAddress,
656 Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
657 DPRINTF(RubySlicc, "Victim for %s L1D0_Repl is %s\n", in_msg.LineAddress, victim);
658 trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
659 TBEs.lookup(victim));
662 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
663 DPRINTF(RubySlicc, "Victim for %s L2_Repl(4) is %s\n", in_msg.LineAddress, victim);
664 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
665 TBEs.lookup(victim));
676 action(ii_invIcache, "ii", desc="invalidate iCache") {
677 if (L1Icache.isTagPresent(address)) {
678 L1Icache.deallocate(address);
682 action(i0_invCluster, "i0", desc="invalidate cluster 0") {
683 if (L1D0cache.isTagPresent(address)) {
684 L1D0cache.deallocate(address);
688 action(i1_invCluster, "i1", desc="invalidate cluster 1") {
689 if (L1D1cache.isTagPresent(address)) {
690 L1D1cache.deallocate(address);
694 action(ib_invBothClusters, "ib", desc="invalidate both clusters") {
695 if (L1D0cache.isTagPresent(address)) {
696 L1D0cache.deallocate(address);
698 if (L1D1cache.isTagPresent(address)) {
699 L1D1cache.deallocate(address);
703 action(i2_invL2, "i2", desc="invalidate L2") {
704 if(is_valid(cache_entry)) {
705 L2cache.deallocate(address);
710 action(n_issueRdBlk, "n", desc="Issue RdBlk") {
711 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
712 out_msg.addr := address;
713 out_msg.Type := CoherenceRequestType:RdBlk;
714 out_msg.Requestor := machineID;
715 out_msg.Destination.add(getPeer(machineID));
716 out_msg.MessageSize := MessageSizeType:Request_Control;
717 out_msg.InitialRequestTime := curCycle();
721 action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") {
722 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
723 out_msg.addr := address;
724 out_msg.Type := CoherenceRequestType:RdBlkM;
725 out_msg.Requestor := machineID;
726 out_msg.Destination.add(getPeer(machineID));
727 out_msg.MessageSize := MessageSizeType:Request_Control;
728 out_msg.InitialRequestTime := curCycle();
732 action(nMs_issueRdBlkMSinked, "nMs", desc="Issue RdBlkM with CtoDSinked") {
733 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
734 out_msg.addr := address;
735 out_msg.Type := CoherenceRequestType:RdBlkM;
736 out_msg.Requestor := machineID;
737 out_msg.Destination.add(getPeer(machineID));
738 out_msg.MessageSize := MessageSizeType:Request_Control;
739 out_msg.CtoDSinked := true;
743 action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
744 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
745 out_msg.addr := address;
746 out_msg.Type := CoherenceRequestType:RdBlkS;
747 out_msg.Requestor := machineID;
748 out_msg.Destination.add(getPeer(machineID));
749 out_msg.MessageSize := MessageSizeType:Request_Control;
750 out_msg.InitialRequestTime := curCycle();
754 action(nSs_issueRdBlkSSinked, "nSs", desc="Issue RdBlkS with CtoDSinked") {
755 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
756 out_msg.addr := address;
757 out_msg.Type := CoherenceRequestType:RdBlkS;
758 out_msg.Requestor := machineID;
759 out_msg.Destination.add(getPeer(machineID));
760 out_msg.CtoDSinked := true;
761 out_msg.MessageSize := MessageSizeType:Request_Control;
765 action(vd_victim, "vd", desc="Victimize M/O L2 Data") {
766 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
767 out_msg.addr := address;
768 out_msg.Requestor := machineID;
769 assert(is_valid(cache_entry));
770 out_msg.DataBlk := cache_entry.DataBlk;
771 assert(cache_entry.Dirty);
772 out_msg.Destination.add(getPeer(machineID));
773 out_msg.MessageSize := MessageSizeType:Request_Control;
774 out_msg.Type := CoherenceRequestType:VicDirty;
775 out_msg.InitialRequestTime := curCycle();
776 if (cache_entry.CacheState == State:O) {
777 out_msg.Shared := true;
779 out_msg.Shared := false;
784 action(vc_victim, "vc", desc="Victimize E/S L2 Data") {
785 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
786 out_msg.addr := address;
787 out_msg.Requestor := machineID;
788 out_msg.Destination.add(getPeer(machineID));
789 out_msg.MessageSize := MessageSizeType:Request_Control;
790 out_msg.Type := CoherenceRequestType:VicClean;
791 out_msg.InitialRequestTime := curCycle();
792 if (cache_entry.CacheState == State:S) {
793 out_msg.Shared := true;
795 out_msg.Shared := false;
800 // Could send these two directly to dir if we made a new out network on channel 0
801 action(vdf_victimForce, "vdf", desc="Victimize M/O L2 Data") {
802 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
803 out_msg.addr := address;
804 out_msg.Requestor := machineID;
805 assert(is_valid(cache_entry));
806 out_msg.DataBlk := cache_entry.DataBlk;
807 assert(cache_entry.Dirty);
808 out_msg.Destination.add(getPeer(machineID));
809 out_msg.MessageSize := MessageSizeType:Request_Control;
810 out_msg.Type := CoherenceRequestType:VicDirty;
811 out_msg.InitialRequestTime := curCycle();
812 if (cache_entry.CacheState == State:O) {
813 out_msg.Shared := true;
815 out_msg.Shared := false;
817 out_msg.Private := true;
821 action(vcf_victimForce, "vcf", desc="Victimize E/S L2 Data") {
822 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
823 out_msg.addr := address;
824 out_msg.Requestor := machineID;
825 out_msg.Destination.add(getPeer(machineID));
826 out_msg.MessageSize := MessageSizeType:Request_Control;
827 out_msg.Type := CoherenceRequestType:VicClean;
828 out_msg.InitialRequestTime := curCycle();
829 if (cache_entry.CacheState == State:S) {
830 out_msg.Shared := true;
832 out_msg.Shared := false;
834 out_msg.Private := true;
838 action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
839 if (L1D0cache.isTagPresent(address) == false) {
840 L1D0cache.allocateVoid(address, new Entry);
844 action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
845 if (L1D1cache.isTagPresent(address) == false) {
846 L1D1cache.allocateVoid(address, new Entry);
850 action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
851 if (L1Icache.isTagPresent(address) == false) {
852 L1Icache.allocateVoid(address, new Entry);
856 action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
857 if (is_invalid(cache_entry)) {
858 set_cache_entry(L2cache.allocate(address, new Entry));
862 action(t_allocateTBE, "t", desc="allocate TBE Entry") {
863 check_allocate(TBEs);
864 assert(is_valid(cache_entry));
865 TBEs.allocate(address);
866 set_tbe(TBEs.lookup(address));
867 tbe.DataBlk := cache_entry.DataBlk; // Data only used for WBs
868 tbe.Dirty := cache_entry.Dirty;
872 action(d_deallocateTBE, "d", desc="Deallocate TBE") {
873 TBEs.deallocate(address);
877 action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
878 mandatoryQueue_in.dequeue(clockEdge());
881 action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
882 responseToCore_in.dequeue(clockEdge());
885 action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") {
886 triggerQueue_in.dequeue(clockEdge());
889 action(pp_popProbeQueue, "pp", desc="pop probe queue") {
890 probeNetwork_in.dequeue(clockEdge());
893 action(il0_loadDone, "il0", desc="Cluster 0 i load done") {
894 Entry entry := getICacheEntry(address);
895 Entry l2entry := getCacheEntry(address); // Used for functional accesses
896 assert(is_valid(entry));
897 // L2 supplies data (functional accesses only look in L2, ok because L1
898 // writes through to L2)
899 sequencer.readCallback(address,
902 testAndClearLocalHit(entry));
905 action(il1_loadDone, "il1", desc="Cluster 1 i load done") {
906 Entry entry := getICacheEntry(address);
907 Entry l2entry := getCacheEntry(address); // Used for functional accesses
908 assert(is_valid(entry));
909 // L2 supplies data (functional accesses only look in L2, ok because L1
910 // writes through to L2)
911 sequencer1.readCallback(address,
914 testAndClearLocalHit(entry));
917 action(l0_loadDone, "l0", desc="Cluster 0 load done") {
918 Entry entry := getL1CacheEntry(address, 0);
919 Entry l2entry := getCacheEntry(address); // Used for functional accesses
920 assert(is_valid(entry));
921 // L2 supplies data (functional accesses only look in L2, ok because L1
922 // writes through to L2)
923 sequencer.readCallback(address,
926 testAndClearLocalHit(entry));
929 action(l1_loadDone, "l1", desc="Cluster 1 load done") {
930 Entry entry := getL1CacheEntry(address, 1);
931 Entry l2entry := getCacheEntry(address); // Used for functional accesses
932 assert(is_valid(entry));
933 // L2 supplies data (functional accesses only look in L2, ok because L1
934 // writes through to L2)
935 sequencer1.readCallback(address,
938 testAndClearLocalHit(entry));
941 action(xl0_loadDone, "xl0", desc="Cluster 0 load done") {
942 peek(responseToCore_in, ResponseMsg) {
943 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
944 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
945 Entry l2entry := getCacheEntry(address); // Used for functional accesses
946 DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n",
947 address, l2entry.DataBlk);
948 // L2 supplies data (functional accesses only look in L2, ok because L1
949 // writes through to L2)
950 assert(is_valid(l2entry));
951 sequencer.readCallback(address,
954 machineIDToMachineType(in_msg.Sender),
955 in_msg.InitialRequestTime,
956 in_msg.ForwardRequestTime,
957 in_msg.ProbeRequestStartTime);
961 action(xl1_loadDone, "xl1", desc="Cluster 1 load done") {
962 peek(responseToCore_in, ResponseMsg) {
963 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
964 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
965 Entry l2entry := getCacheEntry(address); // Used for functional accesses
966 // L2 supplies data (functional accesses only look in L2, ok because L1
967 // writes through to L2)
968 assert(is_valid(l2entry));
969 sequencer1.readCallback(address,
972 machineIDToMachineType(in_msg.Sender),
973 in_msg.InitialRequestTime,
974 in_msg.ForwardRequestTime,
975 in_msg.ProbeRequestStartTime);
979 action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") {
980 peek(responseToCore_in, ResponseMsg) {
981 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
982 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
983 Entry l2entry := getCacheEntry(address); // Used for functional accesses
984 // L2 supplies data (functional accesses only look in L2, ok because L1
985 // writes through to L2)
986 assert(is_valid(l2entry));
987 sequencer.readCallback(address,
990 machineIDToMachineType(in_msg.Sender),
991 in_msg.InitialRequestTime,
992 in_msg.ForwardRequestTime,
993 in_msg.ProbeRequestStartTime);
997 action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") {
998 peek(responseToCore_in, ResponseMsg) {
999 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1000 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1001 Entry l2entry := getCacheEntry(address); // Used for functional accesses
1002 // L2 supplies data (functional accesses only look in L2, ok because L1
1003 // writes through to L2)
1004 assert(is_valid(l2entry));
1005 sequencer1.readCallback(address,
1008 machineIDToMachineType(in_msg.Sender),
1009 in_msg.InitialRequestTime,
1010 in_msg.ForwardRequestTime,
1011 in_msg.ProbeRequestStartTime);
1015 action(s0_storeDone, "s0", desc="Cluster 0 store done") {
1016 Entry entry := getL1CacheEntry(address, 0);
1017 assert(is_valid(entry));
1018 assert(is_valid(cache_entry));
1019 sequencer.writeCallback(address,
1020 cache_entry.DataBlk,
1022 testAndClearLocalHit(entry));
1023 cache_entry.Dirty := true;
1024 entry.DataBlk := cache_entry.DataBlk;
1025 entry.Dirty := true;
1026 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1029 action(s1_storeDone, "s1", desc="Cluster 1 store done") {
1030 Entry entry := getL1CacheEntry(address, 1);
1031 assert(is_valid(entry));
1032 assert(is_valid(cache_entry));
1033 sequencer1.writeCallback(address,
1034 cache_entry.DataBlk,
1036 testAndClearLocalHit(entry));
1037 cache_entry.Dirty := true;
1038 entry.Dirty := true;
1039 entry.DataBlk := cache_entry.DataBlk;
1040 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1043 action(xs0_storeDone, "xs0", desc="Cluster 0 store done") {
1044 peek(responseToCore_in, ResponseMsg) {
1045 Entry entry := getL1CacheEntry(address, 0);
1046 assert(is_valid(entry));
1047 assert(is_valid(cache_entry));
1048 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1049 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1050 sequencer.writeCallback(address,
1051 cache_entry.DataBlk,
1053 machineIDToMachineType(in_msg.Sender),
1054 in_msg.InitialRequestTime,
1055 in_msg.ForwardRequestTime,
1056 in_msg.ProbeRequestStartTime);
1057 cache_entry.Dirty := true;
1058 entry.Dirty := true;
1059 entry.DataBlk := cache_entry.DataBlk;
1060 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1064 action(xs1_storeDone, "xs1", desc="Cluster 1 store done") {
1065 peek(responseToCore_in, ResponseMsg) {
1066 Entry entry := getL1CacheEntry(address, 1);
1067 assert(is_valid(entry));
1068 assert(is_valid(cache_entry));
1069 assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1070 (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1071 sequencer1.writeCallback(address,
1072 cache_entry.DataBlk,
1074 machineIDToMachineType(in_msg.Sender),
1075 in_msg.InitialRequestTime,
1076 in_msg.ForwardRequestTime,
1077 in_msg.ProbeRequestStartTime);
1078 cache_entry.Dirty := true;
1079 entry.Dirty := true;
1080 entry.DataBlk := cache_entry.DataBlk;
1081 DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1085 action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") {
1086 if (send_evictions) {
1087 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1088 sequencer.evictionCallback(address);
1092 action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") {
1093 if (send_evictions) {
1094 DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1095 sequencer1.evictionCallback(address);
1099 action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") {
1100 Entry entry := getICacheEntry(address);
1101 assert(is_valid(entry));
1102 assert(is_valid(cache_entry));
1103 entry.Dirty := cache_entry.Dirty;
1104 entry.DataBlk := cache_entry.DataBlk;
1105 entry.FromL2 := true;
1108 action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") {
1109 Entry entry := getL1CacheEntry(address, 0);
1110 assert(is_valid(entry));
1111 assert(is_valid(cache_entry));
1112 entry.Dirty := cache_entry.Dirty;
1113 entry.DataBlk := cache_entry.DataBlk;
1114 entry.FromL2 := true;
1117 action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
1118 peek(responseToCore_in, ResponseMsg) {
1119 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1120 out_msg.addr := address;
1121 out_msg.Type := CoherenceResponseType:StaleNotif;
1122 out_msg.Sender := machineID;
1123 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1124 out_msg.MessageSize := MessageSizeType:Response_Control;
1125 DPRINTF(RubySlicc, "%s\n", out_msg);
1130 action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") {
1131 Entry entry := getL1CacheEntry(address, 1);
1132 assert(is_valid(entry));
1133 assert(is_valid(cache_entry));
1134 entry.Dirty := cache_entry.Dirty;
1135 entry.DataBlk := cache_entry.DataBlk;
1136 entry.FromL2 := true;
1139 action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") {
1140 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1141 out_msg.addr := address;
1142 out_msg.Type := TriggerType:L2_to_L1;
1143 out_msg.Dest := CacheId:L1I;
1147 action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") {
1148 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1149 out_msg.addr := address;
1150 out_msg.Type := TriggerType:L2_to_L1;
1151 out_msg.Dest := CacheId:L1D0;
1155 action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") {
1156 enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1157 out_msg.addr := address;
1158 out_msg.Type := TriggerType:L2_to_L1;
1159 out_msg.Dest := CacheId:L1D1;
1163 action(wi_writeIcache, "wi", desc="write data to icache (and l2)") {
1164 peek(responseToCore_in, ResponseMsg) {
1165 Entry entry := getICacheEntry(address);
1166 assert(is_valid(entry));
1167 assert(is_valid(cache_entry));
1168 entry.DataBlk := in_msg.DataBlk;
1169 entry.Dirty := in_msg.Dirty;
1170 cache_entry.DataBlk := in_msg.DataBlk;
1171 cache_entry.Dirty := in_msg.Dirty;
1175 action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") {
1176 peek(responseToCore_in, ResponseMsg) {
1177 Entry entry := getL1CacheEntry(address, 0);
1178 assert(is_valid(entry));
1179 assert(is_valid(cache_entry));
1180 entry.DataBlk := in_msg.DataBlk;
1181 entry.Dirty := in_msg.Dirty;
1182 cache_entry.DataBlk := in_msg.DataBlk;
1183 cache_entry.Dirty := in_msg.Dirty;
1187 action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") {
1188 peek(responseToCore_in, ResponseMsg) {
1189 Entry entry := getL1CacheEntry(address, 1);
1190 assert(is_valid(entry));
1191 assert(is_valid(cache_entry));
1192 entry.DataBlk := in_msg.DataBlk;
1193 entry.Dirty := in_msg.Dirty;
1194 cache_entry.DataBlk := in_msg.DataBlk;
1195 cache_entry.Dirty := in_msg.Dirty;
1199 action(wb_data, "wb", desc="write back data") {
1200 peek(responseToCore_in, ResponseMsg) {
1201 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1202 out_msg.addr := address;
1203 out_msg.Type := CoherenceResponseType:CPUData;
1204 out_msg.Sender := machineID;
1205 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1206 out_msg.DataBlk := tbe.DataBlk;
1207 out_msg.Dirty := tbe.Dirty;
1209 out_msg.NbReqShared := true;
1211 out_msg.NbReqShared := false;
1213 out_msg.State := CoherenceState:Shared; // faux info
1214 out_msg.MessageSize := MessageSizeType:Writeback_Data;
1215 DPRINTF(RubySlicc, "%s\n", out_msg);
1220 action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
1221 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1222 out_msg.addr := address;
1223 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
1224 out_msg.Sender := machineID;
1225 // will this always be ok? probably not for multisocket
1226 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1227 out_msg.Dirty := false;
1228 out_msg.Hit := false;
1229 out_msg.Ntsl := true;
1230 out_msg.State := CoherenceState:NA;
1231 out_msg.MessageSize := MessageSizeType:Response_Control;
1232 out_msg.isValid := isValid(address);
1236 action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
1237 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1238 out_msg.addr := address;
1239 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
1240 out_msg.Sender := machineID;
1241 // will this always be ok? probably not for multisocket
1242 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1243 out_msg.Dirty := false;
1244 out_msg.Ntsl := true;
1245 out_msg.Hit := false;
1246 APPEND_TRANSITION_COMMENT("Setting Ms");
1247 out_msg.State := CoherenceState:NA;
1248 out_msg.MessageSize := MessageSizeType:Response_Control;
1249 out_msg.isValid := isValid(address);
1253 action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") {
1254 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1255 out_msg.addr := address;
1256 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
1257 out_msg.Sender := machineID;
1258 // will this always be ok? probably not for multisocket
1259 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1260 assert(addressInCore(address) || is_valid(tbe));
1261 out_msg.Dirty := false; // only true if sending back data i think
1262 out_msg.Hit := true;
1263 out_msg.Ntsl := false;
1264 out_msg.State := CoherenceState:NA;
1265 out_msg.MessageSize := MessageSizeType:Response_Control;
1266 out_msg.isValid := isValid(address);
1270 action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") {
1271 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1272 out_msg.addr := address;
1273 out_msg.Type := CoherenceResponseType:CPUPrbResp; // L3 and CPUs respond in same way to probes
1274 out_msg.Sender := machineID;
1275 // will this always be ok? probably not for multisocket
1276 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1277 if (addressInCore(address)) {
1278 out_msg.Hit := true;
1280 out_msg.Hit := false;
1282 out_msg.Dirty := false; // not sending back data, so def. not dirty
1283 out_msg.Ntsl := false;
1284 out_msg.State := CoherenceState:NA;
1285 out_msg.MessageSize := MessageSizeType:Response_Control;
1286 out_msg.isValid := isValid(address);
1290 action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
1291 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1292 assert(is_valid(cache_entry));
1293 out_msg.addr := address;
1294 out_msg.Type := CoherenceResponseType:CPUPrbResp;
1295 out_msg.Sender := machineID;
1296 // will this always be ok? probably not for multisocket
1297 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1298 out_msg.DataBlk := cache_entry.DataBlk;
1299 assert(cache_entry.Dirty);
1300 out_msg.Dirty := true;
1301 out_msg.Hit := true;
1302 out_msg.State := CoherenceState:NA;
1303 out_msg.MessageSize := MessageSizeType:Response_Data;
1304 out_msg.isValid := isValid(address);
1308 action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
1309 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1310 assert(is_valid(cache_entry));
1311 out_msg.addr := address;
1312 out_msg.Type := CoherenceResponseType:CPUPrbResp;
1313 out_msg.Sender := machineID;
1314 // will this always be ok? probably not for multisocket
1315 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1316 out_msg.DataBlk := cache_entry.DataBlk;
1317 assert(cache_entry.Dirty);
1318 out_msg.Dirty := true;
1319 out_msg.Hit := true;
1320 APPEND_TRANSITION_COMMENT("Setting Ms");
1321 out_msg.State := CoherenceState:NA;
1322 out_msg.MessageSize := MessageSizeType:Response_Data;
1323 out_msg.isValid := isValid(address);
1327 action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
1328 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1329 assert(is_valid(tbe));
1330 out_msg.addr := address;
1331 out_msg.Type := CoherenceResponseType:CPUPrbResp;
1332 out_msg.Sender := machineID;
1333 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1334 out_msg.DataBlk := tbe.DataBlk;
1336 out_msg.Dirty := true;
1337 out_msg.Hit := true;
1338 out_msg.State := CoherenceState:NA;
1339 out_msg.MessageSize := MessageSizeType:Response_Data;
1340 out_msg.isValid := isValid(address);
1344 action(ra_sendReplAck, "ra", desc="Send ack to r-buf that line is replaced if needed") {
1345 if (is_invalid(tbe) || tbe.AckNeeded) {
1346 enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
1347 out_msg.addr := address;
1348 out_msg.Type := CoherenceRequestType:InvAck;
1349 out_msg.Requestor := machineID;
1350 out_msg.Destination.add(getPeer(machineID));
1351 out_msg.MessageSize := MessageSizeType:Request_Control;
1353 APPEND_TRANSITION_COMMENT(" Sending ack to r-buf ");
1355 APPEND_TRANSITION_COMMENT(" NOT Sending ack to r-buf ");
1359 action(m_markAckNeeded, "m", desc="Mark TBE to send ack when deallocated") {
1360 assert(is_valid(tbe));
1361 tbe.AckNeeded := true;
1364 action(mc_cancelWB, "mc", desc="send writeback cancel to L3") {
1365 enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1366 out_msg.addr := address;
1367 out_msg.Type := CoherenceResponseType:CPUCancelWB;
1368 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1369 out_msg.Sender := machineID;
1370 out_msg.MessageSize := MessageSizeType:Response_Control;
1374 action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") {
1375 assert(is_valid(tbe));
1379 action(uu_sendUnblock, "uu", desc="state changed, unblock") {
1380 enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
1381 out_msg.addr := address;
1382 out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
1383 out_msg.MessageSize := MessageSizeType:Unblock_Control;
1384 out_msg.wasValid := isValid(address);
1385 DPRINTF(RubySlicc, "%s\n", out_msg);
1389 action(sdv_sendDoneValid, "sdv", desc="Request finished, send done ack") {
1390 enqueue(unblockNetwork_out, UnblockMsg, 1) {
1391 out_msg.addr := address;
1392 out_msg.Destination.add(getPeer(machineID));
1393 out_msg.DoneAck := true;
1394 out_msg.MessageSize := MessageSizeType:Unblock_Control;
1395 if (is_valid(tbe)) {
1396 out_msg.Dirty := tbe.Dirty;
1397 } else if (is_valid(cache_entry)) {
1398 out_msg.Dirty := cache_entry.Dirty;
1400 out_msg.Dirty := false;
1402 out_msg.validToInvalid := false;
1403 DPRINTF(RubySlicc, "%s\n", out_msg);
1407 action(sdi_sendDoneInvalid, "sdi", desc="Request finished, send done ack") {
1408 enqueue(unblockNetwork_out, UnblockMsg, 1) {
1409 out_msg.addr := address;
1410 out_msg.Destination.add(getPeer(machineID));
1411 out_msg.DoneAck := true;
1412 out_msg.MessageSize := MessageSizeType:Unblock_Control;
1413 if (is_valid(tbe)) {
1414 out_msg.Dirty := tbe.Dirty;
1415 } else if (is_valid(cache_entry)) {
1416 out_msg.Dirty := cache_entry.Dirty;
1418 out_msg.Dirty := false;
1420 out_msg.validToInvalid := true;
1421 DPRINTF(RubySlicc, "%s\n", out_msg);
1425 action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
1426 ++L1D0cache.demand_misses;
1429 action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
1430 ++L1D1cache.demand_misses;
1433 action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
1434 ++L1Icache.demand_misses;
1437 action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
1438 ++L2cache.demand_misses;
1441 action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
1442 probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1445 action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
1446 mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1450 // BEGIN TRANSITIONS
1452 // transitions from base
1453 transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} {
1454 // track misses, if implemented
1455 // since in I state, L2 miss as well
1464 p_popMandatoryQueue;
1467 transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} {
1468 // track misses, if implemented
1469 // since in I state, L2 miss as well
1477 p_popMandatoryQueue;
1480 transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1481 // track misses, if implemented
1490 p_popMandatoryQueue;
1493 transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1495 // track misses, if implemented
1503 p_popMandatoryQueue;
1506 transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead,L2TagArrayRead} {
1514 p_popMandatoryQueue;
1517 transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} {
1525 p_popMandatoryQueue;
1528 transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1532 p_popMandatoryQueue;
1535 transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1539 p_popMandatoryQueue;
1542 transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1546 p_popMandatoryQueue;
1549 transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1553 p_popMandatoryQueue;
1556 transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead}{
1563 p_popMandatoryQueue;
1566 transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead,L2TagArrayRead} {
1573 p_popMandatoryQueue;
1575 transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} { // can this be folded with S_F?
1579 p_popMandatoryQueue;
1582 transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} { // can this be folded with S_F?
1586 p_popMandatoryQueue;
1589 transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1596 p_popMandatoryQueue;
1599 transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1606 p_popMandatoryQueue;
1609 // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW
1610 transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayWrite,L1D0TagArrayRead, L2TagArrayRead, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1613 s0_storeDone; // instantaneous L1/L2 dirty - no writethrough delay
1614 p_popMandatoryQueue;
1617 transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1621 p_popMandatoryQueue;
1624 transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1628 p_popMandatoryQueue;
1631 transition(E0, C1_Load_L1miss, E0_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1635 p_popMandatoryQueue;
1638 transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1639 l2m_profileMiss; // permissions miss, still issue RdBlkS
1646 p_popMandatoryQueue;
1649 transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead } {
1650 l2m_profileMiss; // permissions miss, still issue RdBlkS
1657 p_popMandatoryQueue;
1660 transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1663 p_popMandatoryQueue;
1666 transition(E0, C1_Store_L1miss, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1671 p_popMandatoryQueue;
1674 transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1678 p_popMandatoryQueue;
1681 transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1685 p_popMandatoryQueue;
1688 transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} {
1689 l2m_profileMiss; // permissions miss, still issue RdBlkS
1696 p_popMandatoryQueue;
1699 transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead,L1ITagArrayRead} {
1700 l2m_profileMiss; // permissions miss, still issue RdBlkS
1707 p_popMandatoryQueue;
1710 transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1713 p_popMandatoryQueue;
1716 transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1721 p_popMandatoryQueue;
1724 transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1725 l2m_profileMiss; // permissions miss, still issue CtoD
1731 p_popMandatoryQueue;
1734 transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1735 l2m_profileMiss; // permissions miss, still issue RdBlkS
1741 p_popMandatoryQueue;
1744 transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1748 p_popMandatoryQueue;
1751 transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1755 p_popMandatoryQueue;
1758 transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1762 p_popMandatoryQueue;
1765 transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1769 p_popMandatoryQueue;
1772 transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead, L2TagArrayRead} {
1773 l2m_profileMiss; // permissions miss
1780 p_popMandatoryQueue;
1783 transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead L2TagArrayRead } {
1784 l2m_profileMiss; // permissions miss
1791 p_popMandatoryQueue;
1794 transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1798 p_popMandatoryQueue;
1801 transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1805 p_popMandatoryQueue;
1808 transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1812 p_popMandatoryQueue;
1815 transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D1TagArrayRead} {
1819 p_popMandatoryQueue;
1822 transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} {
1825 p_popMandatoryQueue;
1828 transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1832 p_popMandatoryQueue;
1835 transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1839 p_popMandatoryQueue;
1842 transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead L2TagArrayRead, L2DataArrayRead} {
1846 p_popMandatoryQueue;
1849 transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1853 p_popMandatoryQueue;
1856 transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite} {
1859 p_popMandatoryQueue;
1862 // end transitions from base
1864 // Begin simple hit transitions
1865 transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es,
1866 Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} {
1867 // track hits, if implemented
1869 p_popMandatoryQueue;
1872 transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es,
1873 Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} {
1874 // track hits, if implemented
1876 p_popMandatoryQueue;
1879 transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} {
1880 // track hits, if implemented
1882 p_popMandatoryQueue;
1885 transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} {
1886 // track hits, if implemented
1888 p_popMandatoryQueue;
1891 // end simple hit transitions
1893 // Transitions from transient states
1896 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1897 IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1898 E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} {
1899 zz_recycleMandatoryQueue;
1902 transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1,
1903 O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} {
1904 zz_recycleMandatoryQueue;
1907 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1908 IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1909 E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} {
1910 zz_recycleMandatoryQueue;
1913 transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0,
1914 O_M0, S0, S1, I_C, S0_C, S1_C, S_C}, C1_Load_L1miss) {} {
1915 zz_recycleMandatoryQueue;
1918 transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} {
1919 zz_recycleMandatoryQueue;
1922 transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES,
1923 IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F,
1924 O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F,
1925 E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C,
1926 S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} {
1927 zz_recycleMandatoryQueue;
1930 transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1,
1931 Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms,
1932 M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} {
1933 zz_recycleMandatoryQueue;
1936 transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0,
1937 Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F,
1938 M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} {
1939 zz_recycleMandatoryQueue;
1942 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1943 IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} {
1944 zz_recycleMandatoryQueue;
1947 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1948 IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1,
1949 O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F,
1950 M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} {
1951 zz_recycleMandatoryQueue;
1954 transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1955 IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1956 E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} {
1957 zz_recycleMandatoryQueue;
1960 transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1961 IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1962 E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} {
1963 zz_recycleMandatoryQueue;
1966 transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} {
1967 zz_recycleMandatoryQueue;
1970 transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} {
1971 zz_recycleMandatoryQueue;
1974 transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS,
1975 PrbInvData, PrbInvDataDemand, PrbInv, PrbShrData, PrbShrDataDemand}) {} {
1976 zz_recycleMandatoryQueue; // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1979 transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} {
1980 zz_recycleMandatoryQueue; // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1983 transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} {
1987 p_popMandatoryQueue;
1990 transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} {
1994 p_popMandatoryQueue;
1997 transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} {
2001 p_popMandatoryQueue;
2004 transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} {
2008 p_popMandatoryQueue;
2011 transition(I_M0, C1_Load_L1miss, I_M0Ms){
2015 p_popMandatoryQueue;
2018 transition(I_M1, C0_Load_L1miss, I_M1Ms){
2022 p_popMandatoryQueue;
2025 transition(I_M0, C1_Store_L1miss, I_M0M1) {
2029 p_popMandatoryQueue;
2032 transition(I_M1, C0_Store_L1miss, I_M1M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
2035 p_popMandatoryQueue;
2038 transition(I_E0S, C1_Load_L1miss, I_ES) {} {
2042 p_popMandatoryQueue;
2045 transition(I_E1S, C0_Load_L1miss, I_ES) {} {
2050 p_popMandatoryQueue;
2053 transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} {
2057 p_popMandatoryQueue;
2060 transition(S_F0, C1_Load_L1miss, S_F) { L2DataArrayRead} {
2064 p_popMandatoryQueue;
2067 transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} {
2071 p_popMandatoryQueue;
2074 transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) {L2DataArrayRead} {
2078 p_popMandatoryQueue;
2081 transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} {
2085 transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} {
2089 transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} {
2093 transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead,L1D0TagArrayRead, L1D1TagArrayRead, L1ITagArrayRead} {
2094 forward_eviction_to_cpu0;
2095 forward_eviction_to_cpu1;
2103 transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayRead, L1D1TagArrayRead} {
2104 forward_eviction_to_cpu0;
2105 forward_eviction_to_cpu1;
2109 ib_invBothClusters; // nothing will happen for D0 on M1, vice versa
2112 transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2117 pr_popResponseQueue;
2120 transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2125 pr_popResponseQueue;
2128 transition(S0_C, NB_AckS, S_C) { L1IDataArrayWrite,L2DataArrayWrite} {
2129 // does not need send done since the rdblks was "sinked"
2133 pr_popResponseQueue;
2136 transition(S1_C, NB_AckS, S_C) { L1D1DataArrayWrite,L2DataArrayWrite} {
2140 pr_popResponseQueue;
2143 transition(I_M0, NB_AckM, M0) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2148 pr_popResponseQueue;
2151 transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2156 pr_popResponseQueue;
2159 // THESE MO->M1 should not be instantaneous but oh well for now.
2160 transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2167 pr_popResponseQueue;
2170 transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2177 pr_popResponseQueue;
2180 // Above shoudl be more like this, which has some latency to xfer to L1
2181 transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} {
2187 pr_popResponseQueue;
2190 transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite,L2DataArrayWrite} {
2196 pr_popResponseQueue;
2199 transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2204 pr_popResponseQueue;
2207 transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2212 pr_popResponseQueue;
2215 transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } {
2222 pr_popResponseQueue;
2225 transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2230 pr_popResponseQueue;
2233 transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2238 pr_popResponseQueue;
2241 transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2248 pr_popResponseQueue;
2251 transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2257 transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2263 transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2269 transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2275 transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2281 transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2287 transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2293 transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2299 transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2305 transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2311 transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2317 transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2323 transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2329 transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2335 transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} {
2341 transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} {
2347 transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2353 transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2359 transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2365 transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2371 transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} {
2377 transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} {
2383 transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} {
2389 transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} {
2395 transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} {
2401 transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} {
2407 transition(IF_E0S, L2_to_L1D0, I_E0S) {} {
2411 transition(IF_E1S, L2_to_L1D1, I_E1S) {} {
2415 transition(IF_ES, L2_to_L1D0, IF1_ES) {} {
2419 transition(IF_ES, L2_to_L1D1, IF0_ES) {} {
2423 transition(IF0_ES, L2_to_L1D0, I_ES) {} {
2427 transition(IF1_ES, L2_to_L1D1, I_ES) {} {
2431 transition(F_S0, L2_to_L1I, S0) {} {
2435 transition(F_S1, L2_to_L1I, S1) {} {
2439 transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2443 pr_popResponseQueue;
2446 transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2450 pr_popResponseQueue;
2453 transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} {
2456 sdi_sendDoneInvalid;
2458 pr_popResponseQueue;
2461 transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} {
2464 sdi_sendDoneInvalid;
2466 pr_popResponseQueue;
2469 transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} {
2475 d_deallocateTBE; // FOO
2476 pr_popResponseQueue;
2479 transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} {
2485 d_deallocateTBE; // FOO
2486 pr_popResponseQueue;
2489 // Writeback cancel "ack"
2490 transition(I_C, NB_AckWB, I) {L2TagArrayWrite} {
2491 ss_sendStaleNotification;
2492 sdi_sendDoneInvalid;
2494 pr_popResponseQueue;
2497 transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} {
2498 ss_sendStaleNotification;
2500 pr_popResponseQueue;
2503 transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} {
2504 ss_sendStaleNotification;
2506 pr_popResponseQueue;
2509 transition(S_C, NB_AckWB, S) {L2TagArrayWrite} {
2510 ss_sendStaleNotification;
2512 pr_popResponseQueue;
2515 // Begin Probe Transitions
2517 transition({Ms, M0, M1, O}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2518 forward_eviction_to_cpu0;
2519 forward_eviction_to_cpu1;
2520 pd_sendProbeResponseData;
2526 transition({Es, E0, E1, S, I}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite} {
2527 forward_eviction_to_cpu0;
2528 forward_eviction_to_cpu1;
2529 pi_sendProbeResponseInv;
2532 ii_invIcache; // only relevant for S
2536 transition(S_C, {PrbInvData, PrbInvDataDemand}, I_C) {L2TagArrayWrite} {
2538 forward_eviction_to_cpu0;
2539 forward_eviction_to_cpu1;
2540 pi_sendProbeResponseInv;
2547 transition(I_C, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2548 pi_sendProbeResponseInv;
2553 transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} {
2554 forward_eviction_to_cpu0;
2555 forward_eviction_to_cpu1;
2556 pi_sendProbeResponseInv;
2557 i2_invL2; // nothing will happen in I
2563 transition(S_C, PrbInv, I_C) {L2TagArrayWrite} {
2565 forward_eviction_to_cpu0;
2566 forward_eviction_to_cpu1;
2567 pi_sendProbeResponseInv;
2574 transition(I_C, PrbInv, I_C) {} {
2575 pi_sendProbeResponseInv;
2581 transition({Ms, M0, M1, O}, {PrbShrData, PrbShrDataDemand}, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2582 pd_sendProbeResponseData;
2586 transition({Es, E0, E1, S}, {PrbShrData, PrbShrDataDemand}, S) {L2TagArrayRead, L2TagArrayWrite} {
2587 ph_sendProbeResponseHit;
2591 transition(S_C, {PrbShrData, PrbShrDataDemand}) {} {
2592 ph_sendProbeResponseHit;
2596 transition({I, I_C}, {PrbShrData, PrbShrDataDemand}) {L2TagArrayRead} {
2597 pb_sendProbeResponseBackprobe;
2601 transition({I_M0, I_E0S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2602 pi_sendProbeResponseInv;
2603 ib_invBothClusters; // must invalidate current data (only relevant for I_M0)
2604 a0_allocateL1D; // but make sure there is room for incoming data when it arrives
2608 transition({I_M1, I_E1S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2609 pi_sendProbeResponseInv;
2610 ib_invBothClusters; // must invalidate current data (only relevant for I_M1)
2611 a1_allocateL1D; // but make sure there is room for incoming data when it arrives
2615 transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbInvDataDemand, PrbShrData, PrbShrDataDemand}) {} {
2616 pi_sendProbeResponseInv;
2623 transition({I_M0, I_E0S, I_M1, I_E1S}, {PrbShrData, PrbShrDataDemand}) {} {
2624 pb_sendProbeResponseBackprobe;
2628 transition(ES_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2629 pi_sendProbeResponseInv;
2635 transition(MO_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2636 pdt_sendProbeResponseDataFromTBE;
2642 transition(MO_I, PrbInv, I_C) {} {
2643 pi_sendProbeResponseInv;
2649 transition(ES_I, PrbInv, I_C) {} {
2650 pi_sendProbeResponseInv;
2656 transition(ES_I, {PrbShrData, PrbShrDataDemand}, ES_I) {} {
2657 ph_sendProbeResponseHit;
2662 transition(MO_I, {PrbShrData, PrbShrDataDemand}, MO_I) {} {
2663 pdt_sendProbeResponseDataFromTBE;
2668 transition(MO_S0, {PrbInvData, PrbInvDataDemand}, S0_C) {L2TagArrayWrite} {
2669 forward_eviction_to_cpu0;
2670 forward_eviction_to_cpu1;
2671 pdt_sendProbeResponseDataFromTBE;
2679 transition(MO_S1, {PrbInvData, PrbInvDataDemand}, S1_C) {} {
2680 forward_eviction_to_cpu0;
2681 forward_eviction_to_cpu1;
2682 pdt_sendProbeResponseDataFromTBE;
2690 transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} {
2691 forward_eviction_to_cpu0;
2692 forward_eviction_to_cpu1;
2693 pi_sendProbeResponseInv;
2701 transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} {
2702 forward_eviction_to_cpu0;
2703 forward_eviction_to_cpu1;
2704 pi_sendProbeResponseInv;
2712 transition({MO_S0, MO_S1}, {PrbShrData, PrbShrDataDemand}) {} {
2713 pdt_sendProbeResponseDataFromTBE;
2718 transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E0S) {} {
2719 forward_eviction_to_cpu0;
2720 forward_eviction_to_cpu1;
2721 pi_sendProbeResponseInv;
2722 // invalidate everything you've got
2726 // but make sure you have room for what you need from the fill
2733 transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E1S) {} {
2734 forward_eviction_to_cpu0;
2735 forward_eviction_to_cpu1;
2736 pi_sendProbeResponseInv;
2737 // invalidate everything you've got
2741 // but make sure you have room for what you need from the fill
2748 transition({S_F, Es_F}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_ES) {} {
2749 forward_eviction_to_cpu0;
2750 forward_eviction_to_cpu1;
2751 pi_sendProbeResponseInv;
2752 // invalidate everything you've got
2756 // but make sure you have room for what you need from the fill
2764 transition(Si_F0, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S0) {} {
2765 forward_eviction_to_cpu0;
2766 forward_eviction_to_cpu1;
2767 pi_sendProbeResponseInv;
2777 transition(Si_F1, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S1) {} {
2778 forward_eviction_to_cpu0;
2779 forward_eviction_to_cpu1;
2780 pi_sendProbeResponseInv;
2790 transition({Es_F0, E0_F, E1_Es}, {PrbShrData, PrbShrDataDemand}, S_F0) {} {
2791 ph_sendProbeResponseHit;
2795 transition({Es_F1, E1_F, E0_Es}, {PrbShrData, PrbShrDataDemand}, S_F1) {} {
2796 ph_sendProbeResponseHit;
2800 transition(Es_F, {PrbShrData, PrbShrDataDemand}, S_F) {} {
2801 ph_sendProbeResponseHit;
2805 transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, {PrbShrData, PrbShrDataDemand}) {} {
2806 ph_sendProbeResponseHit;
2810 transition(S_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {} {
2811 forward_eviction_to_cpu0;
2812 forward_eviction_to_cpu1;
2813 pim_sendProbeResponseInvMs;
2822 transition(O_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {L2DataArrayRead} {
2823 forward_eviction_to_cpu0;
2824 forward_eviction_to_cpu1;
2825 pdm_sendProbeResponseDataMs;
2834 transition({S_M0, O_M0}, {PrbInv}, I_M0) {} {
2835 forward_eviction_to_cpu0;
2836 forward_eviction_to_cpu1;
2837 pim_sendProbeResponseInvMs;
2846 transition(S_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2847 forward_eviction_to_cpu0;
2848 forward_eviction_to_cpu1;
2849 pim_sendProbeResponseInvMs;
2858 transition(O_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2859 forward_eviction_to_cpu0;
2860 forward_eviction_to_cpu1;
2861 pdm_sendProbeResponseDataMs;
2870 transition({S_M1, O_M1}, {PrbInv}, I_M1) {} {
2871 forward_eviction_to_cpu0;
2872 forward_eviction_to_cpu1;
2873 pim_sendProbeResponseInvMs;
2882 transition({S0, S0_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2883 forward_eviction_to_cpu0;
2884 forward_eviction_to_cpu1;
2885 pi_sendProbeResponseInv;
2894 transition({S1, S1_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2895 forward_eviction_to_cpu0;
2896 forward_eviction_to_cpu1;
2897 pi_sendProbeResponseInv;
2906 transition({S_M0, S_M1}, {PrbShrData, PrbShrDataDemand}) {} {
2907 ph_sendProbeResponseHit;
2911 transition({O_M0, O_M1}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
2912 pd_sendProbeResponseData;
2916 transition({S0, S1, S0_C, S1_C}, {PrbShrData, PrbShrDataDemand}) {} {
2917 pb_sendProbeResponseBackprobe;
2921 transition({Ms_F0, M0_F, M1_Ms, O_F0}, {PrbInvData, PrbInvDataDemand}, IF_E0S) {L2DataArrayRead} {
2922 forward_eviction_to_cpu0;
2923 forward_eviction_to_cpu1;
2924 pd_sendProbeResponseData;
2933 transition({Ms_F1, M1_F, M0_Ms, O_F1}, {PrbInvData, PrbInvDataDemand}, IF_E1S) {L2DataArrayRead} {
2934 forward_eviction_to_cpu0;
2935 forward_eviction_to_cpu1;
2936 pd_sendProbeResponseData;
2945 transition({Ms_F, O_F}, {PrbInvData, PrbInvDataDemand}, IF_ES) {L2DataArrayRead} {
2946 forward_eviction_to_cpu0;
2947 forward_eviction_to_cpu1;
2948 pd_sendProbeResponseData;
2958 transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} {
2959 forward_eviction_to_cpu0;
2960 forward_eviction_to_cpu1;
2961 pi_sendProbeResponseInv;
2970 transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} {
2971 forward_eviction_to_cpu0;
2972 forward_eviction_to_cpu1;
2973 pi_sendProbeResponseInv;
2982 transition({Ms_F, O_F}, PrbInv, IF_ES) {} {
2983 forward_eviction_to_cpu0;
2984 forward_eviction_to_cpu1;
2985 pi_sendProbeResponseInv;
2995 transition({Ms_F0, M0_F, M1_Ms}, {PrbShrData, PrbShrDataDemand}, O_F0) {L2DataArrayRead} {
2996 pd_sendProbeResponseData;
3000 transition({Ms_F1, M1_F, M0_Ms}, {PrbShrData, PrbShrDataDemand}, O_F1) {} {
3003 transition({Ms_F}, {PrbShrData, PrbShrDataDemand}, O_F) {L2DataArrayRead} {
3004 pd_sendProbeResponseData;
3008 transition({O_F0, O_F1, O_F}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
3009 pd_sendProbeResponseData;