src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm

   1 /*
   2  * Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its contributors
  18  * may be used to endorse or promote products derived from this software
  19  * without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Author: Lisa Hsu
  34  */
  35
  36 machine(MachineType:CorePair, "CP-like Core Coherence")
  37  : Sequencer * sequencer;
  38    Sequencer * sequencer1;
  39    CacheMemory * L1Icache;
  40    CacheMemory * L1D0cache;
  41    CacheMemory * L1D1cache;
  42    CacheMemory * L2cache;
  43    int regionBufferNum;
  44    bool send_evictions := "False";
  45    Cycles issue_latency := 5;
  46    Cycles l2_hit_latency := 18;
  47
  48   // BEGIN Core Buffers
  49
  50   // To the Network
  51   MessageBuffer * requestFromCore, network="To", virtual_network="0", ordered="true", vnet_type="request";
  52   MessageBuffer * responseFromCore, network="To", virtual_network="2", ordered="false", vnet_type="response";
  53   MessageBuffer * unblockFromCore, network="To", virtual_network="4", ordered="false", vnet_type="unblock";
  54
  55   // From the Network
  56   MessageBuffer * probeToCore, network="From", virtual_network="0", ordered="false", vnet_type="request";
  57   MessageBuffer * responseToCore, network="From", virtual_network="2", ordered="false", vnet_type="response";
  58
  59   MessageBuffer * mandatoryQueue, ordered="false";
  60   MessageBuffer * triggerQueue, ordered="true";
  61
  62   // END Core Buffers
  63
  64 {
  65   // BEGIN STATES
  66   state_declaration(State, desc="Cache states", default="CorePair_State_I") {
  67
  68     I, AccessPermission:Invalid, desc="Invalid";
  69     S, AccessPermission:Read_Only, desc="Shared";
  70     E0, AccessPermission:Read_Write, desc="Exclusive with Cluster 0 ownership";
  71     E1, AccessPermission:Read_Write, desc="Exclusive with Cluster 1 ownership";
  72     Es, AccessPermission:Read_Write, desc="Exclusive in core";
  73     O, AccessPermission:Read_Only, desc="Owner state in core, both clusters and other cores may be sharing line";
  74     Ms, AccessPermission:Read_Write, desc="Modified in core, both clusters may be sharing line";
  75     M0, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  76     M1, AccessPermission:Read_Write, desc="Modified with cluster ownership";
  77
  78     // Transient States
  79     I_M0, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  80     I_M1, AccessPermission:Busy, desc="Invalid, issued RdBlkM, have not seen response yet";
  81     I_M0M1, AccessPermission:Busy, desc="Was in I_M0, got a store request from other cluster as well";
  82     I_M1M0, AccessPermission:Busy, desc="Was in I_M1, got a store request from other cluster as well";
  83     I_M0Ms, AccessPermission:Busy, desc="Was in I_M0, got a load request from other cluster as well";
  84     I_M1Ms, AccessPermission:Busy, desc="Was in I_M1, got a load request from other cluster as well";
  85     I_E0S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  86     I_E1S, AccessPermission:Busy, desc="Invalid, issued RdBlk, have not seen response yet";
  87     I_ES, AccessPermission:Busy, desc="S_F got hit by invalidating probe, RdBlk response needs to go to both clusters";
  88
  89     IF_E0S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E0S but expecting a L2_to_L1D0 trigger, just drop when receive";
  90     IF_E1S, AccessPermission:Busy, desc="something got hit with Probe Invalidate, now just I_E1S but expecting a L2_to_L1D1 trigger, just drop when receive";
  91     IF_ES, AccessPermission:Busy, desc="same, but waiting for two fills";
  92     IF0_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  93     IF1_ES, AccessPermission:Busy, desc="same, but waiting for two fills, got one";
  94     F_S0, AccessPermission:Busy, desc="same, but going to S0 when trigger received";
  95     F_S1, AccessPermission:Busy, desc="same, but going to S1 when trigger received";
  96
  97     ES_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for clean writeback ack";
  98     MO_I, AccessPermission:Read_Only, desc="L2 replacement, waiting for dirty writeback ack";
  99     MO_S0, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
 100     MO_S1, AccessPermission:Read_Only, desc="M/O got Ifetch Miss, must write back first, then send RdBlkS";
 101     S_F0, AccessPermission:Read_Only,  desc="Shared, filling L1";
 102     S_F1, AccessPermission:Read_Only,  desc="Shared, filling L1";
 103     S_F, AccessPermission:Read_Only,   desc="Shared, filling L1";
 104     O_F0, AccessPermission:Read_Only,  desc="Owned, filling L1";
 105     O_F1, AccessPermission:Read_Only,  desc="Owned, filling L1";
 106     O_F,  AccessPermission:Read_Only,  desc="Owned, filling L1";
 107     Si_F0, AccessPermission:Read_Only, desc="Shared, filling icache";
 108     Si_F1, AccessPermission:Read_Only, desc="Shared, filling icache";
 109     S_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 110     S_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 111     O_M0, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 112     O_M1, AccessPermission:Read_Only, desc="Shared, issued CtoD, have not seen response yet";
 113     S0, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 0, waiting for response";
 114     S1, AccessPermission:Busy, desc="RdBlkS on behalf of cluster 1, waiting for response";
 115
 116     Es_F0, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 117     Es_F1, AccessPermission:Read_Write, desc="Es, Cluster read, filling";
 118     Es_F, AccessPermission:Read_Write,  desc="Es, other cluster read, filling";
 119     E0_F, AccessPermission:Read_Write, desc="E0, cluster read, filling";
 120     E1_F, AccessPermission:Read_Write, desc="...";
 121     E0_Es, AccessPermission:Read_Write, desc="...";
 122     E1_Es, AccessPermission:Read_Write, desc="...";
 123     Ms_F0, AccessPermission:Read_Write, desc="...";
 124     Ms_F1, AccessPermission:Read_Write, desc="...";
 125     Ms_F, AccessPermission:Read_Write,  desc="...";
 126     M0_F, AccessPermission:Read_Write, desc="...";
 127     M0_Ms, AccessPermission:Read_Write, desc="...";
 128     M1_F, AccessPermission:Read_Write, desc="...";
 129     M1_Ms, AccessPermission:Read_Write, desc="...";
 130
 131     I_C, AccessPermission:Invalid, desc="Invalid, but waiting for WBAck from NB from canceled writeback";
 132     S0_C, AccessPermission:Busy, desc="MO_S0 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 133     S1_C, AccessPermission:Busy, desc="MO_S1 hit by invalidating probe, waiting for WBAck form NB for canceled WB";
 134     S_C, AccessPermission:Busy, desc="S*_C got NB_AckS, still waiting for WBAck";
 135
 136   } // END STATES
 137
 138   // BEGIN EVENTS
 139   enumeration(Event, desc="CP Events") {
 140     // CP Initiated events
 141     C0_Load_L1miss,            desc="Cluster 0 load, L1 missed";
 142     C0_Load_L1hit,             desc="Cluster 0 load, L1 hit";
 143     C1_Load_L1miss,            desc="Cluster 1 load L1 missed";
 144     C1_Load_L1hit,             desc="Cluster 1 load L1 hit";
 145     Ifetch0_L1hit,             desc="Instruction fetch, hit in the L1";
 146     Ifetch1_L1hit,             desc="Instruction fetch, hit in the L1";
 147     Ifetch0_L1miss,            desc="Instruction fetch, missed in the L1";
 148     Ifetch1_L1miss,            desc="Instruction fetch, missed in the L1";
 149     C0_Store_L1miss,           desc="Cluster 0 store missed in L1";
 150     C0_Store_L1hit,            desc="Cluster 0 store hit in L1";
 151     C1_Store_L1miss,           desc="Cluster 1 store missed in L1";
 152     C1_Store_L1hit,            desc="Cluster 1 store hit in L1";
 153     // NB Initiated events
 154     NB_AckS,             desc="NB Ack to Core Request";
 155     NB_AckM,             desc="NB Ack to Core Request";
 156     NB_AckE,             desc="NB Ack to Core Request";
 157
 158     NB_AckWB,            desc="NB Ack for writeback";
 159
 160     // Memory System initiatied events
 161     L1I_Repl,           desc="Replace address from L1I"; // Presumed clean
 162     L1D0_Repl,           desc="Replace address from L1D0"; // Presumed clean
 163     L1D1_Repl,           desc="Replace address from L1D1"; // Presumed clean
 164     L2_Repl,            desc="Replace address from L2";
 165
 166     L2_to_L1D0,           desc="L1 fill from L2";
 167     L2_to_L1D1,           desc="L1 fill from L2";
 168     L2_to_L1I,           desc="L1 fill from L2";
 169
 170     // Probe Events
 171     PrbInvData,         desc="probe, return O or M data";
 172     PrbInvDataDemand,     desc="probe, return O or M data. Demand request";
 173     PrbInv,             desc="probe, no need for data";
 174     PrbShrData,         desc="probe downgrade, return O or M data";
 175     PrbShrDataDemand,     desc="probe downgrade, return O or M data. Demand request";
 176     ForceRepl,          desc="probe from r-buf. Act as though a repl";
 177     ForceDowngrade,     desc="probe from r-buf. Act as though a repl";
 178
 179   }  // END EVENTS
 180
 181   enumeration(RequestType, desc="To communicate stats from transitions to recordStats") {
 182     L1D0DataArrayRead,    desc="Read the data array";
 183     L1D0DataArrayWrite,   desc="Write the data array";
 184     L1D0TagArrayRead,     desc="Read the data array";
 185     L1D0TagArrayWrite,    desc="Write the data array";
 186     L1D1DataArrayRead,    desc="Read the data array";
 187     L1D1DataArrayWrite,   desc="Write the data array";
 188     L1D1TagArrayRead,     desc="Read the data array";
 189     L1D1TagArrayWrite,    desc="Write the data array";
 190     L1IDataArrayRead,     desc="Read the data array";
 191     L1IDataArrayWrite,    desc="Write the data array";
 192     L1ITagArrayRead,      desc="Read the data array";
 193     L1ITagArrayWrite,     desc="Write the data array";
 194     L2DataArrayRead,      desc="Read the data array";
 195     L2DataArrayWrite,     desc="Write the data array";
 196     L2TagArrayRead,       desc="Read the data array";
 197     L2TagArrayWrite,      desc="Write the data array";
 198   }
 199
 200
 201   // BEGIN STRUCTURE DEFINITIONS
 202
 203
 204   // Cache Entry
 205   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 206     State CacheState,           desc="cache state";
 207     bool Dirty,                 desc="Is the data dirty (diff than memory)?";
 208     DataBlock DataBlk,          desc="data for the block";
 209     bool FromL2, default="false", desc="block just moved from L2";
 210   }
 211
 212   structure(TBE, desc="...") {
 213     State TBEState,             desc="Transient state";
 214     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 215     bool Dirty,              desc="Is the data dirty (different than memory)?";
 216     int NumPendingMsgs,      desc="Number of acks/data messages that this processor is waiting for";
 217     bool Shared,             desc="Victim hit by shared probe";
 218     bool AckNeeded,          desc="True if need to ack r-dir";
 219    }
 220
 221   structure(TBETable, external="yes") {
 222     TBE lookup(Addr);
 223     void allocate(Addr);
 224     void deallocate(Addr);
 225     bool isPresent(Addr);
 226   }
 227
 228   TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
 229
 230   Tick clockEdge();
 231   Tick cyclesToTicks(Cycles c);
 232
 233   void set_cache_entry(AbstractCacheEntry b);
 234   void unset_cache_entry();
 235   void set_tbe(TBE b);
 236   void unset_tbe();
 237   void wakeUpAllBuffers();
 238   void wakeUpBuffers(Addr a);
 239   Cycles curCycle();
 240
 241   // END STRUCTURE DEFINITIONS
 242
 243   // BEGIN INTERNAL FUNCTIONS
 244
 245   MachineID getPeer(MachineID mach) {
 246     return createMachineID(MachineType:RegionBuffer, intToID(regionBufferNum));
 247   }
 248
 249   bool addressInCore(Addr addr) {
 250     return (L2cache.isTagPresent(addr) || L1Icache.isTagPresent(addr) || L1D0cache.isTagPresent(addr) || L1D1cache.isTagPresent(addr));
 251   }
 252
 253   Entry getCacheEntry(Addr address), return_by_pointer="yes" {
 254     Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
 255     return L2cache_entry;
 256   }
 257
 258   DataBlock getDataBlock(Addr addr), return_by_ref="yes" {
 259     TBE tbe := TBEs.lookup(addr);
 260     if(is_valid(tbe)) {
 261       return tbe.DataBlk;
 262     } else {
 263       return getCacheEntry(addr).DataBlk;
 264     }
 265   }
 266
 267   Entry getL1CacheEntry(Addr addr, int cluster), return_by_pointer="yes" {
 268     if (cluster == 0) {
 269       Entry L1D0_entry := static_cast(Entry, "pointer", L1D0cache.lookup(addr));
 270       return L1D0_entry;
 271     } else {
 272       Entry L1D1_entry := static_cast(Entry, "pointer", L1D1cache.lookup(addr));
 273       return L1D1_entry;
 274     }
 275   }
 276
 277   Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
 278     Entry c_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
 279     return c_entry;
 280   }
 281
 282   bool presentOrAvail2(Addr addr) {
 283     return L2cache.isTagPresent(addr) || L2cache.cacheAvail(addr);
 284   }
 285
 286   bool presentOrAvailI(Addr addr) {
 287     return L1Icache.isTagPresent(addr) || L1Icache.cacheAvail(addr);
 288   }
 289
 290   bool presentOrAvailD0(Addr addr) {
 291     return L1D0cache.isTagPresent(addr) || L1D0cache.cacheAvail(addr);
 292   }
 293
 294   bool presentOrAvailD1(Addr addr) {
 295     return L1D1cache.isTagPresent(addr) || L1D1cache.cacheAvail(addr);
 296   }
 297
 298   State getState(TBE tbe, Entry cache_entry, Addr addr) {
 299     if(is_valid(tbe)) {
 300       return tbe.TBEState;
 301     } else if (is_valid(cache_entry)) {
 302       return cache_entry.CacheState;
 303     }
 304     return State:I;
 305   }
 306
 307   void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
 308     if (is_valid(tbe)) {
 309       tbe.TBEState := state;
 310     }
 311
 312     if (is_valid(cache_entry)) {
 313       cache_entry.CacheState := state;
 314     }
 315   }
 316
 317   AccessPermission getAccessPermission(Addr addr) {
 318     TBE tbe := TBEs.lookup(addr);
 319     if(is_valid(tbe)) {
 320       return CorePair_State_to_permission(tbe.TBEState);
 321     }
 322
 323     Entry cache_entry := getCacheEntry(addr);
 324     if(is_valid(cache_entry)) {
 325       return CorePair_State_to_permission(cache_entry.CacheState);
 326     }
 327
 328     return AccessPermission:NotPresent;
 329   }
 330
 331   void functionalRead(Addr addr, Packet *pkt) {
 332     TBE tbe := TBEs.lookup(addr);
 333     if(is_valid(tbe)) {
 334       testAndRead(addr, tbe.DataBlk, pkt);
 335     } else {
 336       functionalMemoryRead(pkt);
 337     }
 338   }
 339
 340   int functionalWrite(Addr addr, Packet *pkt) {
 341     int num_functional_writes := 0;
 342
 343     TBE tbe := TBEs.lookup(addr);
 344     if(is_valid(tbe)) {
 345       num_functional_writes := num_functional_writes +
 346             testAndWrite(addr, tbe.DataBlk, pkt);
 347     }
 348
 349     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
 350     return num_functional_writes;
 351   }
 352
 353   bool isValid(Addr addr) {
 354       AccessPermission perm := getAccessPermission(addr);
 355       if (perm == AccessPermission:NotPresent ||
 356           perm == AccessPermission:Invalid ||
 357           perm == AccessPermission:Busy) {
 358           return false;
 359       } else {
 360           return true;
 361       }
 362   }
 363
 364   void setAccessPermission(Entry cache_entry, Addr addr, State state) {
 365     if (is_valid(cache_entry)) {
 366       cache_entry.changePermission(CorePair_State_to_permission(state));
 367     }
 368   }
 369
 370   MachineType testAndClearLocalHit(Entry cache_entry) {
 371     assert(is_valid(cache_entry));
 372     if (cache_entry.FromL2) {
 373       cache_entry.FromL2 := false;
 374       return MachineType:L2Cache;
 375     } else {
 376       return MachineType:L1Cache;
 377     }
 378   }
 379
 380   void recordRequestType(RequestType request_type, Addr addr) {
 381     if (request_type == RequestType:L1D0DataArrayRead) {
 382       L1D0cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 383     } else if (request_type == RequestType:L1D0DataArrayWrite) {
 384       L1D0cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 385     } else if (request_type == RequestType:L1D0TagArrayRead) {
 386       L1D0cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 387     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 388       L1D0cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 389     } else if (request_type == RequestType:L1D1DataArrayRead) {
 390       L1D1cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 391     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 392       L1D1cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 393     } else if (request_type == RequestType:L1D1TagArrayRead) {
 394       L1D1cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 395     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 396       L1D1cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 397     } else if (request_type == RequestType:L1IDataArrayRead) {
 398       L1Icache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 399     } else if (request_type == RequestType:L1IDataArrayWrite) {
 400       L1Icache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 401     } else if (request_type == RequestType:L1ITagArrayRead) {
 402       L1Icache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 403     } else if (request_type == RequestType:L1ITagArrayWrite) {
 404       L1Icache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 405     } else if (request_type == RequestType:L2DataArrayRead) {
 406       L2cache.recordRequestType(CacheRequestType:DataArrayRead, addr);
 407     } else if (request_type == RequestType:L2DataArrayWrite) {
 408       L2cache.recordRequestType(CacheRequestType:DataArrayWrite, addr);
 409     } else if (request_type == RequestType:L2TagArrayRead) {
 410       L2cache.recordRequestType(CacheRequestType:TagArrayRead, addr);
 411     } else if (request_type == RequestType:L2TagArrayWrite) {
 412       L2cache.recordRequestType(CacheRequestType:TagArrayWrite, addr);
 413     }
 414   }
 415
 416   bool checkResourceAvailable(RequestType request_type, Addr addr) {
 417     if (request_type == RequestType:L2DataArrayRead) {
 418       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 419     } else if (request_type == RequestType:L2DataArrayWrite) {
 420       return L2cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 421     } else if (request_type == RequestType:L2TagArrayRead) {
 422       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 423     } else if (request_type == RequestType:L2TagArrayWrite) {
 424       return L2cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 425     } else if  (request_type == RequestType:L1D0DataArrayRead) {
 426       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 427     } else if  (request_type == RequestType:L1D0DataArrayWrite) {
 428       return L1D0cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 429     } else if (request_type == RequestType:L1D0TagArrayRead) {
 430       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 431     } else if (request_type == RequestType:L1D0TagArrayWrite) {
 432       return L1D0cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 433     } else if (request_type == RequestType:L1D1DataArrayRead) {
 434       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 435     } else if (request_type == RequestType:L1D1DataArrayWrite) {
 436       return L1D1cache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 437     } else if (request_type == RequestType:L1D1TagArrayRead) {
 438       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 439     } else if (request_type == RequestType:L1D1TagArrayWrite) {
 440       return L1D1cache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 441     } else if (request_type == RequestType:L1IDataArrayRead) {
 442       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 443     } else if (request_type == RequestType:L1IDataArrayWrite) {
 444       return L1Icache.checkResourceAvailable(CacheResourceType:DataArray, addr);
 445     } else if (request_type == RequestType:L1ITagArrayRead) {
 446       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 447     } else if (request_type == RequestType:L1ITagArrayWrite) {
 448       return L1Icache.checkResourceAvailable(CacheResourceType:TagArray, addr);
 449     } else {
 450       return true;
 451     }
 452   }
 453
 454   // END INTERNAL FUNCTIONS
 455
 456   // ** OUT_PORTS **
 457
 458   out_port(requestNetwork_out, CPURequestMsg, requestFromCore);
 459   out_port(responseNetwork_out, ResponseMsg, responseFromCore);
 460   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 461   out_port(unblockNetwork_out, UnblockMsg, unblockFromCore);
 462
 463   // ** IN_PORTS **
 464
 465   in_port(triggerQueue_in, TriggerMsg, triggerQueue, block_on="addr") {
 466     if (triggerQueue_in.isReady(clockEdge())) {
 467       peek(triggerQueue_in, TriggerMsg) {
 468         Entry cache_entry := getCacheEntry(in_msg.addr);
 469         TBE tbe := TBEs.lookup(in_msg.addr);
 470
 471         if (in_msg.Type == TriggerType:L2_to_L1) {
 472           if (in_msg.Dest == CacheId:L1I) {
 473             trigger(Event:L2_to_L1I, in_msg.addr, cache_entry, tbe);
 474           } else if (in_msg.Dest == CacheId:L1D0) {
 475             trigger(Event:L2_to_L1D0, in_msg.addr, cache_entry, tbe);
 476           } else if (in_msg.Dest == CacheId:L1D1) {
 477             trigger(Event:L2_to_L1D1, in_msg.addr, cache_entry, tbe);
 478           } else {
 479             error("unexpected trigger dest");
 480           }
 481         }
 482       }
 483     }
 484   }
 485
 486
 487   in_port(probeNetwork_in, NBProbeRequestMsg, probeToCore) {
 488     if (probeNetwork_in.isReady(clockEdge())) {
 489       peek(probeNetwork_in, NBProbeRequestMsg, block_on="addr") {
 490         Entry cache_entry := getCacheEntry(in_msg.addr);
 491         TBE tbe := TBEs.lookup(in_msg.addr);
 492
 493         if (in_msg.Type == ProbeRequestType:PrbInv) {
 494           if (in_msg.DemandRequest) {
 495             trigger(Event:PrbInvDataDemand, in_msg.addr, cache_entry, tbe);
 496           } else if (in_msg.ReturnData) {
 497             trigger(Event:PrbInvData, in_msg.addr, cache_entry, tbe);
 498           } else {
 499             trigger(Event:PrbInv, in_msg.addr, cache_entry, tbe);
 500           }
 501         } else if (in_msg.Type == ProbeRequestType:PrbDowngrade) {
 502           if (in_msg.DemandRequest) {
 503                trigger(Event:PrbShrDataDemand, in_msg.addr, cache_entry, tbe);
 504           } else {
 505                assert(in_msg.ReturnData);
 506                trigger(Event:PrbShrData, in_msg.addr, cache_entry, tbe);
 507           }
 508         } else if (in_msg.Type == ProbeRequestType:PrbRepl) {
 509           trigger(Event:ForceRepl, in_msg.addr, cache_entry, tbe);
 510         } else if (in_msg.Type == ProbeRequestType:PrbRegDowngrade) {
 511           trigger(Event:ForceDowngrade, in_msg.addr, cache_entry, tbe);
 512         } else {
 513           error("Unknown probe request");
 514         }
 515       }
 516     }
 517   }
 518
 519
 520   // ResponseNetwork
 521   in_port(responseToCore_in, ResponseMsg, responseToCore) {
 522     if (responseToCore_in.isReady(clockEdge())) {
 523       peek(responseToCore_in, ResponseMsg, block_on="addr") {
 524
 525         Entry cache_entry := getCacheEntry(in_msg.addr);
 526         TBE tbe := TBEs.lookup(in_msg.addr);
 527
 528         if (in_msg.Type == CoherenceResponseType:NBSysResp) {
 529           if (in_msg.State == CoherenceState:Modified) {
 530               trigger(Event:NB_AckM, in_msg.addr, cache_entry, tbe);
 531           } else if (in_msg.State == CoherenceState:Shared) {
 532             trigger(Event:NB_AckS, in_msg.addr, cache_entry, tbe);
 533           } else if (in_msg.State == CoherenceState:Exclusive) {
 534             trigger(Event:NB_AckE, in_msg.addr, cache_entry, tbe);
 535           }
 536         } else if (in_msg.Type == CoherenceResponseType:NBSysWBAck) {
 537           trigger(Event:NB_AckWB, in_msg.addr, cache_entry, tbe);
 538         } else {
 539           error("Unexpected Response Message to Core");
 540         }
 541       }
 542     }
 543   }
 544
 545   // Nothing from the Unblock Network
 546
 547   // Mandatory Queue
 548   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 549     if (mandatoryQueue_in.isReady(clockEdge())) {
 550       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 551
 552         Entry cache_entry := getCacheEntry(in_msg.LineAddress);
 553         TBE tbe := TBEs.lookup(in_msg.LineAddress);
 554
 555         if (in_msg.Type == RubyRequestType:IFETCH) {
 556           // FETCH ACCESS
 557
 558           if (L1Icache.isTagPresent(in_msg.LineAddress)) {
 559             if (mod(in_msg.contextId, 2) == 0) {
 560               trigger(Event:Ifetch0_L1hit, in_msg.LineAddress, cache_entry, tbe);
 561             } else {
 562               trigger(Event:Ifetch1_L1hit, in_msg.LineAddress, cache_entry, tbe);
 563             }
 564           } else {
 565             if (presentOrAvail2(in_msg.LineAddress)) {
 566               if (presentOrAvailI(in_msg.LineAddress)) {
 567                 if (mod(in_msg.contextId, 2) == 0) {
 568                   trigger(Event:Ifetch0_L1miss, in_msg.LineAddress, cache_entry,
 569                           tbe);
 570                 } else {
 571                   trigger(Event:Ifetch1_L1miss, in_msg.LineAddress, cache_entry,
 572                           tbe);
 573                 }
 574               } else {
 575                 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
 576                 trigger(Event:L1I_Repl, victim,
 577                         getCacheEntry(victim), TBEs.lookup(victim));
 578               }
 579             } else { // Not present or avail in L2
 580               Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 581               DPRINTF(RubySlicc, "Victim for %s L2_Repl(0) is %s\n", in_msg.LineAddress, victim);
 582               trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 583                       TBEs.lookup(victim));
 584             }
 585           }
 586         } else {
 587           // DATA ACCESS
 588           if (mod(in_msg.contextId, 2) == 1) {
 589             if (L1D1cache.isTagPresent(in_msg.LineAddress)) {
 590               if (in_msg.Type == RubyRequestType:LD) {
 591                 trigger(Event:C1_Load_L1hit, in_msg.LineAddress, cache_entry,
 592                         tbe);
 593               } else {
 594                 // Stores must write through, make sure L2 avail.
 595                 if (presentOrAvail2(in_msg.LineAddress)) {
 596                   trigger(Event:C1_Store_L1hit, in_msg.LineAddress, cache_entry,
 597                           tbe);
 598                 } else {
 599                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 600               DPRINTF(RubySlicc, "Victim for %s L2_Repl(1) is %s\n", in_msg.LineAddress, victim);
 601                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 602                           TBEs.lookup(victim));
 603                 }
 604               }
 605             } else {
 606               if (presentOrAvail2(in_msg.LineAddress)) {
 607                 if (presentOrAvailD1(in_msg.LineAddress)) {
 608                   if (in_msg.Type == RubyRequestType:LD) {
 609                     trigger(Event:C1_Load_L1miss, in_msg.LineAddress,
 610                             cache_entry, tbe);
 611                   } else {
 612                     trigger(Event:C1_Store_L1miss, in_msg.LineAddress,
 613                             cache_entry, tbe);
 614                   }
 615                 } else {
 616                   Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
 617               DPRINTF(RubySlicc, "Victim for %s L1D1_Repl is %s\n", in_msg.LineAddress, victim);
 618                   trigger(Event:L1D1_Repl, victim,
 619                           getCacheEntry(victim), TBEs.lookup(victim));
 620                 }
 621               } else { // not present or avail in L2
 622                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 623               DPRINTF(RubySlicc, "Victim for %s L2_Repl(2) is %s\n", in_msg.LineAddress, victim);
 624                 trigger(Event:L2_Repl, victim, getCacheEntry(victim), TBEs.lookup(victim));
 625               }
 626             }
 627           } else {
 628             Entry L1D0cache_entry := getL1CacheEntry(in_msg.LineAddress, 0);
 629             if (is_valid(L1D0cache_entry)) {
 630               if (in_msg.Type == RubyRequestType:LD) {
 631                 trigger(Event:C0_Load_L1hit, in_msg.LineAddress, cache_entry,
 632                     tbe);
 633               } else {
 634                 if (presentOrAvail2(in_msg.LineAddress)) {
 635                   trigger(Event:C0_Store_L1hit, in_msg.LineAddress, cache_entry,
 636                       tbe);
 637                 } else {
 638                   Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 639               DPRINTF(RubySlicc, "Victim for %s L2_Repl(3) is %s\n", in_msg.LineAddress, victim);
 640                   trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 641                       TBEs.lookup(victim));
 642                 }
 643               }
 644             } else {
 645               if (presentOrAvail2(in_msg.LineAddress)) {
 646                 if (presentOrAvailD0(in_msg.LineAddress)) {
 647                   if (in_msg.Type == RubyRequestType:LD) {
 648                     trigger(Event:C0_Load_L1miss, in_msg.LineAddress,
 649                         cache_entry, tbe);
 650                   } else {
 651                     trigger(Event:C0_Store_L1miss, in_msg.LineAddress,
 652                             cache_entry, tbe);
 653                   }
 654                 } else {
 655                   Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
 656               DPRINTF(RubySlicc, "Victim for %s L1D0_Repl is %s\n", in_msg.LineAddress, victim);
 657                   trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
 658                           TBEs.lookup(victim));
 659                 }
 660               } else {
 661                 Addr victim := L2cache.cacheProbe(in_msg.LineAddress);
 662               DPRINTF(RubySlicc, "Victim for %s L2_Repl(4) is %s\n", in_msg.LineAddress, victim);
 663                 trigger(Event:L2_Repl, victim, getCacheEntry(victim),
 664                         TBEs.lookup(victim));
 665               }
 666             }
 667           }
 668         }
 669       }
 670     }
 671   }
 672
 673
 674   // ACTIONS
 675   action(ii_invIcache, "ii", desc="invalidate iCache") {
 676     if (L1Icache.isTagPresent(address)) {
 677       L1Icache.deallocate(address);
 678     }
 679   }
 680
 681   action(i0_invCluster, "i0", desc="invalidate cluster 0") {
 682     if (L1D0cache.isTagPresent(address)) {
 683       L1D0cache.deallocate(address);
 684     }
 685   }
 686
 687   action(i1_invCluster, "i1", desc="invalidate cluster 1") {
 688     if (L1D1cache.isTagPresent(address)) {
 689       L1D1cache.deallocate(address);
 690     }
 691   }
 692
 693   action(ib_invBothClusters, "ib", desc="invalidate both clusters") {
 694     if (L1D0cache.isTagPresent(address)) {
 695       L1D0cache.deallocate(address);
 696     }
 697     if (L1D1cache.isTagPresent(address)) {
 698       L1D1cache.deallocate(address);
 699     }
 700   }
 701
 702   action(i2_invL2, "i2", desc="invalidate L2") {
 703     if(is_valid(cache_entry)) {
 704         L2cache.deallocate(address);
 705     }
 706     unset_cache_entry();
 707   }
 708
 709   action(n_issueRdBlk, "n", desc="Issue RdBlk") {
 710     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 711       out_msg.addr := address;
 712       out_msg.Type := CoherenceRequestType:RdBlk;
 713       out_msg.Requestor := machineID;
 714       out_msg.Destination.add(getPeer(machineID));
 715       out_msg.MessageSize := MessageSizeType:Request_Control;
 716       out_msg.InitialRequestTime := curCycle();
 717     }
 718   }
 719
 720   action(nM_issueRdBlkM, "nM", desc="Issue RdBlkM") {
 721     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 722       out_msg.addr := address;
 723       out_msg.Type := CoherenceRequestType:RdBlkM;
 724       out_msg.Requestor := machineID;
 725       out_msg.Destination.add(getPeer(machineID));
 726       out_msg.MessageSize := MessageSizeType:Request_Control;
 727       out_msg.InitialRequestTime := curCycle();
 728     }
 729   }
 730
 731   action(nMs_issueRdBlkMSinked, "nMs", desc="Issue RdBlkM with CtoDSinked") {
 732     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 733       out_msg.addr := address;
 734       out_msg.Type := CoherenceRequestType:RdBlkM;
 735       out_msg.Requestor := machineID;
 736       out_msg.Destination.add(getPeer(machineID));
 737       out_msg.MessageSize := MessageSizeType:Request_Control;
 738       out_msg.CtoDSinked := true;
 739     }
 740   }
 741
 742   action(nS_issueRdBlkS, "nS", desc="Issue RdBlkS") {
 743     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 744       out_msg.addr := address;
 745       out_msg.Type := CoherenceRequestType:RdBlkS;
 746       out_msg.Requestor := machineID;
 747       out_msg.Destination.add(getPeer(machineID));
 748       out_msg.MessageSize := MessageSizeType:Request_Control;
 749       out_msg.InitialRequestTime := curCycle();
 750     }
 751   }
 752
 753   action(nSs_issueRdBlkSSinked, "nSs", desc="Issue RdBlkS with CtoDSinked") {
 754     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 755       out_msg.addr := address;
 756       out_msg.Type := CoherenceRequestType:RdBlkS;
 757       out_msg.Requestor := machineID;
 758       out_msg.Destination.add(getPeer(machineID));
 759       out_msg.CtoDSinked := true;
 760       out_msg.MessageSize := MessageSizeType:Request_Control;
 761     }
 762   }
 763
 764   action(vd_victim, "vd", desc="Victimize M/O L2 Data") {
 765     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 766       out_msg.addr := address;
 767       out_msg.Requestor := machineID;
 768       assert(is_valid(cache_entry));
 769       out_msg.DataBlk := cache_entry.DataBlk;
 770       assert(cache_entry.Dirty);
 771       out_msg.Destination.add(getPeer(machineID));
 772       out_msg.MessageSize := MessageSizeType:Request_Control;
 773       out_msg.Type := CoherenceRequestType:VicDirty;
 774       out_msg.InitialRequestTime := curCycle();
 775       if (cache_entry.CacheState == State:O) {
 776         out_msg.Shared := true;
 777       } else {
 778         out_msg.Shared := false;
 779       }
 780     }
 781   }
 782
 783   action(vc_victim, "vc", desc="Victimize E/S L2 Data") {
 784     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 785       out_msg.addr := address;
 786       out_msg.Requestor := machineID;
 787       out_msg.Destination.add(getPeer(machineID));
 788       out_msg.MessageSize := MessageSizeType:Request_Control;
 789       out_msg.Type := CoherenceRequestType:VicClean;
 790       out_msg.InitialRequestTime := curCycle();
 791       if (cache_entry.CacheState == State:S) {
 792         out_msg.Shared := true;
 793       } else {
 794         out_msg.Shared := false;
 795       }
 796     }
 797   }
 798
 799   // Could send these two directly to dir if we made a new out network on channel 0
 800   action(vdf_victimForce, "vdf", desc="Victimize M/O L2 Data") {
 801     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 802       out_msg.addr := address;
 803       out_msg.Requestor := machineID;
 804       assert(is_valid(cache_entry));
 805       out_msg.DataBlk := cache_entry.DataBlk;
 806       assert(cache_entry.Dirty);
 807       out_msg.Destination.add(getPeer(machineID));
 808       out_msg.MessageSize := MessageSizeType:Request_Control;
 809       out_msg.Type := CoherenceRequestType:VicDirty;
 810       out_msg.InitialRequestTime := curCycle();
 811       if (cache_entry.CacheState == State:O) {
 812         out_msg.Shared := true;
 813       } else {
 814         out_msg.Shared := false;
 815       }
 816       out_msg.Private := true;
 817     }
 818   }
 819
 820   action(vcf_victimForce, "vcf", desc="Victimize E/S L2 Data") {
 821     enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
 822       out_msg.addr := address;
 823       out_msg.Requestor := machineID;
 824       out_msg.Destination.add(getPeer(machineID));
 825       out_msg.MessageSize := MessageSizeType:Request_Control;
 826       out_msg.Type := CoherenceRequestType:VicClean;
 827       out_msg.InitialRequestTime := curCycle();
 828       if (cache_entry.CacheState == State:S) {
 829         out_msg.Shared := true;
 830       } else {
 831         out_msg.Shared := false;
 832       }
 833       out_msg.Private := true;
 834     }
 835   }
 836
 837   action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
 838     if (L1D0cache.isTagPresent(address) == false) {
 839       L1D0cache.allocateVoid(address, new Entry);
 840     }
 841   }
 842
 843   action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
 844     if (L1D1cache.isTagPresent(address) == false) {
 845       L1D1cache.allocateVoid(address, new Entry);
 846     }
 847   }
 848
 849   action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
 850     if (L1Icache.isTagPresent(address) == false) {
 851       L1Icache.allocateVoid(address, new Entry);
 852     }
 853   }
 854
 855   action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
 856     if (is_invalid(cache_entry)) {
 857       set_cache_entry(L2cache.allocate(address, new Entry));
 858     }
 859   }
 860
 861   action(t_allocateTBE, "t", desc="allocate TBE Entry") {
 862     check_allocate(TBEs);
 863     assert(is_valid(cache_entry));
 864     TBEs.allocate(address);
 865     set_tbe(TBEs.lookup(address));
 866     tbe.DataBlk := cache_entry.DataBlk;  // Data only used for WBs
 867     tbe.Dirty := cache_entry.Dirty;
 868     tbe.Shared := false;
 869   }
 870
 871   action(d_deallocateTBE, "d", desc="Deallocate TBE") {
 872     TBEs.deallocate(address);
 873     unset_tbe();
 874   }
 875
 876   action(p_popMandatoryQueue, "pm", desc="Pop Mandatory Queue") {
 877     mandatoryQueue_in.dequeue(clockEdge());
 878   }
 879
 880   action(pr_popResponseQueue, "pr", desc="Pop Response Queue") {
 881     responseToCore_in.dequeue(clockEdge());
 882   }
 883
 884   action(pt_popTriggerQueue, "pt", desc="Pop Trigger Queue") {
 885     triggerQueue_in.dequeue(clockEdge());
 886   }
 887
 888   action(pp_popProbeQueue, "pp", desc="pop probe queue") {
 889     probeNetwork_in.dequeue(clockEdge());
 890   }
 891
 892   action(il0_loadDone, "il0", desc="Cluster 0 i load done") {
 893     Entry entry := getICacheEntry(address);
 894     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 895     assert(is_valid(entry));
 896     // L2 supplies data (functional accesses only look in L2, ok because L1
 897     //                   writes through to L2)
 898     sequencer.readCallback(address,
 899                            l2entry.DataBlk,
 900                            true,
 901                            testAndClearLocalHit(entry));
 902   }
 903
 904   action(il1_loadDone, "il1", desc="Cluster 1 i load done") {
 905     Entry entry := getICacheEntry(address);
 906     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 907     assert(is_valid(entry));
 908     // L2 supplies data (functional accesses only look in L2, ok because L1
 909     //                   writes through to L2)
 910     sequencer1.readCallback(address,
 911                             l2entry.DataBlk,
 912                             true,
 913                             testAndClearLocalHit(entry));
 914   }
 915
 916   action(l0_loadDone, "l0", desc="Cluster 0 load done") {
 917     Entry entry := getL1CacheEntry(address, 0);
 918     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 919     assert(is_valid(entry));
 920     // L2 supplies data (functional accesses only look in L2, ok because L1
 921     //                   writes through to L2)
 922     sequencer.readCallback(address,
 923                            l2entry.DataBlk,
 924                            true,
 925                            testAndClearLocalHit(entry));
 926   }
 927
 928   action(l1_loadDone, "l1", desc="Cluster 1 load done") {
 929     Entry entry := getL1CacheEntry(address, 1);
 930     Entry l2entry := getCacheEntry(address); // Used for functional accesses
 931     assert(is_valid(entry));
 932     // L2 supplies data (functional accesses only look in L2, ok because L1
 933     //                   writes through to L2)
 934     sequencer1.readCallback(address,
 935                             l2entry.DataBlk,
 936                             true,
 937                             testAndClearLocalHit(entry));
 938   }
 939
 940   action(xl0_loadDone, "xl0", desc="Cluster 0 load done") {
 941     peek(responseToCore_in, ResponseMsg) {
 942       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 943               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 944       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 945       DPRINTF(ProtocolTrace, "CP Load Done 0 -- address %s, data: %s\n",
 946               address, l2entry.DataBlk);
 947       // L2 supplies data (functional accesses only look in L2, ok because L1
 948       //                   writes through to L2)
 949       assert(is_valid(l2entry));
 950       sequencer.readCallback(address,
 951                              l2entry.DataBlk,
 952                              false,
 953                              machineIDToMachineType(in_msg.Sender),
 954                              in_msg.InitialRequestTime,
 955                              in_msg.ForwardRequestTime,
 956                              in_msg.ProbeRequestStartTime);
 957     }
 958   }
 959
 960   action(xl1_loadDone, "xl1", desc="Cluster 1 load done") {
 961    peek(responseToCore_in, ResponseMsg) {
 962       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 963               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 964       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 965       // L2 supplies data (functional accesses only look in L2, ok because L1
 966       //                   writes through to L2)
 967       assert(is_valid(l2entry));
 968       sequencer1.readCallback(address,
 969                               l2entry.DataBlk,
 970                               false,
 971                               machineIDToMachineType(in_msg.Sender),
 972                               in_msg.InitialRequestTime,
 973                               in_msg.ForwardRequestTime,
 974                               in_msg.ProbeRequestStartTime);
 975    }
 976   }
 977
 978   action(xi0_loadDone, "xi0", desc="Cluster 0 i-load done") {
 979     peek(responseToCore_in, ResponseMsg) {
 980       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 981               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
 982       Entry l2entry := getCacheEntry(address); // Used for functional accesses
 983       // L2 supplies data (functional accesses only look in L2, ok because L1
 984       //                   writes through to L2)
 985       assert(is_valid(l2entry));
 986       sequencer.readCallback(address,
 987                              l2entry.DataBlk,
 988                              false,
 989                              machineIDToMachineType(in_msg.Sender),
 990                              in_msg.InitialRequestTime,
 991                              in_msg.ForwardRequestTime,
 992                              in_msg.ProbeRequestStartTime);
 993     }
 994   }
 995
 996   action(xi1_loadDone, "xi1", desc="Cluster 1 i-load done") {
 997     peek(responseToCore_in, ResponseMsg) {
 998       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
 999               (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1000       Entry l2entry := getCacheEntry(address); // Used for functional accesses
1001       // L2 supplies data (functional accesses only look in L2, ok because L1
1002       //                   writes through to L2)
1003       assert(is_valid(l2entry));
1004       sequencer1.readCallback(address,
1005                               l2entry.DataBlk,
1006                               false,
1007                               machineIDToMachineType(in_msg.Sender),
1008                               in_msg.InitialRequestTime,
1009                               in_msg.ForwardRequestTime,
1010                               in_msg.ProbeRequestStartTime);
1011     }
1012   }
1013
1014   action(s0_storeDone, "s0", desc="Cluster 0 store done") {
1015     Entry entry := getL1CacheEntry(address, 0);
1016     assert(is_valid(entry));
1017     assert(is_valid(cache_entry));
1018     sequencer.writeCallback(address,
1019                             cache_entry.DataBlk,
1020                             true,
1021                             testAndClearLocalHit(entry));
1022     cache_entry.Dirty := true;
1023     entry.DataBlk := cache_entry.DataBlk;
1024     entry.Dirty := true;
1025     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1026   }
1027
1028   action(s1_storeDone, "s1", desc="Cluster 1 store done") {
1029     Entry entry := getL1CacheEntry(address, 1);
1030     assert(is_valid(entry));
1031     assert(is_valid(cache_entry));
1032     sequencer1.writeCallback(address,
1033                              cache_entry.DataBlk,
1034                              true,
1035                              testAndClearLocalHit(entry));
1036     cache_entry.Dirty := true;
1037     entry.Dirty := true;
1038     entry.DataBlk := cache_entry.DataBlk;
1039     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1040   }
1041
1042   action(xs0_storeDone, "xs0", desc="Cluster 0 store done") {
1043     peek(responseToCore_in, ResponseMsg) {
1044       Entry entry := getL1CacheEntry(address, 0);
1045       assert(is_valid(entry));
1046       assert(is_valid(cache_entry));
1047       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1048              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1049       sequencer.writeCallback(address,
1050                               cache_entry.DataBlk,
1051                               false,
1052                               machineIDToMachineType(in_msg.Sender),
1053                               in_msg.InitialRequestTime,
1054                               in_msg.ForwardRequestTime,
1055                               in_msg.ProbeRequestStartTime);
1056       cache_entry.Dirty := true;
1057       entry.Dirty := true;
1058       entry.DataBlk := cache_entry.DataBlk;
1059       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1060     }
1061   }
1062
1063   action(xs1_storeDone, "xs1", desc="Cluster 1 store done") {
1064     peek(responseToCore_in, ResponseMsg) {
1065       Entry entry := getL1CacheEntry(address, 1);
1066       assert(is_valid(entry));
1067       assert(is_valid(cache_entry));
1068       assert((machineIDToMachineType(in_msg.Sender) == MachineType:Directory) ||
1069              (machineIDToMachineType(in_msg.Sender) == MachineType:L3Cache));
1070       sequencer1.writeCallback(address,
1071                                cache_entry.DataBlk,
1072                                false,
1073                                machineIDToMachineType(in_msg.Sender),
1074                                in_msg.InitialRequestTime,
1075                                in_msg.ForwardRequestTime,
1076                                in_msg.ProbeRequestStartTime);
1077       cache_entry.Dirty := true;
1078       entry.Dirty := true;
1079       entry.DataBlk := cache_entry.DataBlk;
1080       DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
1081     }
1082   }
1083
1084   action(forward_eviction_to_cpu0, "fec0", desc="sends eviction information to processor0") {
1085     if (send_evictions) {
1086       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1087       sequencer.evictionCallback(address);
1088     }
1089   }
1090
1091   action(forward_eviction_to_cpu1, "fec1", desc="sends eviction information to processor1") {
1092     if (send_evictions) {
1093       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
1094       sequencer1.evictionCallback(address);
1095     }
1096   }
1097
1098   action(ci_copyL2ToL1, "ci", desc="copy L2 data to L1") {
1099     Entry entry := getICacheEntry(address);
1100     assert(is_valid(entry));
1101     assert(is_valid(cache_entry));
1102     entry.Dirty := cache_entry.Dirty;
1103     entry.DataBlk := cache_entry.DataBlk;
1104     entry.FromL2 := true;
1105   }
1106
1107   action(c0_copyL2ToL1, "c0", desc="copy L2 data to L1") {
1108     Entry entry := getL1CacheEntry(address, 0);
1109     assert(is_valid(entry));
1110     assert(is_valid(cache_entry));
1111     entry.Dirty := cache_entry.Dirty;
1112     entry.DataBlk := cache_entry.DataBlk;
1113     entry.FromL2 := true;
1114   }
1115
1116   action(ss_sendStaleNotification, "ss", desc="stale data; nothing to writeback") {
1117     peek(responseToCore_in, ResponseMsg) {
1118       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1119         out_msg.addr := address;
1120         out_msg.Type := CoherenceResponseType:StaleNotif;
1121         out_msg.Sender := machineID;
1122         out_msg.Destination.add(map_Address_to_Directory(address));
1123         out_msg.MessageSize := MessageSizeType:Response_Control;
1124         DPRINTF(RubySlicc, "%s\n", out_msg);
1125       }
1126     }
1127   }
1128
1129   action(c1_copyL2ToL1, "c1", desc="copy L2 data to L1") {
1130     Entry entry := getL1CacheEntry(address, 1);
1131     assert(is_valid(entry));
1132     assert(is_valid(cache_entry));
1133     entry.Dirty := cache_entry.Dirty;
1134     entry.DataBlk := cache_entry.DataBlk;
1135     entry.FromL2 := true;
1136   }
1137
1138   action(fi_L2ToL1, "fi", desc="L2 to L1 inst fill") {
1139     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1140       out_msg.addr := address;
1141       out_msg.Type := TriggerType:L2_to_L1;
1142       out_msg.Dest := CacheId:L1I;
1143     }
1144   }
1145
1146   action(f0_L2ToL1, "f0", desc="L2 to L1 data fill") {
1147     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1148       out_msg.addr := address;
1149       out_msg.Type := TriggerType:L2_to_L1;
1150       out_msg.Dest := CacheId:L1D0;
1151     }
1152   }
1153
1154   action(f1_L2ToL1, "f1", desc="L2 to L1 data fill") {
1155     enqueue(triggerQueue_out, TriggerMsg, l2_hit_latency) {
1156       out_msg.addr := address;
1157       out_msg.Type := TriggerType:L2_to_L1;
1158       out_msg.Dest := CacheId:L1D1;
1159     }
1160   }
1161
1162   action(wi_writeIcache, "wi", desc="write data to icache (and l2)") {
1163     peek(responseToCore_in, ResponseMsg) {
1164       Entry entry := getICacheEntry(address);
1165       assert(is_valid(entry));
1166       assert(is_valid(cache_entry));
1167       entry.DataBlk := in_msg.DataBlk;
1168       entry.Dirty := in_msg.Dirty;
1169       cache_entry.DataBlk := in_msg.DataBlk;
1170       cache_entry.Dirty := in_msg.Dirty;
1171     }
1172   }
1173
1174   action(w0_writeDcache, "w0", desc="write data to dcache 0 (and l2)") {
1175     peek(responseToCore_in, ResponseMsg) {
1176       Entry entry := getL1CacheEntry(address, 0);
1177       assert(is_valid(entry));
1178       assert(is_valid(cache_entry));
1179       entry.DataBlk := in_msg.DataBlk;
1180       entry.Dirty := in_msg.Dirty;
1181       cache_entry.DataBlk := in_msg.DataBlk;
1182       cache_entry.Dirty := in_msg.Dirty;
1183     }
1184   }
1185
1186   action(w1_writeDcache, "w1", desc="write data to dcache 1 (and l2)") {
1187     peek(responseToCore_in, ResponseMsg) {
1188       Entry entry := getL1CacheEntry(address, 1);
1189       assert(is_valid(entry));
1190       assert(is_valid(cache_entry));
1191       entry.DataBlk := in_msg.DataBlk;
1192       entry.Dirty := in_msg.Dirty;
1193       cache_entry.DataBlk := in_msg.DataBlk;
1194       cache_entry.Dirty := in_msg.Dirty;
1195     }
1196   }
1197
1198   action(wb_data, "wb", desc="write back data") {
1199     peek(responseToCore_in, ResponseMsg) {
1200       enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1201         out_msg.addr := address;
1202         out_msg.Type := CoherenceResponseType:CPUData;
1203         out_msg.Sender := machineID;
1204         out_msg.Destination.add(map_Address_to_Directory(address));
1205         out_msg.DataBlk := tbe.DataBlk;
1206         out_msg.Dirty := tbe.Dirty;
1207         if (tbe.Shared) {
1208           out_msg.NbReqShared := true;
1209         } else {
1210           out_msg.NbReqShared := false;
1211         }
1212         out_msg.State := CoherenceState:Shared; // faux info
1213         out_msg.MessageSize := MessageSizeType:Writeback_Data;
1214         DPRINTF(RubySlicc, "%s\n", out_msg);
1215       }
1216     }
1217   }
1218
1219   action(pi_sendProbeResponseInv, "pi", desc="send probe ack inv, no data") {
1220     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1221       out_msg.addr := address;
1222       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1223       out_msg.Sender := machineID;
1224       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1225       out_msg.Dirty := false;
1226       out_msg.Hit := false;
1227       out_msg.Ntsl := true;
1228       out_msg.State := CoherenceState:NA;
1229       out_msg.MessageSize := MessageSizeType:Response_Control;
1230       out_msg.isValid := isValid(address);
1231     }
1232   }
1233
1234   action(pim_sendProbeResponseInvMs, "pim", desc="send probe ack inv, no data") {
1235     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1236       out_msg.addr := address;
1237       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1238       out_msg.Sender := machineID;
1239       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1240       out_msg.Dirty := false;
1241       out_msg.Ntsl := true;
1242       out_msg.Hit := false;
1243       APPEND_TRANSITION_COMMENT("Setting Ms");
1244       out_msg.State := CoherenceState:NA;
1245       out_msg.MessageSize := MessageSizeType:Response_Control;
1246       out_msg.isValid := isValid(address);
1247     }
1248   }
1249
1250   action(ph_sendProbeResponseHit, "ph", desc="send probe ack PrbShrData, no data") {
1251     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1252       out_msg.addr := address;
1253       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1254       out_msg.Sender := machineID;
1255       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1256       assert(addressInCore(address) || is_valid(tbe));
1257       out_msg.Dirty := false;  // only true if sending back data i think
1258       out_msg.Hit := true;
1259       out_msg.Ntsl := false;
1260       out_msg.State := CoherenceState:NA;
1261       out_msg.MessageSize := MessageSizeType:Response_Control;
1262       out_msg.isValid := isValid(address);
1263     }
1264   }
1265
1266   action(pb_sendProbeResponseBackprobe, "pb", desc="send probe ack PrbShrData, no data, check for L1 residence") {
1267     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1268       out_msg.addr := address;
1269       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
1270       out_msg.Sender := machineID;
1271       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1272       if (addressInCore(address)) {
1273         out_msg.Hit := true;
1274       } else {
1275         out_msg.Hit := false;
1276       }
1277       out_msg.Dirty := false;  // not sending back data, so def. not dirty
1278       out_msg.Ntsl := false;
1279       out_msg.State := CoherenceState:NA;
1280       out_msg.MessageSize := MessageSizeType:Response_Control;
1281       out_msg.isValid := isValid(address);
1282     }
1283   }
1284
1285   action(pd_sendProbeResponseData, "pd", desc="send probe ack, with data") {
1286     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1287       assert(is_valid(cache_entry));
1288       out_msg.addr := address;
1289       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1290       out_msg.Sender := machineID;
1291       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1292       out_msg.DataBlk := cache_entry.DataBlk;
1293       assert(cache_entry.Dirty);
1294       out_msg.Dirty := true;
1295       out_msg.Hit := true;
1296       out_msg.State := CoherenceState:NA;
1297       out_msg.MessageSize := MessageSizeType:Response_Data;
1298       out_msg.isValid := isValid(address);
1299     }
1300   }
1301
1302   action(pdm_sendProbeResponseDataMs, "pdm", desc="send probe ack, with data") {
1303     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1304       assert(is_valid(cache_entry));
1305       out_msg.addr := address;
1306       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1307       out_msg.Sender := machineID;
1308       out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
1309       out_msg.DataBlk := cache_entry.DataBlk;
1310       assert(cache_entry.Dirty);
1311       out_msg.Dirty := true;
1312       out_msg.Hit := true;
1313       APPEND_TRANSITION_COMMENT("Setting Ms");
1314       out_msg.State := CoherenceState:NA;
1315       out_msg.MessageSize := MessageSizeType:Response_Data;
1316       out_msg.isValid := isValid(address);
1317     }
1318   }
1319
1320   action(pdt_sendProbeResponseDataFromTBE, "pdt", desc="send probe ack with data") {
1321     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1322       assert(is_valid(tbe));
1323       out_msg.addr := address;
1324       out_msg.Type := CoherenceResponseType:CPUPrbResp;
1325       out_msg.Sender := machineID;
1326       out_msg.Destination.add(map_Address_to_Directory(address));
1327       out_msg.DataBlk := tbe.DataBlk;
1328       assert(tbe.Dirty);
1329       out_msg.Dirty := true;
1330       out_msg.Hit := true;
1331       out_msg.State := CoherenceState:NA;
1332       out_msg.MessageSize := MessageSizeType:Response_Data;
1333       out_msg.isValid := isValid(address);
1334     }
1335   }
1336
1337   action(ra_sendReplAck, "ra", desc="Send ack to r-buf that line is replaced if needed") {
1338     if (is_invalid(tbe) || tbe.AckNeeded) {
1339       enqueue(requestNetwork_out, CPURequestMsg, issue_latency) {
1340         out_msg.addr := address;
1341         out_msg.Type := CoherenceRequestType:InvAck;
1342         out_msg.Requestor := machineID;
1343         out_msg.Destination.add(getPeer(machineID));
1344         out_msg.MessageSize := MessageSizeType:Request_Control;
1345       }
1346       APPEND_TRANSITION_COMMENT(" Sending ack to r-buf ");
1347     } else {
1348       APPEND_TRANSITION_COMMENT(" NOT Sending ack to r-buf ");
1349     }
1350   }
1351
1352   action(m_markAckNeeded, "m", desc="Mark TBE to send ack when deallocated") {
1353     assert(is_valid(tbe));
1354     tbe.AckNeeded := true;
1355   }
1356
1357   action(mc_cancelWB, "mc", desc="send writeback cancel to L3") {
1358     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
1359       out_msg.addr := address;
1360       out_msg.Type := CoherenceResponseType:CPUCancelWB;
1361       out_msg.Destination.add(map_Address_to_Directory(address));
1362       out_msg.Sender := machineID;
1363       out_msg.MessageSize := MessageSizeType:Response_Control;
1364     }
1365   }
1366
1367   action(s_setSharedFlip, "s", desc="hit by shared probe, status may be different") {
1368     assert(is_valid(tbe));
1369     tbe.Shared := true;
1370   }
1371
1372   action(uu_sendUnblock, "uu", desc="state changed, unblock") {
1373     enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
1374       out_msg.addr := address;
1375       out_msg.Destination.add(map_Address_to_Directory(address));
1376       out_msg.MessageSize := MessageSizeType:Unblock_Control;
1377       out_msg.wasValid := isValid(address);
1378       DPRINTF(RubySlicc, "%s\n", out_msg);
1379     }
1380   }
1381
1382   action(sdv_sendDoneValid, "sdv", desc="Request finished, send done ack") {
1383     enqueue(unblockNetwork_out, UnblockMsg, 1) {
1384       out_msg.addr := address;
1385       out_msg.Destination.add(getPeer(machineID));
1386       out_msg.DoneAck := true;
1387       out_msg.MessageSize := MessageSizeType:Unblock_Control;
1388       if (is_valid(tbe)) {
1389           out_msg.Dirty := tbe.Dirty;
1390       } else if (is_valid(cache_entry)) {
1391           out_msg.Dirty := cache_entry.Dirty;
1392       } else {
1393           out_msg.Dirty := false;
1394       }
1395       out_msg.validToInvalid := false;
1396       DPRINTF(RubySlicc, "%s\n", out_msg);
1397     }
1398   }
1399
1400   action(sdi_sendDoneInvalid, "sdi", desc="Request finished, send done ack") {
1401     enqueue(unblockNetwork_out, UnblockMsg, 1) {
1402       out_msg.addr := address;
1403       out_msg.Destination.add(getPeer(machineID));
1404       out_msg.DoneAck := true;
1405       out_msg.MessageSize := MessageSizeType:Unblock_Control;
1406       if (is_valid(tbe)) {
1407           out_msg.Dirty := tbe.Dirty;
1408       } else if (is_valid(cache_entry)) {
1409           out_msg.Dirty := cache_entry.Dirty;
1410       } else {
1411           out_msg.Dirty := false;
1412       }
1413       out_msg.validToInvalid := true;
1414       DPRINTF(RubySlicc, "%s\n", out_msg);
1415     }
1416   }
1417
1418   action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
1419     ++L1D0cache.demand_misses;
1420   }
1421
1422   action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
1423     ++L1D1cache.demand_misses;
1424   }
1425
1426   action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
1427     ++L1Icache.demand_misses;
1428   }
1429
1430   action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
1431     ++L2cache.demand_misses;
1432   }
1433
1434   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
1435     probeNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1436   }
1437
1438   action(zz_recycleMandatoryQueue, "\z", desc="recycle mandatory queue") {
1439     mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
1440   }
1441   // END ACTIONS
1442
1443   // BEGIN TRANSITIONS
1444
1445   // transitions from base
1446   transition(I, C0_Load_L1miss, I_E0S) {L1D0TagArrayRead, L2TagArrayRead} {
1447     // track misses, if implemented
1448     // since in I state, L2 miss as well
1449     l2m_profileMiss;
1450     l10m_profileMiss;
1451     a0_allocateL1D;
1452     l1im_profileMiss;
1453     a2_allocateL2;
1454     i1_invCluster;
1455     ii_invIcache;
1456     n_issueRdBlk;
1457     p_popMandatoryQueue;
1458   }
1459
1460   transition(I, C1_Load_L1miss, I_E1S) {L1D1TagArrayRead, L2TagArrayRead} {
1461     // track misses, if implemented
1462     // since in I state, L2 miss as well
1463     l2m_profileMiss;
1464     l11m_profileMiss;
1465     a1_allocateL1D;
1466     a2_allocateL2;
1467     i0_invCluster;
1468     ii_invIcache;
1469     n_issueRdBlk;
1470     p_popMandatoryQueue;
1471   }
1472
1473   transition(I, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1474     // track misses, if implemented
1475     // L2 miss as well
1476     l10m_profileMiss;
1477     l2m_profileMiss;
1478     l1im_profileMiss;
1479     ai_allocateL1I;
1480     a2_allocateL2;
1481     ib_invBothClusters;
1482     nS_issueRdBlkS;
1483     p_popMandatoryQueue;
1484   }
1485
1486   transition(I, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1487      l11m_profileMiss;
1488     // track misses, if implemented
1489     // L2 miss as well
1490     l2m_profileMiss;
1491     l1im_profileMiss;
1492     ai_allocateL1I;
1493     a2_allocateL2;
1494     ib_invBothClusters;
1495     nS_issueRdBlkS;
1496     p_popMandatoryQueue;
1497   }
1498
1499   transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead,L2TagArrayRead} {
1500     l2m_profileMiss;
1501     l10m_profileMiss;
1502     a0_allocateL1D;
1503     a2_allocateL2;
1504     i1_invCluster;
1505     ii_invIcache;
1506     nM_issueRdBlkM;
1507     p_popMandatoryQueue;
1508   }
1509
1510   transition(I, C1_Store_L1miss, I_M1) {L1D0TagArrayRead, L2TagArrayRead} {
1511     l2m_profileMiss;
1512     l11m_profileMiss;
1513     a1_allocateL1D;
1514     a2_allocateL2;
1515     i0_invCluster;
1516     ii_invIcache;
1517     nM_issueRdBlkM;
1518     p_popMandatoryQueue;
1519   }
1520
1521   transition(S, C0_Load_L1miss, S_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1522     l10m_profileMiss;
1523     a0_allocateL1D;
1524     f0_L2ToL1;
1525     p_popMandatoryQueue;
1526   }
1527
1528   transition(S, C1_Load_L1miss, S_F1) {L1D1TagArrayRead,  L2TagArrayRead, L2DataArrayRead} {
1529     l11m_profileMiss;
1530     a1_allocateL1D;
1531     f1_L2ToL1;
1532     p_popMandatoryQueue;
1533   }
1534
1535   transition(S, Ifetch0_L1miss, Si_F0) {L1ITagArrayRead,L2TagArrayRead, L2DataArrayRead} {
1536     l1im_profileMiss;
1537     ai_allocateL1I;
1538     fi_L2ToL1;
1539     p_popMandatoryQueue;
1540   }
1541
1542   transition(S, Ifetch1_L1miss, Si_F1) {L1ITagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1543     l1im_profileMiss;
1544     ai_allocateL1I;
1545     fi_L2ToL1;
1546     p_popMandatoryQueue;
1547   }
1548
1549   transition({S}, {C0_Store_L1hit, C0_Store_L1miss}, S_M0) {L1D0TagArrayRead, L2TagArrayRead}{
1550     l2m_profileMiss;
1551     l10m_profileMiss;
1552     a0_allocateL1D;
1553     i1_invCluster;
1554     ii_invIcache;
1555     nM_issueRdBlkM;
1556     p_popMandatoryQueue;
1557   }
1558
1559   transition({S}, {C1_Store_L1hit, C1_Store_L1miss}, S_M1) {L1D1TagArrayRead,L2TagArrayRead} {
1560     l2m_profileMiss;
1561     l11m_profileMiss;
1562     a1_allocateL1D;
1563     i0_invCluster;
1564     ii_invIcache;
1565     nM_issueRdBlkM;
1566     p_popMandatoryQueue;
1567   }
1568   transition(Es, C0_Load_L1miss, Es_F0) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1569      l10m_profileMiss;
1570     a0_allocateL1D;
1571     f0_L2ToL1;
1572     p_popMandatoryQueue;
1573   }
1574
1575   transition(Es, C1_Load_L1miss, Es_F1) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {  // can this be folded with S_F?
1576      l11m_profileMiss;
1577     a1_allocateL1D;
1578     f1_L2ToL1;
1579     p_popMandatoryQueue;
1580   }
1581
1582   transition(Es, Ifetch0_L1miss, S0) {L1ITagArrayRead, L2TagArrayRead} {
1583       l1im_profileMiss;
1584      i2_invL2;
1585     ai_allocateL1I;
1586     a2_allocateL2;
1587     ib_invBothClusters;
1588     nS_issueRdBlkS;
1589     p_popMandatoryQueue;
1590   }
1591
1592   transition(Es, Ifetch1_L1miss, S1) {L1ITagArrayRead, L2TagArrayRead} {
1593      l1im_profileMiss;
1594     i2_invL2;
1595     ai_allocateL1I;
1596     a2_allocateL2;
1597     ib_invBothClusters;
1598     nS_issueRdBlkS;
1599     p_popMandatoryQueue;
1600   }
1601
1602   // THES SHOULD NOT BE INSTANTANEOUS BUT OH WELL FOR NOW
1603   transition(Es, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayWrite,L1D0TagArrayRead, L2TagArrayRead, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1604     a0_allocateL1D;
1605     i1_invCluster;
1606     s0_storeDone;   // instantaneous L1/L2 dirty - no writethrough delay
1607     p_popMandatoryQueue;
1608   }
1609
1610   transition(Es, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
1611     a1_allocateL1D;
1612     i0_invCluster;
1613     s1_storeDone;
1614     p_popMandatoryQueue;
1615   }
1616
1617   transition(E0, C0_Load_L1miss, E0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1618      l10m_profileMiss;
1619     a0_allocateL1D;
1620     f0_L2ToL1;
1621     p_popMandatoryQueue;
1622   }
1623
1624   transition(E0, C1_Load_L1miss, E0_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1625      l11m_profileMiss;
1626     a1_allocateL1D;
1627     f1_L2ToL1;
1628     p_popMandatoryQueue;
1629   }
1630
1631   transition(E0, Ifetch0_L1miss, S0) {L2TagArrayRead, L1ITagArrayRead} {
1632     l2m_profileMiss; // permissions miss, still issue RdBlkS
1633     l1im_profileMiss;
1634     i2_invL2;
1635     ai_allocateL1I;
1636     a2_allocateL2;
1637     i0_invCluster;
1638     nS_issueRdBlkS;
1639     p_popMandatoryQueue;
1640   }
1641
1642   transition(E0, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead } {
1643     l2m_profileMiss; // permissions miss, still issue RdBlkS
1644     l1im_profileMiss;
1645     i2_invL2;
1646     ai_allocateL1I;
1647     a2_allocateL2;
1648     i0_invCluster;
1649     nS_issueRdBlkS;
1650     p_popMandatoryQueue;
1651   }
1652
1653   transition(E0, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1654     a0_allocateL1D;
1655     s0_storeDone;
1656     p_popMandatoryQueue;
1657   }
1658
1659   transition(E0, C1_Store_L1miss, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1660     a1_allocateL1D;
1661     l11m_profileMiss;
1662     i0_invCluster;
1663     s1_storeDone;
1664     p_popMandatoryQueue;
1665   }
1666
1667   transition(E1, C1_Load_L1miss, E1_F) {L1D1TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1668     a1_allocateL1D;
1669     l11m_profileMiss;
1670     f1_L2ToL1;
1671     p_popMandatoryQueue;
1672   }
1673
1674   transition(E1, C0_Load_L1miss, E1_Es) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1675     a0_allocateL1D;
1676     l10m_profileMiss;
1677     f0_L2ToL1;
1678     p_popMandatoryQueue;
1679   }
1680
1681   transition(E1, Ifetch1_L1miss, S1) {L2TagArrayRead, L1ITagArrayRead} {
1682     l2m_profileMiss; // permissions miss, still issue RdBlkS
1683     l1im_profileMiss;
1684     i2_invL2;
1685     ai_allocateL1I;
1686     a2_allocateL2;
1687     i1_invCluster;
1688     nS_issueRdBlkS;
1689     p_popMandatoryQueue;
1690   }
1691
1692   transition(E1, Ifetch0_L1miss, S0) {L2TagArrayRead,L1ITagArrayRead} {
1693     l2m_profileMiss; // permissions miss, still issue RdBlkS
1694     l1im_profileMiss;
1695     i2_invL2;
1696     ai_allocateL1I;
1697     a2_allocateL2;
1698     i1_invCluster;
1699     nS_issueRdBlkS;
1700     p_popMandatoryQueue;
1701   }
1702
1703   transition(E1, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1704     a1_allocateL1D;
1705     s1_storeDone;
1706     p_popMandatoryQueue;
1707   }
1708
1709   transition(E1, C0_Store_L1miss, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite, L2DataArrayWrite} {
1710      l10m_profileMiss;
1711     a0_allocateL1D;
1712     i1_invCluster;
1713     s0_storeDone;
1714     p_popMandatoryQueue;
1715   }
1716
1717   transition({O}, {C0_Store_L1hit, C0_Store_L1miss}, O_M0) {L1D0TagArrayRead, L2TagArrayRead} {
1718     l2m_profileMiss; // permissions miss, still issue CtoD
1719      l10m_profileMiss;
1720     a0_allocateL1D;
1721     i1_invCluster;
1722     ii_invIcache;
1723     nM_issueRdBlkM;
1724     p_popMandatoryQueue;
1725   }
1726
1727   transition({O}, {C1_Store_L1hit, C1_Store_L1miss}, O_M1) {L1D1TagArrayRead, L2TagArrayRead} {
1728     l2m_profileMiss; // permissions miss, still issue RdBlkS
1729     l11m_profileMiss;
1730     a1_allocateL1D;
1731     i0_invCluster;
1732     ii_invIcache;
1733     nM_issueRdBlkM;
1734     p_popMandatoryQueue;
1735   }
1736
1737   transition(O, C0_Load_L1miss, O_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1738     l10m_profileMiss;
1739     a0_allocateL1D;
1740     f0_L2ToL1;
1741     p_popMandatoryQueue;
1742   }
1743
1744   transition(O, C1_Load_L1miss, O_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1745     l11m_profileMiss;
1746     a1_allocateL1D;
1747     f1_L2ToL1;
1748     p_popMandatoryQueue;
1749   }
1750
1751   transition(Ms, C0_Load_L1miss, Ms_F0) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1752     l10m_profileMiss;
1753     a0_allocateL1D;
1754     f0_L2ToL1;
1755     p_popMandatoryQueue;
1756   }
1757
1758   transition(Ms, C1_Load_L1miss, Ms_F1) {L2TagArrayRead, L2DataArrayRead, L1D1TagArrayRead} {
1759     l11m_profileMiss;
1760     a1_allocateL1D;
1761     f1_L2ToL1;
1762     p_popMandatoryQueue;
1763   }
1764
1765   transition({Ms, M0, M1, O}, Ifetch0_L1miss, MO_S0) {L1ITagArrayRead,  L2TagArrayRead} {
1766     l2m_profileMiss;  // permissions miss
1767     l1im_profileMiss;
1768     ai_allocateL1I;
1769     t_allocateTBE;
1770     ib_invBothClusters;
1771     vd_victim;
1772 //    i2_invL2;
1773     p_popMandatoryQueue;
1774   }
1775
1776   transition({Ms, M0, M1, O}, Ifetch1_L1miss, MO_S1) {L1ITagArrayRead L2TagArrayRead } {
1777     l2m_profileMiss;  // permissions miss
1778     l10m_profileMiss;
1779     ai_allocateL1I;
1780     t_allocateTBE;
1781     ib_invBothClusters;
1782     vd_victim;
1783 //    i2_invL2;
1784     p_popMandatoryQueue;
1785   }
1786
1787   transition(Ms, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1788     a0_allocateL1D;
1789     i1_invCluster;
1790     s0_storeDone;
1791     p_popMandatoryQueue;
1792   }
1793
1794   transition(Ms, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D1TagArrayRead, L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1795     a1_allocateL1D;
1796     i0_invCluster;
1797     s1_storeDone;
1798     p_popMandatoryQueue;
1799   }
1800
1801   transition(M0, C0_Load_L1miss, M0_F) {L1D0TagArrayRead, L2TagArrayRead, L2DataArrayRead} {
1802    l10m_profileMiss;
1803     a0_allocateL1D;
1804     f0_L2ToL1;
1805     p_popMandatoryQueue;
1806   }
1807
1808   transition(M0, C1_Load_L1miss, M0_Ms) {L2TagArrayRead, L2DataArrayRead,L1D1TagArrayRead} {
1809    l11m_profileMiss;
1810     a1_allocateL1D;
1811     f1_L2ToL1;
1812     p_popMandatoryQueue;
1813   }
1814
1815   transition(M0, {C0_Store_L1hit, C0_Store_L1miss}) {L1D0TagArrayRead, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead} {
1816     a0_allocateL1D;
1817     s0_storeDone;
1818     p_popMandatoryQueue;
1819   }
1820
1821   transition(M0, {C1_Store_L1hit, C1_Store_L1miss}, M1) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
1822     a1_allocateL1D;
1823     i0_invCluster;
1824     s1_storeDone;
1825     p_popMandatoryQueue;
1826   }
1827
1828   transition(M1, C0_Load_L1miss, M1_Ms) {L2TagArrayRead, L2DataArrayRead, L1D0TagArrayRead} {
1829     l10m_profileMiss;
1830     a0_allocateL1D;
1831     f0_L2ToL1;
1832     p_popMandatoryQueue;
1833   }
1834
1835   transition(M1, C1_Load_L1miss, M1_F) {L1D1TagArrayRead L2TagArrayRead, L2DataArrayRead} {
1836    l11m_profileMiss;
1837     a1_allocateL1D;
1838     f1_L2ToL1;
1839     p_popMandatoryQueue;
1840   }
1841
1842   transition(M1, {C0_Store_L1hit, C0_Store_L1miss}, M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayRead, L2DataArrayWrite, L2TagArrayWrite} {
1843     a0_allocateL1D;
1844     i1_invCluster;
1845     s0_storeDone;
1846     p_popMandatoryQueue;
1847   }
1848
1849   transition(M1, {C1_Store_L1hit, C1_Store_L1miss}) {L1D1TagArrayRead, L1D1DataArrayWrite, L2TagArrayRead, L2DataArrayWrite} {
1850     a1_allocateL1D;
1851     s1_storeDone;
1852     p_popMandatoryQueue;
1853   }
1854
1855   // end transitions from base
1856
1857   // Begin simple hit transitions
1858   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es,
1859           Ms_F1, M0_Ms}, C0_Load_L1hit) {L1D0TagArrayRead, L1D0DataArrayRead} {
1860     // track hits, if implemented
1861     l0_loadDone;
1862     p_popMandatoryQueue;
1863   }
1864
1865   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es,
1866           Ms_F0, M1_Ms}, C1_Load_L1hit) {L1D1TagArrayRead, L1D1DataArrayRead} {
1867     // track hits, if implemented
1868     l1_loadDone;
1869     p_popMandatoryQueue;
1870   }
1871
1872   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch0_L1hit) {L1ITagArrayRead, L1IDataArrayRead} {
1873     // track hits, if implemented
1874     il0_loadDone;
1875     p_popMandatoryQueue;
1876   }
1877
1878   transition({S, S_C, S_F0, S_F1, S_F}, Ifetch1_L1hit) {L1ITagArrayRead, L1IDataArrayWrite} {
1879     // track hits, if implemented
1880     il1_loadDone;
1881     p_popMandatoryQueue;
1882   }
1883
1884   // end simple hit transitions
1885
1886   // Transitions from transient states
1887
1888   // recycles
1889   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1890           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1891           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, C0_Load_L1hit) {} {
1892     zz_recycleMandatoryQueue;
1893   }
1894
1895   transition({IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M1,
1896           O_M1, S0, S1, I_C, S0_C, S1_C, S_C}, C0_Load_L1miss) {} {
1897     zz_recycleMandatoryQueue;
1898   }
1899
1900   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1901           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1902           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, C1_Load_L1hit) {} {
1903     zz_recycleMandatoryQueue;
1904   }
1905
1906   transition({IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, Si_F0, Si_F1, S_M0,
1907           O_M0, S0, S1, I_C, S0_C, S1_C, S_C},  C1_Load_L1miss) {} {
1908     zz_recycleMandatoryQueue;
1909   }
1910
1911   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, {Ifetch0_L1hit, Ifetch1_L1hit}) {} {
1912     zz_recycleMandatoryQueue;
1913   }
1914
1915   transition({I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES,
1916           IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, ES_I, MO_I, S_F0, S_F1, S_F,
1917           O_F0, O_F1, O_F, S_M0, S_M1, O_M0, O_M1, Es_F0, Es_F1, Es_F, E0_F,
1918           E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, I_C,
1919           S_C}, {Ifetch0_L1miss, Ifetch1_L1miss}) {} {
1920     zz_recycleMandatoryQueue;
1921   }
1922
1923   transition({I_E1S, IF_E1S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1, S_F1, O_F1,
1924           Si_F0, Si_F1, S_M1, O_M1, S0, S1, Es_F1, E1_F, E0_Es, Ms_F1, M0_Ms,
1925           M1_F, I_C, S0_C, S1_C, S_C}, {C0_Store_L1miss}) {} {
1926     zz_recycleMandatoryQueue;
1927   }
1928
1929   transition({I_E0S, IF_E0S, F_S0, F_S1, ES_I, MO_I, MO_S0, MO_S1 S_F0, O_F0,
1930           Si_F0, Si_F1, S_M0, O_M0, S0, S1, Es_F0, E0_F, E1_Es, Ms_F0, M0_F,
1931           M1_Ms, I_C, S0_C, S1_C, S_C}, {C1_Store_L1miss}) {} {
1932     zz_recycleMandatoryQueue;
1933   }
1934
1935   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1936           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M0, O_M0, Es_F0, Es_F1, Es_F, E0_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_Ms}, {C0_Store_L1hit}) {} {
1937     zz_recycleMandatoryQueue;
1938   }
1939
1940   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1941           IF0_ES, IF1_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, Si_F0, Si_F1, S_M1,
1942           O_M1, Es_F0, Es_F1, Es_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F,
1943           M0_Ms, M1_F, M1_Ms}, {C1_Store_L1hit}) {} {
1944     zz_recycleMandatoryQueue;
1945   }
1946
1947   transition({I_M0, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_ES, IF_E0S, IF_ES,
1948           IF0_ES, IF1_ES, S_F0, S_F, O_F0, O_F, S_M0, O_M0, Es_F0, Es_F, E0_F,
1949           E1_Es, Ms_F0, Ms_F, M0_F, M1_Ms}, L1D0_Repl) {} {
1950     zz_recycleMandatoryQueue;
1951   }
1952
1953   transition({I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E1S, I_ES, IF_E1S, IF_ES,
1954           IF0_ES, IF1_ES, S_F1, S_F, O_F1, O_F, S_M1, O_M1, Es_F1, Es_F, E1_F,
1955           E0_Es, Ms_F1, Ms_F, M0_Ms, M1_F}, L1D1_Repl) {} {
1956     zz_recycleMandatoryQueue;
1957   }
1958
1959   transition({F_S0, F_S1, MO_S0, MO_S1, Si_F0, Si_F1, S0, S1, S0_C, S1_C}, L1I_Repl) {} {
1960     zz_recycleMandatoryQueue;
1961   }
1962
1963   transition({S_C, S0_C, S1_C, S0, S1, Si_F0, Si_F1, I_M0, I_M1, I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_E0S, I_E1S, I_ES, S_F0, S_F1, S_F, O_F0, O_F1, O_F, S_M0, O_M0, S_M1, O_M1, Es_F0, Es_F1, Es_F, E0_F, E1_F, E0_Es, E1_Es, Ms_F0, Ms_F1, Ms_F, M0_F, M0_Ms, M1_F, M1_Ms, MO_S0, MO_S1, IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, L2_Repl) {} {
1964     zz_recycleMandatoryQueue;
1965   }
1966
1967   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES, F_S0, F_S1}, {NB_AckS,
1968           PrbInvData, PrbInvDataDemand, PrbInv, PrbShrData, PrbShrDataDemand}) {} {
1969     zz_recycleMandatoryQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1970   }
1971
1972   transition({IF_E0S, IF_E1S, IF_ES, IF0_ES, IF1_ES}, NB_AckE) {} {
1973     zz_recycleMandatoryQueue;  // these should be resolved soon, but I didn't want to add more states, though technically they could be solved now, and probes really could be solved but i don't think it's really necessary.
1974   }
1975
1976   transition({E0_Es, E1_F, Es_F1}, C0_Load_L1miss, Es_F) {L2DataArrayRead} {
1977     l10m_profileMiss;
1978     a0_allocateL1D;
1979     f0_L2ToL1;
1980     p_popMandatoryQueue;
1981   }
1982
1983   transition(S_F1, C0_Load_L1miss, S_F) {L2DataArrayRead} {
1984     l10m_profileMiss;
1985     a0_allocateL1D;
1986     f0_L2ToL1;
1987     p_popMandatoryQueue;
1988   }
1989
1990   transition(O_F1, C0_Load_L1miss, O_F) {L2DataArrayRead} {
1991     l10m_profileMiss;
1992     a0_allocateL1D;
1993     f0_L2ToL1;
1994     p_popMandatoryQueue;
1995   }
1996
1997   transition({Ms_F1, M0_Ms, M1_F}, C0_Load_L1miss, Ms_F) {L2DataArrayRead} {
1998     l10m_profileMiss;
1999     a0_allocateL1D;
2000     f0_L2ToL1;
2001     p_popMandatoryQueue;
2002   }
2003
2004   transition(I_M0, C1_Load_L1miss, I_M0Ms){
2005     l11m_profileMiss;
2006     l2m_profileMiss;
2007     a1_allocateL1D;
2008     p_popMandatoryQueue;
2009   }
2010
2011   transition(I_M1, C0_Load_L1miss, I_M1Ms){
2012     l10m_profileMiss;
2013     l2m_profileMiss;
2014     a0_allocateL1D;
2015     p_popMandatoryQueue;
2016   }
2017
2018   transition(I_M0, C1_Store_L1miss, I_M0M1) {
2019     l11m_profileMiss;
2020     l2m_profileMiss;
2021     a1_allocateL1D;
2022     p_popMandatoryQueue;
2023   }
2024
2025   transition(I_M1, C0_Store_L1miss, I_M1M0) {L1D0TagArrayRead, L1D0TagArrayWrite, L2TagArrayRead, L2TagArrayWrite} {
2026     l2m_profileMiss;
2027     a0_allocateL1D;
2028     p_popMandatoryQueue;
2029   }
2030
2031   transition(I_E0S, C1_Load_L1miss, I_ES) {} {
2032     l2m_profileMiss;
2033     l11m_profileMiss;
2034     a1_allocateL1D;
2035     p_popMandatoryQueue;
2036   }
2037
2038   transition(I_E1S, C0_Load_L1miss, I_ES) {} {
2039     l2m_profileMiss;
2040     l10m_profileMiss;
2041     l2m_profileMiss;
2042     a0_allocateL1D;
2043     p_popMandatoryQueue;
2044   }
2045
2046   transition({E1_Es, E0_F, Es_F0}, C1_Load_L1miss, Es_F) {L2DataArrayRead} {
2047     l11m_profileMiss;
2048     a1_allocateL1D;
2049     f1_L2ToL1;
2050     p_popMandatoryQueue;
2051   }
2052
2053   transition(S_F0, C1_Load_L1miss, S_F) { L2DataArrayRead} {
2054     l11m_profileMiss;
2055     a1_allocateL1D;
2056     f1_L2ToL1;
2057     p_popMandatoryQueue;
2058   }
2059
2060   transition(O_F0, C1_Load_L1miss, O_F) {L2DataArrayRead} {
2061     l11m_profileMiss;
2062     a1_allocateL1D;
2063     f1_L2ToL1;
2064     p_popMandatoryQueue;
2065   }
2066
2067   transition({Ms_F0, M1_Ms, M0_F}, C1_Load_L1miss, Ms_F) {L2DataArrayRead} {
2068     l11m_profileMiss;
2069     a1_allocateL1D;
2070     f1_L2ToL1;
2071     p_popMandatoryQueue;
2072   }
2073
2074   transition({S, Es, E0, O, Ms, M0, O_F1, S_F1, Si_F0, Si_F1, Es_F1, E0_Es, Ms_F1, M0_Ms}, L1D0_Repl) {L1D0TagArrayRead} {
2075     i0_invCluster;
2076   }
2077
2078   transition({S, Es, E1, O, Ms, M1, O_F0, S_F0, Si_F0, Si_F1, Es_F0, E1_Es, Ms_F0, M1_Ms}, L1D1_Repl) {L1D1TagArrayRead} {
2079     i1_invCluster;
2080   }
2081
2082   transition({S, S_C, S_F0, S_F1}, L1I_Repl) {L1ITagArrayRead} {
2083     ii_invIcache;
2084   }
2085
2086   transition({S, E0, E1, Es}, L2_Repl, ES_I) {L2TagArrayRead,L1D0TagArrayRead, L1D1TagArrayRead, L1ITagArrayRead} {
2087     forward_eviction_to_cpu0;
2088     forward_eviction_to_cpu1;
2089     t_allocateTBE;
2090     vc_victim;
2091     ib_invBothClusters;
2092     i2_invL2;
2093     ii_invIcache;
2094   }
2095
2096   transition({Ms, M0, M1, O}, L2_Repl, MO_I) {L2TagArrayRead, L2TagArrayWrite, L1D0TagArrayRead, L1D1TagArrayRead} {
2097     forward_eviction_to_cpu0;
2098     forward_eviction_to_cpu1;
2099     t_allocateTBE;
2100     vd_victim;
2101     i2_invL2;
2102     ib_invBothClusters;  // nothing will happen for D0 on M1, vice versa
2103   }
2104
2105   transition(S0, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2106     wi_writeIcache;
2107     xi0_loadDone;
2108     uu_sendUnblock;
2109     sdv_sendDoneValid;
2110     pr_popResponseQueue;
2111   }
2112
2113   transition(S1, NB_AckS, S) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2114     wi_writeIcache;
2115     xi1_loadDone;
2116     sdv_sendDoneValid;
2117     uu_sendUnblock;
2118     pr_popResponseQueue;
2119   }
2120
2121   transition(S0_C, NB_AckS, S_C) { L1IDataArrayWrite,L2DataArrayWrite} {
2122     // does not need send done since the rdblks was "sinked"
2123     wi_writeIcache;
2124     xi0_loadDone;
2125     uu_sendUnblock;
2126     pr_popResponseQueue;
2127   }
2128
2129   transition(S1_C, NB_AckS, S_C) { L1D1DataArrayWrite,L2DataArrayWrite} {
2130     wi_writeIcache;
2131     xi1_loadDone;
2132     uu_sendUnblock;
2133     pr_popResponseQueue;
2134   }
2135
2136   transition(I_M0, NB_AckM, M0) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2137     w0_writeDcache;
2138     xs0_storeDone;
2139     sdv_sendDoneValid;
2140     uu_sendUnblock;
2141     pr_popResponseQueue;
2142   }
2143
2144   transition(I_M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2145     w1_writeDcache;
2146     xs1_storeDone;
2147     sdv_sendDoneValid;
2148     uu_sendUnblock;
2149     pr_popResponseQueue;
2150   }
2151
2152   // THESE MO->M1 should not be instantaneous but oh well for now.
2153   transition(I_M0M1, NB_AckM, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2154     w0_writeDcache;
2155     xs0_storeDone;
2156     sdv_sendDoneValid;
2157     uu_sendUnblock;
2158     i0_invCluster;
2159     s1_storeDone;
2160     pr_popResponseQueue;
2161   }
2162
2163   transition(I_M1M0, NB_AckM, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite,L2DataArrayWrite, L2TagArrayWrite} {
2164     w1_writeDcache;
2165     xs1_storeDone;
2166     sdv_sendDoneValid;
2167     uu_sendUnblock;
2168     i1_invCluster;
2169     s0_storeDone;
2170     pr_popResponseQueue;
2171   }
2172
2173   // Above shoudl be more like this, which has some latency to xfer to L1
2174   transition(I_M0Ms, NB_AckM, M0_Ms) {L1D0DataArrayWrite,L2DataArrayWrite} {
2175     w0_writeDcache;
2176     xs0_storeDone;
2177     sdv_sendDoneValid;
2178     uu_sendUnblock;
2179     f1_L2ToL1;
2180     pr_popResponseQueue;
2181   }
2182
2183   transition(I_M1Ms, NB_AckM, M1_Ms) {L1D1DataArrayWrite,L2DataArrayWrite} {
2184     w1_writeDcache;
2185     xs1_storeDone;
2186     sdv_sendDoneValid;
2187     uu_sendUnblock;
2188     f0_L2ToL1;
2189     pr_popResponseQueue;
2190   }
2191
2192   transition(I_E0S, NB_AckE, E0) {L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2193     w0_writeDcache;
2194     xl0_loadDone;
2195     sdv_sendDoneValid;
2196     uu_sendUnblock;
2197     pr_popResponseQueue;
2198   }
2199
2200   transition(I_E1S, NB_AckE, E1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2201     w1_writeDcache;
2202     xl1_loadDone;
2203     sdv_sendDoneValid;
2204     uu_sendUnblock;
2205     pr_popResponseQueue;
2206   }
2207
2208   transition(I_ES, NB_AckE, Es) {L1D1DataArrayWrite, L1D1TagArrayWrite, L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite } {
2209     w0_writeDcache;
2210     xl0_loadDone;
2211     w1_writeDcache;
2212     xl1_loadDone;
2213     sdv_sendDoneValid;
2214     uu_sendUnblock;
2215     pr_popResponseQueue;
2216   }
2217
2218   transition(I_E0S, NB_AckS, S) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2219     w0_writeDcache;
2220     xl0_loadDone;
2221     sdv_sendDoneValid;
2222     uu_sendUnblock;
2223     pr_popResponseQueue;
2224   }
2225
2226   transition(I_E1S, NB_AckS, S) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayWrite} {
2227     w1_writeDcache;
2228     xl1_loadDone;
2229     sdv_sendDoneValid;
2230     uu_sendUnblock;
2231     pr_popResponseQueue;
2232   }
2233
2234   transition(I_ES, NB_AckS, S) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite,  L2DataArrayWrite} {
2235     w0_writeDcache;
2236     xl0_loadDone;
2237     w1_writeDcache;
2238     xl1_loadDone;
2239     sdv_sendDoneValid;
2240     uu_sendUnblock;
2241     pr_popResponseQueue;
2242   }
2243
2244   transition(S_F0, L2_to_L1D0, S) {L1D0TagArrayWrite, L1D0DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2245     c0_copyL2ToL1;
2246     l0_loadDone;
2247     pt_popTriggerQueue;
2248   }
2249
2250   transition(S_F1, L2_to_L1D1, S) {L1D1TagArrayWrite, L1D1DataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2251     c1_copyL2ToL1;
2252     l1_loadDone;
2253     pt_popTriggerQueue;
2254   }
2255
2256   transition(Si_F0, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2257     ci_copyL2ToL1;
2258     il0_loadDone;
2259     pt_popTriggerQueue;
2260   }
2261
2262   transition(Si_F1, L2_to_L1I, S) {L1ITagArrayWrite, L1IDataArrayWrite,  L2TagArrayWrite, L2DataArrayRead} {
2263     ci_copyL2ToL1;
2264     il1_loadDone;
2265     pt_popTriggerQueue;
2266   }
2267
2268   transition(S_F, L2_to_L1D0, S_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2269     c0_copyL2ToL1;
2270     l0_loadDone;
2271     pt_popTriggerQueue;
2272   }
2273
2274   transition(S_F, L2_to_L1D1, S_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2275     c1_copyL2ToL1;
2276     l1_loadDone;
2277     pt_popTriggerQueue;
2278   }
2279
2280   transition(O_F0, L2_to_L1D0, O) { L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2281     c0_copyL2ToL1;
2282     l0_loadDone;
2283     pt_popTriggerQueue;
2284   }
2285
2286   transition(O_F1, L2_to_L1D1, O) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2287     c1_copyL2ToL1;
2288     l1_loadDone;
2289     pt_popTriggerQueue;
2290   }
2291
2292   transition(O_F, L2_to_L1D0, O_F1) { L1D0DataArrayWrite, L2DataArrayRead} {
2293     c0_copyL2ToL1;
2294     l0_loadDone;
2295     pt_popTriggerQueue;
2296   }
2297
2298   transition(O_F, L2_to_L1D1, O_F0) { L1D1DataArrayWrite, L2DataArrayRead} {
2299     c1_copyL2ToL1;
2300     l1_loadDone;
2301     pt_popTriggerQueue;
2302   }
2303
2304   transition(M1_F, L2_to_L1D1, M1) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2305     c1_copyL2ToL1;
2306     l1_loadDone;
2307     pt_popTriggerQueue;
2308   }
2309
2310   transition(M0_F, L2_to_L1D0, M0) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2311     c0_copyL2ToL1;
2312     l0_loadDone;
2313     pt_popTriggerQueue;
2314   }
2315
2316   transition(Ms_F0, L2_to_L1D0, Ms) {L1D0DataArrayWrite, L1D0TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2317     c0_copyL2ToL1;
2318     l0_loadDone;
2319     pt_popTriggerQueue;
2320   }
2321
2322   transition(Ms_F1, L2_to_L1D1, Ms) {L1D1DataArrayWrite, L1D1TagArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2323     c1_copyL2ToL1;
2324     l1_loadDone;
2325     pt_popTriggerQueue;
2326   }
2327
2328   transition(Ms_F, L2_to_L1D0, Ms_F1) {L1D0DataArrayWrite, L2DataArrayRead} {
2329     c0_copyL2ToL1;
2330     l0_loadDone;
2331     pt_popTriggerQueue;
2332   }
2333
2334   transition(Ms_F, L2_to_L1D1, Ms_F0) {L1IDataArrayWrite, L2DataArrayRead} {
2335     c1_copyL2ToL1;
2336     l1_loadDone;
2337     pt_popTriggerQueue;
2338   }
2339
2340   transition(M1_Ms, L2_to_L1D0, Ms) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2341     c0_copyL2ToL1;
2342     l0_loadDone;
2343     pt_popTriggerQueue;
2344   }
2345
2346   transition(M0_Ms, L2_to_L1D1, Ms) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2347     c1_copyL2ToL1;
2348     l1_loadDone;
2349     pt_popTriggerQueue;
2350   }
2351
2352   transition(Es_F0, L2_to_L1D0, Es) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2353     c0_copyL2ToL1;
2354     l0_loadDone;
2355     pt_popTriggerQueue;
2356   }
2357
2358   transition(Es_F1, L2_to_L1D1, Es) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2TagArrayWrite, L2DataArrayRead} {
2359     c1_copyL2ToL1;
2360     l1_loadDone;
2361     pt_popTriggerQueue;
2362   }
2363
2364   transition(Es_F, L2_to_L1D0, Es_F1) {L2TagArrayRead, L2DataArrayRead} {
2365     c0_copyL2ToL1;
2366     l0_loadDone;
2367     pt_popTriggerQueue;
2368   }
2369
2370   transition(Es_F, L2_to_L1D1, Es_F0) {L2TagArrayRead, L2DataArrayRead} {
2371     c1_copyL2ToL1;
2372     l1_loadDone;
2373     pt_popTriggerQueue;
2374   }
2375
2376   transition(E0_F, L2_to_L1D0, E0) {L2TagArrayRead, L2DataArrayRead} {
2377     c0_copyL2ToL1;
2378     l0_loadDone;
2379     pt_popTriggerQueue;
2380   }
2381
2382   transition(E1_F, L2_to_L1D1, E1) {L2TagArrayRead, L2DataArrayRead} {
2383     c1_copyL2ToL1;
2384     l1_loadDone;
2385     pt_popTriggerQueue;
2386   }
2387
2388   transition(E1_Es, L2_to_L1D0, Es) {L2TagArrayRead, L2DataArrayRead} {
2389     c0_copyL2ToL1;
2390     l0_loadDone;
2391     pt_popTriggerQueue;
2392   }
2393
2394   transition(E0_Es, L2_to_L1D1, Es) {L2TagArrayRead, L2DataArrayRead} {
2395     c1_copyL2ToL1;
2396     l1_loadDone;
2397     pt_popTriggerQueue;
2398   }
2399
2400   transition(IF_E0S, L2_to_L1D0, I_E0S) {} {
2401     pt_popTriggerQueue;
2402   }
2403
2404   transition(IF_E1S, L2_to_L1D1, I_E1S) {} {
2405     pt_popTriggerQueue;
2406   }
2407
2408   transition(IF_ES, L2_to_L1D0, IF1_ES) {} {
2409     pt_popTriggerQueue;
2410   }
2411
2412   transition(IF_ES, L2_to_L1D1, IF0_ES) {} {
2413     pt_popTriggerQueue;
2414   }
2415
2416   transition(IF0_ES, L2_to_L1D0, I_ES) {} {
2417     pt_popTriggerQueue;
2418   }
2419
2420   transition(IF1_ES, L2_to_L1D1, I_ES) {} {
2421     pt_popTriggerQueue;
2422   }
2423
2424   transition(F_S0, L2_to_L1I, S0) {} {
2425     pt_popTriggerQueue;
2426   }
2427
2428   transition(F_S1, L2_to_L1I, S1) {} {
2429     pt_popTriggerQueue;
2430   }
2431
2432   transition({S_M0, O_M0}, NB_AckM, M0) {L1D0TagArrayWrite, L1D0DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2433     xs0_storeDone;
2434     sdv_sendDoneValid;
2435     uu_sendUnblock;
2436     pr_popResponseQueue;
2437   }
2438
2439   transition({S_M1, O_M1}, NB_AckM, M1) {L1D1TagArrayWrite, L1D1DataArrayWrite, L2DataArrayWrite, L2TagArrayWrite} {
2440     xs1_storeDone;
2441     sdv_sendDoneValid;
2442     uu_sendUnblock;
2443     pr_popResponseQueue;
2444   }
2445
2446   transition(MO_I, NB_AckWB, I) {L2TagArrayWrite} {
2447     wb_data;
2448     ra_sendReplAck;
2449     sdi_sendDoneInvalid;
2450     d_deallocateTBE;
2451     pr_popResponseQueue;
2452   }
2453
2454   transition(ES_I, NB_AckWB, I) {L2TagArrayWrite} {
2455     wb_data;
2456     ra_sendReplAck;
2457     sdi_sendDoneInvalid;
2458     d_deallocateTBE;
2459     pr_popResponseQueue;
2460   }
2461
2462   transition(MO_S0, NB_AckWB, S0) {L2TagArrayWrite} {
2463     wb_data;
2464     i2_invL2;
2465     a2_allocateL2;
2466     sdv_sendDoneValid;
2467     nS_issueRdBlkS;
2468     d_deallocateTBE; // FOO
2469     pr_popResponseQueue;
2470   }
2471
2472   transition(MO_S1, NB_AckWB, S1) {L2TagArrayWrite} {
2473     wb_data;
2474     i2_invL2;
2475     a2_allocateL2;
2476     sdv_sendDoneValid;
2477     nS_issueRdBlkS;
2478     d_deallocateTBE; // FOO
2479     pr_popResponseQueue;
2480   }
2481
2482   // Writeback cancel "ack"
2483   transition(I_C, NB_AckWB, I) {L2TagArrayWrite} {
2484     ss_sendStaleNotification;
2485     sdi_sendDoneInvalid;
2486     d_deallocateTBE;
2487     pr_popResponseQueue;
2488   }
2489
2490   transition(S0_C, NB_AckWB, S0) {L2TagArrayWrite} {
2491     ss_sendStaleNotification;
2492     sdv_sendDoneValid;
2493     pr_popResponseQueue;
2494   }
2495
2496   transition(S1_C, NB_AckWB, S1) {L2TagArrayWrite} {
2497     ss_sendStaleNotification;
2498     sdv_sendDoneValid;
2499     pr_popResponseQueue;
2500   }
2501
2502   transition(S_C, NB_AckWB, S) {L2TagArrayWrite} {
2503     ss_sendStaleNotification;
2504     sdv_sendDoneValid;
2505     pr_popResponseQueue;
2506   }
2507
2508   // Begin Probe Transitions
2509
2510   transition({Ms, M0, M1, O}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2511     forward_eviction_to_cpu0;
2512     forward_eviction_to_cpu1;
2513     pd_sendProbeResponseData;
2514     i2_invL2;
2515     ib_invBothClusters;
2516     pp_popProbeQueue;
2517   }
2518
2519   transition({Es, E0, E1, S, I}, {PrbInvData, PrbInvDataDemand}, I) {L2TagArrayRead, L2TagArrayWrite} {
2520     forward_eviction_to_cpu0;
2521     forward_eviction_to_cpu1;
2522     pi_sendProbeResponseInv;
2523     i2_invL2;
2524     ib_invBothClusters;
2525     ii_invIcache;  // only relevant for S
2526     pp_popProbeQueue;
2527   }
2528
2529   transition(S_C, {PrbInvData, PrbInvDataDemand}, I_C) {L2TagArrayWrite} {
2530     t_allocateTBE;
2531     forward_eviction_to_cpu0;
2532     forward_eviction_to_cpu1;
2533     pi_sendProbeResponseInv;
2534     i2_invL2;
2535     ib_invBothClusters;
2536     ii_invIcache;
2537     pp_popProbeQueue;
2538   }
2539
2540   transition(I_C, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2541     pi_sendProbeResponseInv;
2542     ib_invBothClusters;
2543     pp_popProbeQueue;
2544   }
2545
2546   transition({Ms, M0, M1, O, Es, E0, E1, S, I}, PrbInv, I) {L2TagArrayRead, L2TagArrayWrite} {
2547     forward_eviction_to_cpu0;
2548     forward_eviction_to_cpu1;
2549     pi_sendProbeResponseInv;
2550     i2_invL2; // nothing will happen in I
2551     ib_invBothClusters;
2552     ii_invIcache;
2553     pp_popProbeQueue;
2554   }
2555
2556   transition(S_C, PrbInv, I_C) {L2TagArrayWrite} {
2557     t_allocateTBE;
2558     forward_eviction_to_cpu0;
2559     forward_eviction_to_cpu1;
2560     pi_sendProbeResponseInv;
2561     i2_invL2;
2562     ib_invBothClusters;
2563     ii_invIcache;
2564     pp_popProbeQueue;
2565   }
2566
2567   transition(I_C, PrbInv, I_C) {} {
2568     pi_sendProbeResponseInv;
2569     ib_invBothClusters;
2570     ii_invIcache;
2571     pp_popProbeQueue;
2572   }
2573
2574   transition({Ms, M0, M1, O}, {PrbShrData, PrbShrDataDemand}, O) {L2TagArrayRead, L2TagArrayWrite, L2DataArrayRead} {
2575     pd_sendProbeResponseData;
2576     pp_popProbeQueue;
2577   }
2578
2579   transition({Es, E0, E1, S}, {PrbShrData, PrbShrDataDemand}, S) {L2TagArrayRead, L2TagArrayWrite} {
2580     ph_sendProbeResponseHit;
2581     pp_popProbeQueue;
2582   }
2583
2584   transition(S_C, {PrbShrData, PrbShrDataDemand}) {} {
2585     ph_sendProbeResponseHit;
2586     pp_popProbeQueue;
2587   }
2588
2589   transition({I, I_C}, {PrbShrData, PrbShrDataDemand}) {L2TagArrayRead} {
2590     pb_sendProbeResponseBackprobe;
2591     pp_popProbeQueue;
2592   }
2593
2594   transition({I_M0, I_E0S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2595     pi_sendProbeResponseInv;
2596     ib_invBothClusters;  // must invalidate current data (only relevant for I_M0)
2597     a0_allocateL1D;  // but make sure there is room for incoming data when it arrives
2598     pp_popProbeQueue;
2599   }
2600
2601   transition({I_M1, I_E1S}, {PrbInv, PrbInvData, PrbInvDataDemand}) {} {
2602     pi_sendProbeResponseInv;
2603     ib_invBothClusters; // must invalidate current data (only relevant for I_M1)
2604     a1_allocateL1D;  // but make sure there is room for incoming data when it arrives
2605     pp_popProbeQueue;
2606   }
2607
2608   transition({I_M0M1, I_M1M0, I_M0Ms, I_M1Ms, I_ES}, {PrbInv, PrbInvData, PrbInvDataDemand, PrbShrData, PrbShrDataDemand}) {} {
2609     pi_sendProbeResponseInv;
2610     ib_invBothClusters;
2611     a0_allocateL1D;
2612     a1_allocateL1D;
2613     pp_popProbeQueue;
2614   }
2615
2616   transition({I_M0, I_E0S, I_M1, I_E1S}, {PrbShrData, PrbShrDataDemand}) {} {
2617     pb_sendProbeResponseBackprobe;
2618     pp_popProbeQueue;
2619   }
2620
2621   transition(ES_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2622     pi_sendProbeResponseInv;
2623     ib_invBothClusters;
2624     ii_invIcache;
2625     pp_popProbeQueue;
2626   }
2627
2628   transition(MO_I, {PrbInvData, PrbInvDataDemand}, I_C) {} {
2629     pdt_sendProbeResponseDataFromTBE;
2630     ib_invBothClusters;
2631     ii_invIcache;
2632     pp_popProbeQueue;
2633   }
2634
2635   transition(MO_I, PrbInv, I_C) {} {
2636     pi_sendProbeResponseInv;
2637     ib_invBothClusters;
2638     ii_invIcache;
2639     pp_popProbeQueue;
2640   }
2641
2642   transition(ES_I, PrbInv, I_C) {} {
2643     pi_sendProbeResponseInv;
2644     ib_invBothClusters;
2645     ii_invIcache;
2646     pp_popProbeQueue;
2647   }
2648
2649   transition(ES_I, {PrbShrData, PrbShrDataDemand}, ES_I) {} {
2650     ph_sendProbeResponseHit;
2651     s_setSharedFlip;
2652     pp_popProbeQueue;
2653   }
2654
2655   transition(MO_I, {PrbShrData, PrbShrDataDemand}, MO_I) {} {
2656     pdt_sendProbeResponseDataFromTBE;
2657     s_setSharedFlip;
2658     pp_popProbeQueue;
2659   }
2660
2661   transition(MO_S0, {PrbInvData, PrbInvDataDemand}, S0_C) {L2TagArrayWrite} {
2662     forward_eviction_to_cpu0;
2663     forward_eviction_to_cpu1;
2664     pdt_sendProbeResponseDataFromTBE;
2665     i2_invL2;
2666     a2_allocateL2;
2667     nS_issueRdBlkS;
2668     d_deallocateTBE;
2669     pp_popProbeQueue;
2670   }
2671
2672   transition(MO_S1, {PrbInvData, PrbInvDataDemand}, S1_C) {} {
2673     forward_eviction_to_cpu0;
2674     forward_eviction_to_cpu1;
2675     pdt_sendProbeResponseDataFromTBE;
2676     i2_invL2;
2677     a2_allocateL2;
2678     nS_issueRdBlkS;
2679     d_deallocateTBE;
2680     pp_popProbeQueue;
2681   }
2682
2683   transition(MO_S0, PrbInv, S0_C) {L2TagArrayWrite} {
2684     forward_eviction_to_cpu0;
2685     forward_eviction_to_cpu1;
2686     pi_sendProbeResponseInv;
2687     i2_invL2;
2688     a2_allocateL2;
2689     nS_issueRdBlkS;
2690     d_deallocateTBE;
2691     pp_popProbeQueue;
2692   }
2693
2694   transition(MO_S1, PrbInv, S1_C) {L2TagArrayWrite} {
2695     forward_eviction_to_cpu0;
2696     forward_eviction_to_cpu1;
2697     pi_sendProbeResponseInv;
2698     i2_invL2;
2699     a2_allocateL2;
2700     nS_issueRdBlkS;
2701     d_deallocateTBE;
2702     pp_popProbeQueue;
2703   }
2704
2705   transition({MO_S0, MO_S1}, {PrbShrData, PrbShrDataDemand}) {} {
2706     pdt_sendProbeResponseDataFromTBE;
2707     s_setSharedFlip;
2708     pp_popProbeQueue;
2709   }
2710
2711   transition({S_F0, Es_F0, E0_F, E1_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E0S) {} {
2712     forward_eviction_to_cpu0;
2713     forward_eviction_to_cpu1;
2714     pi_sendProbeResponseInv;
2715     // invalidate everything you've got
2716     ib_invBothClusters;
2717     ii_invIcache;
2718     i2_invL2;
2719     // but make sure you have room for what you need from the fill
2720     a0_allocateL1D;
2721     a2_allocateL2;
2722     n_issueRdBlk;
2723     pp_popProbeQueue;
2724   }
2725
2726   transition({S_F1, Es_F1, E1_F, E0_Es}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_E1S) {} {
2727     forward_eviction_to_cpu0;
2728     forward_eviction_to_cpu1;
2729     pi_sendProbeResponseInv;
2730     // invalidate everything you've got
2731     ib_invBothClusters;
2732     ii_invIcache;
2733     i2_invL2;
2734     // but make sure you have room for what you need from the fill
2735     a1_allocateL1D;
2736     a2_allocateL2;
2737     n_issueRdBlk;
2738     pp_popProbeQueue;
2739   }
2740
2741   transition({S_F, Es_F}, {PrbInvData, PrbInvDataDemand, PrbInv}, IF_ES) {} {
2742     forward_eviction_to_cpu0;
2743     forward_eviction_to_cpu1;
2744     pi_sendProbeResponseInv;
2745     // invalidate everything you've got
2746     ib_invBothClusters;
2747     ii_invIcache;
2748     i2_invL2;
2749     // but make sure you have room for what you need from the fill
2750     a0_allocateL1D;
2751     a1_allocateL1D;
2752     a2_allocateL2;
2753     n_issueRdBlk;
2754     pp_popProbeQueue;
2755   }
2756
2757   transition(Si_F0, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S0) {} {
2758     forward_eviction_to_cpu0;
2759     forward_eviction_to_cpu1;
2760     pi_sendProbeResponseInv;
2761     ib_invBothClusters;
2762     ii_invIcache;
2763     i2_invL2;
2764     ai_allocateL1I;
2765     a2_allocateL2;
2766     nS_issueRdBlkS;
2767     pp_popProbeQueue;
2768   }
2769
2770   transition(Si_F1, {PrbInvData, PrbInvDataDemand, PrbInv}, F_S1) {} {
2771     forward_eviction_to_cpu0;
2772     forward_eviction_to_cpu1;
2773     pi_sendProbeResponseInv;
2774     ib_invBothClusters;
2775     ii_invIcache;
2776     i2_invL2;
2777     ai_allocateL1I;
2778     a2_allocateL2;
2779     nS_issueRdBlkS;
2780     pp_popProbeQueue;
2781   }
2782
2783   transition({Es_F0, E0_F, E1_Es}, {PrbShrData, PrbShrDataDemand}, S_F0) {} {
2784     ph_sendProbeResponseHit;
2785     pp_popProbeQueue;
2786   }
2787
2788   transition({Es_F1, E1_F, E0_Es}, {PrbShrData, PrbShrDataDemand}, S_F1) {} {
2789     ph_sendProbeResponseHit;
2790     pp_popProbeQueue;
2791   }
2792
2793   transition(Es_F, {PrbShrData, PrbShrDataDemand}, S_F) {} {
2794     ph_sendProbeResponseHit;
2795     pp_popProbeQueue;
2796   }
2797
2798   transition({S_F0, S_F1, S_F, Si_F0, Si_F1}, {PrbShrData, PrbShrDataDemand}) {} {
2799     ph_sendProbeResponseHit;
2800     pp_popProbeQueue;
2801   }
2802
2803   transition(S_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {} {
2804     forward_eviction_to_cpu0;
2805     forward_eviction_to_cpu1;
2806     pim_sendProbeResponseInvMs;
2807     ib_invBothClusters;
2808     ii_invIcache;
2809     i2_invL2;
2810     a0_allocateL1D;
2811     a2_allocateL2;
2812     pp_popProbeQueue;
2813   }
2814
2815   transition(O_M0, {PrbInvData, PrbInvDataDemand}, I_M0) {L2DataArrayRead} {
2816     forward_eviction_to_cpu0;
2817     forward_eviction_to_cpu1;
2818     pdm_sendProbeResponseDataMs;
2819     ib_invBothClusters;
2820     ii_invIcache;
2821     i2_invL2;
2822     a0_allocateL1D;
2823     a2_allocateL2;
2824     pp_popProbeQueue;
2825   }
2826
2827   transition({S_M0, O_M0}, {PrbInv}, I_M0) {} {
2828     forward_eviction_to_cpu0;
2829     forward_eviction_to_cpu1;
2830     pim_sendProbeResponseInvMs;
2831     ib_invBothClusters;
2832     ii_invIcache;
2833     i2_invL2;
2834     a0_allocateL1D;
2835     a2_allocateL2;
2836     pp_popProbeQueue;
2837   }
2838
2839   transition(S_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2840     forward_eviction_to_cpu0;
2841     forward_eviction_to_cpu1;
2842     pim_sendProbeResponseInvMs;
2843     ib_invBothClusters;
2844     ii_invIcache;
2845     i2_invL2;
2846     a1_allocateL1D;
2847     a2_allocateL2;
2848     pp_popProbeQueue;
2849   }
2850
2851   transition(O_M1, {PrbInvData, PrbInvDataDemand}, I_M1) {} {
2852     forward_eviction_to_cpu0;
2853     forward_eviction_to_cpu1;
2854     pdm_sendProbeResponseDataMs;
2855     ib_invBothClusters;
2856     ii_invIcache;
2857     i2_invL2;
2858     a1_allocateL1D;
2859     a2_allocateL2;
2860     pp_popProbeQueue;
2861   }
2862
2863   transition({S_M1, O_M1}, {PrbInv}, I_M1) {} {
2864     forward_eviction_to_cpu0;
2865     forward_eviction_to_cpu1;
2866     pim_sendProbeResponseInvMs;
2867     ib_invBothClusters;
2868     ii_invIcache;
2869     i2_invL2;
2870     a1_allocateL1D;
2871     a2_allocateL2;
2872     pp_popProbeQueue;
2873   }
2874
2875   transition({S0, S0_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2876     forward_eviction_to_cpu0;
2877     forward_eviction_to_cpu1;
2878     pi_sendProbeResponseInv;
2879     ib_invBothClusters;
2880     ii_invIcache;
2881     i2_invL2;
2882     ai_allocateL1I;
2883     a2_allocateL2;
2884     pp_popProbeQueue;
2885   }
2886
2887   transition({S1, S1_C}, {PrbInvData, PrbInvDataDemand, PrbInv}) {} {
2888     forward_eviction_to_cpu0;
2889     forward_eviction_to_cpu1;
2890     pi_sendProbeResponseInv;
2891     ib_invBothClusters;
2892     ii_invIcache;
2893     i2_invL2;
2894     ai_allocateL1I;
2895     a2_allocateL2;
2896     pp_popProbeQueue;
2897   }
2898
2899   transition({S_M0, S_M1}, {PrbShrData, PrbShrDataDemand}) {} {
2900     ph_sendProbeResponseHit;
2901     pp_popProbeQueue;
2902   }
2903
2904   transition({O_M0, O_M1}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
2905     pd_sendProbeResponseData;
2906     pp_popProbeQueue;
2907   }
2908
2909   transition({S0, S1, S0_C, S1_C}, {PrbShrData, PrbShrDataDemand}) {} {
2910     pb_sendProbeResponseBackprobe;
2911     pp_popProbeQueue;
2912   }
2913
2914   transition({Ms_F0, M0_F, M1_Ms, O_F0}, {PrbInvData, PrbInvDataDemand}, IF_E0S) {L2DataArrayRead} {
2915     forward_eviction_to_cpu0;
2916     forward_eviction_to_cpu1;
2917     pd_sendProbeResponseData;
2918     ib_invBothClusters;
2919     i2_invL2;
2920     a0_allocateL1D;
2921     a2_allocateL2;
2922     n_issueRdBlk;
2923     pp_popProbeQueue;
2924   }
2925
2926   transition({Ms_F1, M1_F, M0_Ms, O_F1}, {PrbInvData, PrbInvDataDemand}, IF_E1S) {L2DataArrayRead} {
2927     forward_eviction_to_cpu0;
2928     forward_eviction_to_cpu1;
2929     pd_sendProbeResponseData;
2930     ib_invBothClusters;
2931     i2_invL2;
2932     a1_allocateL1D;
2933     a2_allocateL2;
2934     n_issueRdBlk;
2935     pp_popProbeQueue;
2936   }
2937
2938   transition({Ms_F, O_F}, {PrbInvData, PrbInvDataDemand}, IF_ES) {L2DataArrayRead} {
2939     forward_eviction_to_cpu0;
2940     forward_eviction_to_cpu1;
2941     pd_sendProbeResponseData;
2942     ib_invBothClusters;
2943     i2_invL2;
2944     a0_allocateL1D;
2945     a1_allocateL1D;
2946     a2_allocateL2;
2947     n_issueRdBlk;
2948     pp_popProbeQueue;
2949   }
2950
2951   transition({Ms_F0, M0_F, M1_Ms, O_F0}, PrbInv, IF_E0S) {} {
2952     forward_eviction_to_cpu0;
2953     forward_eviction_to_cpu1;
2954     pi_sendProbeResponseInv;
2955     ib_invBothClusters;
2956     i2_invL2;
2957     a0_allocateL1D;
2958     a2_allocateL2;
2959     n_issueRdBlk;
2960     pp_popProbeQueue;
2961   }
2962
2963   transition({Ms_F1, M1_F, M0_Ms, O_F1}, PrbInv, IF_E1S) {} {
2964     forward_eviction_to_cpu0;
2965     forward_eviction_to_cpu1;
2966     pi_sendProbeResponseInv;
2967     ib_invBothClusters;
2968     i2_invL2;
2969     a1_allocateL1D;
2970     a2_allocateL2;
2971     n_issueRdBlk;
2972     pp_popProbeQueue;
2973   }
2974
2975   transition({Ms_F, O_F}, PrbInv, IF_ES) {} {
2976     forward_eviction_to_cpu0;
2977     forward_eviction_to_cpu1;
2978     pi_sendProbeResponseInv;
2979     ib_invBothClusters;
2980     i2_invL2;
2981     a0_allocateL1D;
2982     a1_allocateL1D;
2983     a2_allocateL2;
2984     n_issueRdBlk;
2985     pp_popProbeQueue;
2986   }
2987
2988   transition({Ms_F0, M0_F, M1_Ms}, {PrbShrData, PrbShrDataDemand}, O_F0) {L2DataArrayRead} {
2989     pd_sendProbeResponseData;
2990     pp_popProbeQueue;
2991   }
2992
2993   transition({Ms_F1, M1_F, M0_Ms}, {PrbShrData, PrbShrDataDemand}, O_F1) {} {
2994   }
2995
2996   transition({Ms_F}, {PrbShrData, PrbShrDataDemand}, O_F) {L2DataArrayRead} {
2997     pd_sendProbeResponseData;
2998     pp_popProbeQueue;
2999   }
3000
3001   transition({O_F0, O_F1, O_F}, {PrbShrData, PrbShrDataDemand}) {L2DataArrayRead} {
3002     pd_sendProbeResponseData;
3003     pp_popProbeQueue;
3004   }
3005
3006   // END TRANSITIONS
3007 }
3008
3009