src/mem/protocol/MOESI_CMP_directory-L1cache.sm

   1 /*
   2  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 machine(L1Cache, "Directory protocol")
  30  : Sequencer * sequencer;
  31    CacheMemory * L1Icache;
  32    CacheMemory * L1Dcache;
  33    int l2_select_num_bits;
  34    Cycles request_latency := 2;
  35    Cycles use_timeout_latency := 50;
  36    bool send_evictions;
  37
  38    // Message Queues
  39    // From this node's L1 cache TO the network
  40    // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  41    MessageBuffer * requestFromL1Cache, network="To", virtual_network="0",
  42         vnet_type="request";
  43    // a local L1 -> this L2 bank
  44    MessageBuffer * responseFromL1Cache, network="To", virtual_network="2",
  45         vnet_type="response";
  46
  47    // To this node's L1 cache FROM the network
  48    // a L2 bank -> this L1
  49    MessageBuffer * requestToL1Cache, network="From", virtual_network="0",
  50         vnet_type="request";
  51    // a L2 bank -> this L1
  52    MessageBuffer * responseToL1Cache, network="From", virtual_network="2",
  53         vnet_type="response";
  54 {
  55   // STATES
  56   state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
  57     // Base states
  58     I, AccessPermission:Invalid, desc="Idle";
  59     S, AccessPermission:Read_Only, desc="Shared";
  60     O, AccessPermission:Read_Only, desc="Owned";
  61     M, AccessPermission:Read_Only, desc="Modified (dirty)";
  62     M_W, AccessPermission:Read_Only, desc="Modified (dirty)";
  63     MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
  64     MM_W, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
  65
  66     // Transient States
  67     IM, AccessPermission:Busy, "IM", desc="Issued GetX";
  68     SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have an old copy of the line";
  69     OM, AccessPermission:Read_Only, "SM", desc="Issued GetX, received data";
  70     IS, AccessPermission:Busy, "IS", desc="Issued GetS";
  71     SI, AccessPermission:Busy, "OI", desc="Issued PutS, waiting for ack";
  72     OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
  73     MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
  74     II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
  75   }
  76
  77   // EVENTS
  78   enumeration(Event, desc="Cache events") {
  79     Load,            desc="Load request from the processor";
  80     Ifetch,          desc="I-fetch request from the processor";
  81     Store,           desc="Store request from the processor";
  82     L1_Replacement,  desc="Replacement";
  83
  84     // Requests
  85     Own_GETX,      desc="We observe our own GetX forwarded back to us";
  86     Fwd_GETX,      desc="A GetX from another processor";
  87     Fwd_GETS,      desc="A GetS from another processor";
  88     Fwd_DMA,      desc="A GetS from another processor";
  89     Inv,           desc="Invalidations from the directory";
  90
  91     // Responses
  92     Ack,             desc="Received an ack message";
  93     Data,            desc="Received a data message, responder has a shared copy";
  94     Exclusive_Data,  desc="Received a data message";
  95
  96     Writeback_Ack,   desc="Writeback O.K. from directory";
  97     Writeback_Ack_Data,   desc="Writeback O.K. from directory";
  98     Writeback_Nack,  desc="Writeback not O.K. from directory";
  99
 100     // Triggers
 101     All_acks,                  desc="Received all required data and message acks";
 102
 103     // Timeouts
 104     Use_Timeout, desc="lockout period ended";
 105   }
 106
 107   // TYPES
 108
 109   // CacheEntry
 110   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 111     State CacheState,        desc="cache state";
 112     bool Dirty,              desc="Is the data dirty (different than memory)?";
 113     DataBlock DataBlk,       desc="data for the block";
 114   }
 115
 116   // TBE fields
 117   structure(TBE, desc="...") {
 118     Addr addr,         desc="Physical address for this TBE";
 119     State TBEState,          desc="Transient state";
 120     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 121     bool Dirty,              desc="Is the data dirty (different than memory)?";
 122     int NumPendingMsgs, default="0",     desc="Number of acks/data messages that this processor is waiting for";
 123   }
 124
 125   structure(TBETable, external ="yes") {
 126     TBE lookup(Addr);
 127     void allocate(Addr);
 128     void deallocate(Addr);
 129     bool isPresent(Addr);
 130   }
 131
 132   void set_cache_entry(AbstractCacheEntry b);
 133   void unset_cache_entry();
 134   void set_tbe(TBE b);
 135   void unset_tbe();
 136
 137   MessageBuffer mandatoryQueue, abstract_chip_ptr="true";
 138
 139   TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 140   TimerTable useTimerTable;
 141   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 142
 143   Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
 144     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
 145     if(is_valid(L1Dcache_entry)) {
 146       return L1Dcache_entry;
 147     }
 148
 149     Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
 150     return L1Icache_entry;
 151   }
 152
 153   Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
 154     return static_cast(Entry, "pointer", L1Dcache.lookup(addr));
 155   }
 156
 157   Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
 158     return static_cast(Entry, "pointer", L1Icache.lookup(addr));
 159   }
 160
 161   State getState(TBE tbe, Entry cache_entry, Addr addr) {
 162     if(is_valid(tbe)) {
 163       return tbe.TBEState;
 164     } else if (is_valid(cache_entry)) {
 165       return cache_entry.CacheState;
 166     }
 167     return State:I;
 168   }
 169
 170   void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
 171     assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
 172
 173     if (is_valid(tbe)) {
 174       tbe.TBEState := state;
 175     }
 176
 177     if (is_valid(cache_entry)) {
 178       if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
 179          ((cache_entry.CacheState != State:MM) && (state == State:MM)) ||
 180          ((cache_entry.CacheState != State:S) && (state == State:S)) ||
 181          ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
 182
 183         cache_entry.CacheState := state;
 184         sequencer.checkCoherence(addr);
 185       }
 186       else {
 187         cache_entry.CacheState := state;
 188       }
 189     }
 190   }
 191
 192   AccessPermission getAccessPermission(Addr addr) {
 193     TBE tbe := TBEs.lookup(addr);
 194     if(is_valid(tbe)) {
 195       DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
 196       return L1Cache_State_to_permission(tbe.TBEState);
 197     }
 198
 199     Entry cache_entry := getCacheEntry(addr);
 200     if(is_valid(cache_entry)) {
 201       DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(cache_entry.CacheState));
 202       return L1Cache_State_to_permission(cache_entry.CacheState);
 203     }
 204
 205     DPRINTF(RubySlicc, "AccessPermission_NotPresent\n");
 206     return AccessPermission:NotPresent;
 207   }
 208
 209   void setAccessPermission(Entry cache_entry, Addr addr, State state) {
 210     if (is_valid(cache_entry)) {
 211       cache_entry.changePermission(L1Cache_State_to_permission(state));
 212     }
 213   }
 214
 215   void functionalRead(Addr addr, Packet *pkt) {
 216     Entry cache_entry := getCacheEntry(addr);
 217     if(is_valid(cache_entry)) {
 218       testAndRead(addr, cache_entry.DataBlk, pkt);
 219     } else {
 220       TBE tbe := TBEs.lookup(addr);
 221       if(is_valid(tbe)) {
 222         testAndRead(addr, tbe.DataBlk, pkt);
 223       } else {
 224         error("Data block missing!");
 225       }
 226     }
 227   }
 228
 229   int functionalWrite(Addr addr, Packet *pkt) {
 230     int num_functional_writes := 0;
 231
 232     Entry cache_entry := getCacheEntry(addr);
 233     if(is_valid(cache_entry)) {
 234       num_functional_writes := num_functional_writes +
 235         testAndWrite(addr, cache_entry.DataBlk, pkt);
 236       return num_functional_writes;
 237     }
 238
 239     TBE tbe := TBEs.lookup(addr);
 240     num_functional_writes := num_functional_writes +
 241         testAndWrite(addr, tbe.DataBlk, pkt);
 242     return num_functional_writes;
 243   }
 244
 245   Event mandatory_request_type_to_event(RubyRequestType type) {
 246     if (type == RubyRequestType:LD) {
 247       return Event:Load;
 248     } else if (type == RubyRequestType:IFETCH) {
 249       return Event:Ifetch;
 250     } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
 251       return Event:Store;
 252     } else {
 253       error("Invalid RubyRequestType");
 254     }
 255   }
 256
 257   MessageBuffer triggerQueue;
 258
 259   // ** OUT_PORTS **
 260
 261   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 262   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 263   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 264
 265   // ** IN_PORTS **
 266
 267   // Use Timer
 268   in_port(useTimerTable_in, Addr, useTimerTable) {
 269     if (useTimerTable_in.isReady()) {
 270         trigger(Event:Use_Timeout, useTimerTable.readyAddress(),
 271                 getCacheEntry(useTimerTable.readyAddress()),
 272                 TBEs.lookup(useTimerTable.readyAddress()));
 273     }
 274   }
 275
 276   // Trigger Queue
 277   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 278     if (triggerQueue_in.isReady()) {
 279       peek(triggerQueue_in, TriggerMsg) {
 280         if (in_msg.Type == TriggerType:ALL_ACKS) {
 281           trigger(Event:All_acks, in_msg.addr,
 282                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 283         } else {
 284           error("Unexpected message");
 285         }
 286       }
 287     }
 288   }
 289
 290   // Nothing from the request network
 291
 292   // Request Network
 293   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 294     if (requestNetwork_in.isReady()) {
 295       peek(requestNetwork_in, RequestMsg, block_on="addr") {
 296         assert(in_msg.Destination.isElement(machineID));
 297         DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 298
 299         if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
 300           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
 301             trigger(Event:Own_GETX, in_msg.addr,
 302                     getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 303           } else {
 304             trigger(Event:Fwd_GETX, in_msg.addr,
 305                     getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 306           }
 307         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 308           trigger(Event:Fwd_GETS, in_msg.addr,
 309                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 310         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
 311           trigger(Event:Fwd_DMA, in_msg.addr,
 312                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 313         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 314           trigger(Event:Writeback_Ack, in_msg.addr,
 315                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 316         } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) {
 317           trigger(Event:Writeback_Ack_Data, in_msg.addr,
 318                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 319         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 320           trigger(Event:Writeback_Nack, in_msg.addr,
 321                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 322         } else if (in_msg.Type == CoherenceRequestType:INV) {
 323           trigger(Event:Inv, in_msg.addr,
 324                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 325         } else {
 326           error("Unexpected message");
 327         }
 328       }
 329     }
 330   }
 331
 332   // Response Network
 333   in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
 334     if (responseToL1Cache_in.isReady()) {
 335       peek(responseToL1Cache_in, ResponseMsg, block_on="addr") {
 336         if (in_msg.Type == CoherenceResponseType:ACK) {
 337           trigger(Event:Ack, in_msg.addr,
 338                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 339         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 340           trigger(Event:Data, in_msg.addr,
 341                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 342         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 343           trigger(Event:Exclusive_Data, in_msg.addr,
 344                   getCacheEntry(in_msg.addr), TBEs.lookup(in_msg.addr));
 345         } else {
 346           error("Unexpected message");
 347         }
 348       }
 349     }
 350   }
 351
 352   // Nothing from the unblock network
 353   // Mandatory Queue betweens Node's CPU and it's L1 caches
 354   in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
 355     if (mandatoryQueue_in.isReady()) {
 356       peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
 357
 358         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 359
 360         if (in_msg.Type == RubyRequestType:IFETCH) {
 361           // ** INSTRUCTION ACCESS ***
 362
 363           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 364           if (is_valid(L1Icache_entry)) {
 365             // The tag matches for the L1, so the L1 asks the L2 for it.
 366             trigger(mandatory_request_type_to_event(in_msg.Type),
 367                     in_msg.LineAddress, L1Icache_entry,
 368                     TBEs.lookup(in_msg.LineAddress));
 369           } else {
 370
 371             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 372             // Check to see if it is in the OTHER L1
 373             if (is_valid(L1Dcache_entry)) {
 374               // The block is in the wrong L1, put the request on the queue to the shared L2
 375               trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry,
 376                       TBEs.lookup(in_msg.LineAddress));
 377             }
 378             if (L1Icache.cacheAvail(in_msg.LineAddress)) {
 379               // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
 380               trigger(mandatory_request_type_to_event(in_msg.Type),
 381                       in_msg.LineAddress, L1Icache_entry,
 382                       TBEs.lookup(in_msg.LineAddress));
 383             } else {
 384               // No room in the L1, so we need to make room in the L1
 385               trigger(Event:L1_Replacement,
 386                       L1Icache.cacheProbe(in_msg.LineAddress),
 387                       getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
 388                       TBEs.lookup(L1Icache.cacheProbe(in_msg.LineAddress)));
 389             }
 390           }
 391         } else {
 392           // *** DATA ACCESS ***
 393
 394           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 395           if (is_valid(L1Dcache_entry)) {
 396             // The tag matches for the L1, so the L1 ask the L2 for it
 397             trigger(mandatory_request_type_to_event(in_msg.Type),
 398                     in_msg.LineAddress, L1Dcache_entry,
 399                     TBEs.lookup(in_msg.LineAddress));
 400           } else {
 401
 402             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 403             // Check to see if it is in the OTHER L1
 404             if (is_valid(L1Icache_entry)) {
 405               // The block is in the wrong L1, put the request on the queue to the shared L2
 406               trigger(Event:L1_Replacement, in_msg.LineAddress,
 407                       L1Icache_entry, TBEs.lookup(in_msg.LineAddress));
 408             }
 409             if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
 410               // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
 411               trigger(mandatory_request_type_to_event(in_msg.Type),
 412                       in_msg.LineAddress, L1Dcache_entry,
 413                       TBEs.lookup(in_msg.LineAddress));
 414             } else {
 415               // No room in the L1, so we need to make room in the L1
 416               trigger(Event:L1_Replacement,
 417                       L1Dcache.cacheProbe(in_msg.LineAddress),
 418                       getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
 419                       TBEs.lookup(L1Dcache.cacheProbe(in_msg.LineAddress)));
 420             }
 421           }
 422         }
 423       }
 424     }
 425   }
 426
 427
 428   // ACTIONS
 429
 430   action(a_issueGETS, "a", desc="Issue GETS") {
 431     peek(mandatoryQueue_in, RubyRequest) {
 432       enqueue(requestNetwork_out, RequestMsg,  request_latency) {
 433         out_msg.addr := address;
 434         out_msg.Type := CoherenceRequestType:GETS;
 435         out_msg.Requestor := machineID;
 436         out_msg.RequestorMachine := MachineType:L1Cache;
 437         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 438               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 439         out_msg.MessageSize := MessageSizeType:Request_Control;
 440         out_msg.AccessMode := in_msg.AccessMode;
 441         out_msg.Prefetch := in_msg.Prefetch;
 442       }
 443     }
 444   }
 445
 446   action(b_issueGETX, "b", desc="Issue GETX") {
 447     peek(mandatoryQueue_in, RubyRequest) {
 448       enqueue(requestNetwork_out, RequestMsg, request_latency) {
 449         out_msg.addr := address;
 450         out_msg.Type := CoherenceRequestType:GETX;
 451         out_msg.Requestor := machineID;
 452         out_msg.RequestorMachine := MachineType:L1Cache;
 453         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 454               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 455         out_msg.MessageSize := MessageSizeType:Request_Control;
 456         out_msg.AccessMode := in_msg.AccessMode;
 457         out_msg.Prefetch := in_msg.Prefetch;
 458       }
 459     }
 460   }
 461
 462   action(d_issuePUTX, "d", desc="Issue PUTX") {
 463     enqueue(requestNetwork_out, RequestMsg, request_latency) {
 464       out_msg.addr := address;
 465       out_msg.Type := CoherenceRequestType:PUTX;
 466       out_msg.Requestor := machineID;
 467       out_msg.RequestorMachine := MachineType:L1Cache;
 468       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 469               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 470       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 471     }
 472   }
 473
 474   action(dd_issuePUTO, "\d", desc="Issue PUTO") {
 475     enqueue(requestNetwork_out, RequestMsg, request_latency) {
 476       out_msg.addr := address;
 477       out_msg.Type := CoherenceRequestType:PUTO;
 478       out_msg.Requestor := machineID;
 479       out_msg.RequestorMachine := MachineType:L1Cache;
 480       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 481               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 482       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 483     }
 484   }
 485
 486   action(dd_issuePUTS, "\ds", desc="Issue PUTS") {
 487     enqueue(requestNetwork_out, RequestMsg, request_latency) {
 488       out_msg.addr := address;
 489       out_msg.Type := CoherenceRequestType:PUTS;
 490       out_msg.Requestor := machineID;
 491       out_msg.RequestorMachine := MachineType:L1Cache;
 492       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 493               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 494       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 495     }
 496   }
 497
 498   action(e_sendData, "e", desc="Send data from cache to requestor") {
 499     peek(requestNetwork_in, RequestMsg) {
 500       assert(is_valid(cache_entry));
 501       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 502         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 503           out_msg.addr := address;
 504           out_msg.Type := CoherenceResponseType:DATA;
 505           out_msg.Sender := machineID;
 506           out_msg.SenderMachine := MachineType:L1Cache;
 507           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 508               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 509           out_msg.DataBlk := cache_entry.DataBlk;
 510           // out_msg.Dirty := cache_entry.Dirty;
 511           out_msg.Dirty := false;
 512           out_msg.Acks := in_msg.Acks;
 513           out_msg.MessageSize := MessageSizeType:Response_Data;
 514         }
 515         DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.addr);
 516       }
 517       else {
 518         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 519           out_msg.addr := address;
 520           out_msg.Type := CoherenceResponseType:DATA;
 521           out_msg.Sender := machineID;
 522           out_msg.SenderMachine := MachineType:L1Cache;
 523           out_msg.Destination.add(in_msg.Requestor);
 524           out_msg.DataBlk := cache_entry.DataBlk;
 525           // out_msg.Dirty := cache_entry.Dirty;
 526           out_msg.Dirty := false;
 527           out_msg.Acks := in_msg.Acks;
 528           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 529         }
 530         DPRINTF(RubySlicc, "Sending data to L1\n");
 531       }
 532     }
 533   }
 534
 535   action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
 536     enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 537       assert(is_valid(cache_entry));
 538       out_msg.addr := address;
 539       out_msg.Type := CoherenceResponseType:DATA;
 540       out_msg.Sender := machineID;
 541       out_msg.SenderMachine := MachineType:L1Cache;
 542       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 543               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 544       out_msg.DataBlk := cache_entry.DataBlk;
 545       out_msg.Dirty := cache_entry.Dirty;
 546       out_msg.Acks := 0; // irrelevant
 547       out_msg.MessageSize := MessageSizeType:Response_Data;
 548     }
 549   }
 550
 551   action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
 552     peek(requestNetwork_in, RequestMsg) {
 553       assert(is_valid(cache_entry));
 554       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 555         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 556           out_msg.addr := address;
 557           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 558           out_msg.Sender := machineID;
 559           out_msg.SenderMachine := MachineType:L1Cache;
 560           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 561               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 562           out_msg.DataBlk := cache_entry.DataBlk;
 563           out_msg.Dirty := cache_entry.Dirty;
 564           out_msg.Acks := in_msg.Acks;
 565           out_msg.MessageSize := MessageSizeType:Response_Data;
 566         }
 567         DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
 568       }
 569       else {
 570         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 571           out_msg.addr := address;
 572           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 573           out_msg.Sender := machineID;
 574           out_msg.SenderMachine := MachineType:L1Cache;
 575           out_msg.Destination.add(in_msg.Requestor);
 576           out_msg.DataBlk := cache_entry.DataBlk;
 577           out_msg.Dirty := cache_entry.Dirty;
 578           out_msg.Acks := in_msg.Acks;
 579           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 580         }
 581         DPRINTF(RubySlicc, "Sending exclusive data to L1\n");
 582       }
 583     }
 584   }
 585
 586   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 587     peek(requestNetwork_in, RequestMsg) {
 588       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 589         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 590           out_msg.addr := address;
 591           out_msg.Type := CoherenceResponseType:ACK;
 592           out_msg.Sender := machineID;
 593           out_msg.SenderMachine := MachineType:L1Cache;
 594           out_msg.Destination.add(in_msg.Requestor);
 595           out_msg.Acks := 0 - 1; // -1
 596           out_msg.MessageSize := MessageSizeType:Response_Control;
 597         }
 598       }
 599       else {
 600         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 601           out_msg.addr := address;
 602           out_msg.Type := CoherenceResponseType:ACK;
 603           out_msg.Sender := machineID;
 604           out_msg.SenderMachine := MachineType:L1Cache;
 605           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 606               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 607           out_msg.Acks := 0 - 1; // -1
 608           out_msg.MessageSize := MessageSizeType:Response_Control;
 609         }
 610       }
 611     }
 612   }
 613
 614   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 615     enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 616       out_msg.addr := address;
 617       out_msg.Type := CoherenceResponseType:UNBLOCK;
 618       out_msg.Sender := machineID;
 619       out_msg.SenderMachine := MachineType:L1Cache;
 620       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 621               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 622       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 623     }
 624   }
 625
 626   action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
 627     enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 628       out_msg.addr := address;
 629       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 630       out_msg.Sender := machineID;
 631       out_msg.SenderMachine := MachineType:L1Cache;
 632       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 633               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 634       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 635     }
 636   }
 637
 638   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 639     assert(is_valid(cache_entry));
 640     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 641     sequencer.readCallback(address, cache_entry.DataBlk);
 642   }
 643
 644   action(hx_load_hit, "hx", desc="Notify sequencer the load completed.") {
 645     assert(is_valid(cache_entry));
 646     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 647     sequencer.readCallback(address, cache_entry.DataBlk, true);
 648   }
 649
 650   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 651     assert(is_valid(cache_entry));
 652     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 653     sequencer.writeCallback(address, cache_entry.DataBlk);
 654     cache_entry.Dirty := true;
 655   }
 656
 657   action(xx_store_hit, "\xx", desc="Notify sequencer that store completed.") {
 658     assert(is_valid(cache_entry));
 659     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 660     sequencer.writeCallback(address, cache_entry.DataBlk, true);
 661     cache_entry.Dirty := true;
 662   }
 663
 664   action(i_allocateTBE, "i", desc="Allocate TBE") {
 665     check_allocate(TBEs);
 666     TBEs.allocate(address);
 667     set_tbe(TBEs.lookup(address));
 668     assert(is_valid(cache_entry));
 669     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 670     tbe.Dirty := cache_entry.Dirty;
 671   }
 672
 673   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 674     triggerQueue_in.dequeue();
 675   }
 676
 677   action(jj_unsetUseTimer, "\jj", desc="Unset use timer.") {
 678     useTimerTable.unset(address);
 679   }
 680
 681   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 682     mandatoryQueue_in.dequeue();
 683   }
 684
 685   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 686     requestNetwork_in.dequeue();
 687   }
 688
 689   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 690     peek(responseToL1Cache_in, ResponseMsg) {
 691       assert(is_valid(tbe));
 692       DPRINTF(RubySlicc, "L1 decrementNumberOfMessages: %d\n", in_msg.Acks);
 693       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 694     }
 695   }
 696
 697   action(mm_decrementNumberOfMessages, "\m", desc="Decrement the number of messages for which we're waiting") {
 698     peek(requestNetwork_in, RequestMsg) {
 699       assert(is_valid(tbe));
 700       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 701     }
 702   }
 703
 704   action(n_popResponseQueue, "n", desc="Pop response queue") {
 705     responseToL1Cache_in.dequeue();
 706   }
 707
 708   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 709     assert(is_valid(tbe));
 710     if (tbe.NumPendingMsgs == 0) {
 711       enqueue(triggerQueue_out, TriggerMsg) {
 712         out_msg.addr := address;
 713         out_msg.Type := TriggerType:ALL_ACKS;
 714       }
 715     }
 716   }
 717
 718   action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") {
 719     useTimerTable.set(address, use_timeout_latency);
 720   }
 721
 722   action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
 723     peek(requestNetwork_in, RequestMsg) {
 724       enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 725         out_msg.addr := address;
 726         out_msg.Type := CoherenceResponseType:DMA_ACK;
 727         out_msg.Sender := machineID;
 728         out_msg.SenderMachine := MachineType:L1Cache;
 729         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 730               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 731         out_msg.Dirty := false;
 732         out_msg.Acks := 1;
 733         out_msg.MessageSize := MessageSizeType:Response_Control;
 734       }
 735     }
 736   }
 737
 738   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 739     peek(requestNetwork_in, RequestMsg) {
 740       assert(is_valid(tbe));
 741       if (in_msg.RequestorMachine == MachineType:L1Cache ||
 742           in_msg.RequestorMachine == MachineType:DMA) {
 743         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 744           out_msg.addr := address;
 745           out_msg.Type := CoherenceResponseType:DATA;
 746           out_msg.Sender := machineID;
 747           out_msg.SenderMachine := MachineType:L1Cache;
 748           out_msg.Destination.add(in_msg.Requestor);
 749           out_msg.DataBlk := tbe.DataBlk;
 750           // out_msg.Dirty := tbe.Dirty;
 751           out_msg.Dirty := false;
 752           out_msg.Acks := in_msg.Acks;
 753           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 754         }
 755       }
 756       else {
 757         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 758           out_msg.addr := address;
 759           out_msg.Type := CoherenceResponseType:DATA;
 760           out_msg.Sender := machineID;
 761           out_msg.SenderMachine := MachineType:L1Cache;
 762           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 763               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 764           out_msg.DataBlk := tbe.DataBlk;
 765           // out_msg.Dirty := tbe.Dirty;
 766           out_msg.Dirty := false;
 767           out_msg.Acks := in_msg.Acks;
 768           out_msg.MessageSize := MessageSizeType:Response_Data;
 769         }
 770       }
 771     }
 772   }
 773
 774   action(q_sendExclusiveDataFromTBEToCache, "qq", desc="Send data from TBE to cache") {
 775     peek(requestNetwork_in, RequestMsg) {
 776       assert(is_valid(tbe));
 777       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 778         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 779           out_msg.addr := address;
 780           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 781           out_msg.Sender := machineID;
 782           out_msg.SenderMachine := MachineType:L1Cache;
 783           out_msg.Destination.add(in_msg.Requestor);
 784           out_msg.DataBlk := tbe.DataBlk;
 785           out_msg.Dirty := tbe.Dirty;
 786           out_msg.Acks := in_msg.Acks;
 787           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 788         }
 789       }
 790       else {
 791         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 792           out_msg.addr := address;
 793           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 794           out_msg.Sender := machineID;
 795           out_msg.SenderMachine := MachineType:L1Cache;
 796           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 797               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 798           out_msg.DataBlk := tbe.DataBlk;
 799           out_msg.Dirty := tbe.Dirty;
 800           out_msg.Acks := in_msg.Acks;
 801           out_msg.MessageSize := MessageSizeType:Response_Data;
 802         }
 803       }
 804     }
 805   }
 806
 807   // L2 will usually request data for a writeback
 808   action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
 809     enqueue(responseNetwork_out, ResponseMsg, request_latency) {
 810       assert(is_valid(tbe));
 811       out_msg.addr := address;
 812       out_msg.Sender := machineID;
 813       out_msg.SenderMachine := MachineType:L1Cache;
 814       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 815               l2_select_low_bit, l2_select_num_bits, intToID(0)));
 816       out_msg.Dirty := tbe.Dirty;
 817       if (tbe.Dirty) {
 818         out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
 819       } else {
 820         out_msg.Type := CoherenceResponseType:WRITEBACK_CLEAN_DATA;
 821       }
 822       out_msg.DataBlk := tbe.DataBlk;
 823       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 824     }
 825   }
 826
 827   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 828     TBEs.deallocate(address);
 829     unset_tbe();
 830   }
 831
 832   action(u_writeDataToCache, "u", desc="Write data to cache") {
 833     peek(responseToL1Cache_in, ResponseMsg) {
 834       assert(is_valid(cache_entry));
 835       cache_entry.DataBlk := in_msg.DataBlk;
 836       cache_entry.Dirty := in_msg.Dirty;
 837
 838       if (in_msg.Type == CoherenceResponseType:DATA) {
 839         //assert(in_msg.Dirty == false);
 840       }
 841     }
 842   }
 843
 844   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 845     peek(responseToL1Cache_in, ResponseMsg) {
 846       assert(is_valid(cache_entry));
 847       assert(cache_entry.DataBlk == in_msg.DataBlk);
 848       cache_entry.DataBlk := in_msg.DataBlk;
 849       cache_entry.Dirty := in_msg.Dirty;
 850     }
 851   }
 852
 853   action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 854     if (L1Dcache.isTagPresent(address)) {
 855       L1Dcache.deallocate(address);
 856     } else {
 857       L1Icache.deallocate(address);
 858     }
 859     unset_cache_entry();
 860   }
 861
 862   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 863     if ((is_invalid(cache_entry))) {
 864       set_cache_entry(L1Dcache.allocate(address, new Entry));
 865     }
 866   }
 867
 868   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 869     if ((is_invalid(cache_entry))) {
 870       set_cache_entry(L1Icache.allocate(address, new Entry));
 871     }
 872   }
 873
 874   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
 875     if (send_evictions) {
 876       DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
 877       sequencer.evictionCallback(address);
 878     }
 879   }
 880
 881   action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
 882       ++L1Icache.demand_misses;
 883   }
 884
 885   action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
 886       ++L1Icache.demand_hits;
 887   }
 888
 889   action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
 890       ++L1Dcache.demand_misses;
 891   }
 892
 893   action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
 894       ++L1Dcache.demand_hits;
 895   }
 896
 897   action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {
 898     requestNetwork_in.recycle();
 899   }
 900
 901   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
 902     mandatoryQueue_in.recycle();
 903   }
 904
 905   //*****************************************************
 906   // TRANSITIONS
 907   //*****************************************************
 908
 909   // Transitions for Load/Store/L2_Replacement from transient states
 910   transition({IM, SM, OM, IS, OI, SI, MI, II}, {Store, L1_Replacement}) {
 911     zz_recycleMandatoryQueue;
 912   }
 913
 914   transition({M_W, MM_W}, L1_Replacement) {
 915     zz_recycleMandatoryQueue;
 916   }
 917
 918   transition({M_W, MM_W}, {Fwd_GETS, Fwd_DMA, Fwd_GETX, Own_GETX, Inv}) {
 919     z_recycleRequestQueue;
 920   }
 921
 922   transition({IM, IS, OI, MI, SI, II}, {Load, Ifetch}) {
 923     zz_recycleMandatoryQueue;
 924   }
 925
 926   // Transitions from Idle
 927   transition(I, Load, IS) {
 928     ii_allocateL1DCacheBlock;
 929     i_allocateTBE;
 930     a_issueGETS;
 931     uu_profileDataMiss;
 932     k_popMandatoryQueue;
 933   }
 934
 935   transition(I, Ifetch, IS) {
 936     jj_allocateL1ICacheBlock;
 937     i_allocateTBE;
 938     a_issueGETS;
 939     uu_profileInstMiss;
 940     k_popMandatoryQueue;
 941   }
 942
 943   transition(I, Store, IM) {
 944     ii_allocateL1DCacheBlock;
 945     i_allocateTBE;
 946     b_issueGETX;
 947     uu_profileDataMiss;
 948     k_popMandatoryQueue;
 949   }
 950
 951   transition(I, L1_Replacement) {
 952     kk_deallocateL1CacheBlock;
 953   }
 954
 955   transition(I, Inv) {
 956     f_sendAck;
 957     l_popForwardQueue;
 958   }
 959
 960   transition({S, SM, O, OM, MM, MM_W, M, M_W}, Load) {
 961     h_load_hit;
 962     uu_profileDataHit;
 963     k_popMandatoryQueue;
 964   }
 965
 966   transition({S, SM, O, OM, MM, MM_W, M, M_W}, Ifetch) {
 967     h_load_hit;
 968     uu_profileInstHit;
 969     k_popMandatoryQueue;
 970   }
 971
 972   // Transitions from Shared
 973   transition(S, Store, SM) {
 974     i_allocateTBE;
 975     b_issueGETX;
 976     uu_profileDataMiss;
 977     k_popMandatoryQueue;
 978   }
 979
 980   transition(S, L1_Replacement, SI) {
 981     i_allocateTBE;
 982     dd_issuePUTS;
 983     forward_eviction_to_cpu;
 984     kk_deallocateL1CacheBlock;
 985   }
 986
 987   transition(S, Inv, I) {
 988     f_sendAck;
 989     forward_eviction_to_cpu;
 990     l_popForwardQueue;
 991   }
 992
 993   transition(S, Fwd_GETS) {
 994     e_sendData;
 995     l_popForwardQueue;
 996   }
 997
 998   transition(S, Fwd_DMA) {
 999     e_sendData;
1000     ub_dmaUnblockL2Cache;
1001     l_popForwardQueue;
1002   }
1003
1004   // Transitions from Owned
1005   transition(O, Store, OM) {
1006     i_allocateTBE;
1007     b_issueGETX;
1008     uu_profileDataMiss;
1009     k_popMandatoryQueue;
1010   }
1011
1012   transition(O, L1_Replacement, OI) {
1013     i_allocateTBE;
1014     dd_issuePUTO;
1015     forward_eviction_to_cpu;
1016     kk_deallocateL1CacheBlock;
1017   }
1018
1019   transition(O, Fwd_GETX, I) {
1020     ee_sendDataExclusive;
1021     forward_eviction_to_cpu;
1022     l_popForwardQueue;
1023   }
1024
1025   transition(O, Fwd_GETS) {
1026     e_sendData;
1027     l_popForwardQueue;
1028   }
1029
1030   transition(O, Fwd_DMA) {
1031     e_sendData;
1032     ub_dmaUnblockL2Cache;
1033     l_popForwardQueue;
1034   }
1035
1036   // Transitions from MM
1037   transition({MM, MM_W}, Store) {
1038     hh_store_hit;
1039     uu_profileDataHit;
1040     k_popMandatoryQueue;
1041   }
1042
1043   transition(MM, L1_Replacement, MI) {
1044     i_allocateTBE;
1045     d_issuePUTX;
1046     forward_eviction_to_cpu;
1047     kk_deallocateL1CacheBlock;
1048   }
1049
1050   transition(MM, Fwd_GETX, I) {
1051     ee_sendDataExclusive;
1052     forward_eviction_to_cpu;
1053     l_popForwardQueue;
1054   }
1055
1056   transition(MM, Fwd_GETS, I) {
1057     ee_sendDataExclusive;
1058     forward_eviction_to_cpu;
1059     l_popForwardQueue;
1060   }
1061
1062   transition(MM, Fwd_DMA, MM) {
1063     e_sendData;
1064     ub_dmaUnblockL2Cache;
1065     l_popForwardQueue;
1066   }
1067
1068   // Transitions from M
1069   transition(M, Store, MM) {
1070     hh_store_hit;
1071     uu_profileDataHit;
1072     k_popMandatoryQueue;
1073   }
1074
1075   transition(M_W, Store, MM_W) {
1076     hh_store_hit;
1077     uu_profileDataHit;
1078     k_popMandatoryQueue;
1079   }
1080
1081   transition(M, L1_Replacement, MI) {
1082     i_allocateTBE;
1083     d_issuePUTX;
1084     forward_eviction_to_cpu;
1085     kk_deallocateL1CacheBlock;
1086   }
1087
1088   transition(M, Fwd_GETX, I) {
1089     // e_sendData;
1090     ee_sendDataExclusive;
1091     forward_eviction_to_cpu;
1092     l_popForwardQueue;
1093   }
1094
1095   transition(M, Fwd_GETS, O) {
1096     e_sendData;
1097     l_popForwardQueue;
1098   }
1099
1100   transition(M, Fwd_DMA) {
1101     e_sendData;
1102     ub_dmaUnblockL2Cache;
1103     l_popForwardQueue;
1104   }
1105
1106   // Transitions from IM
1107
1108   transition(IM, Inv) {
1109     f_sendAck;
1110     l_popForwardQueue;
1111   }
1112
1113   transition(IM, Ack) {
1114     m_decrementNumberOfMessages;
1115     o_checkForCompletion;
1116     n_popResponseQueue;
1117   }
1118
1119   transition(IM, {Exclusive_Data, Data}, OM) {
1120     u_writeDataToCache;
1121     m_decrementNumberOfMessages;
1122     o_checkForCompletion;
1123     n_popResponseQueue;
1124   }
1125
1126   // Transitions from SM
1127   transition(SM, Inv, IM) {
1128     f_sendAck;
1129     forward_eviction_to_cpu;
1130     l_popForwardQueue;
1131   }
1132
1133   transition(SM, Ack) {
1134     m_decrementNumberOfMessages;
1135     o_checkForCompletion;
1136     n_popResponseQueue;
1137   }
1138
1139   transition(SM, {Data, Exclusive_Data}, OM) {
1140     // v_writeDataToCacheVerify;
1141     m_decrementNumberOfMessages;
1142     o_checkForCompletion;
1143     n_popResponseQueue;
1144   }
1145
1146   transition(SM, Fwd_GETS) {
1147     e_sendData;
1148     l_popForwardQueue;
1149   }
1150
1151   transition(SM, Fwd_DMA) {
1152     e_sendData;
1153     ub_dmaUnblockL2Cache;
1154     l_popForwardQueue;
1155   }
1156
1157   // Transitions from OM
1158   transition(OM, Own_GETX) {
1159     mm_decrementNumberOfMessages;
1160     o_checkForCompletion;
1161     l_popForwardQueue;
1162   }
1163
1164
1165   // transition(OM, Fwd_GETX, OMF) {
1166   transition(OM, Fwd_GETX, IM) {
1167     ee_sendDataExclusive;
1168     l_popForwardQueue;
1169   }
1170
1171   transition(OM, Fwd_GETS) {
1172     e_sendData;
1173     l_popForwardQueue;
1174   }
1175
1176   transition(OM, Fwd_DMA) {
1177     e_sendData;
1178     ub_dmaUnblockL2Cache;
1179     l_popForwardQueue;
1180   }
1181
1182   //transition({OM, OMF}, Ack) {
1183   transition(OM, Ack) {
1184     m_decrementNumberOfMessages;
1185     o_checkForCompletion;
1186     n_popResponseQueue;
1187   }
1188
1189   transition(OM, All_acks, MM_W) {
1190     xx_store_hit;
1191     gg_sendUnblockExclusive;
1192     s_deallocateTBE;
1193     o_scheduleUseTimeout;
1194     j_popTriggerQueue;
1195   }
1196
1197   transition(MM_W, Use_Timeout, MM) {
1198     jj_unsetUseTimer;
1199   }
1200
1201   // Transitions from IS
1202
1203   transition(IS, Inv) {
1204     f_sendAck;
1205     l_popForwardQueue;
1206   }
1207
1208   transition(IS, Data, S) {
1209     u_writeDataToCache;
1210     m_decrementNumberOfMessages;
1211     hx_load_hit;
1212     g_sendUnblock;
1213     s_deallocateTBE;
1214     n_popResponseQueue;
1215   }
1216
1217   transition(IS, Exclusive_Data, M_W) {
1218     u_writeDataToCache;
1219     m_decrementNumberOfMessages;
1220     hx_load_hit;
1221     gg_sendUnblockExclusive;
1222     o_scheduleUseTimeout;
1223     s_deallocateTBE;
1224     n_popResponseQueue;
1225   }
1226
1227   transition(M_W, Use_Timeout, M) {
1228     jj_unsetUseTimer;
1229   }
1230
1231   // Transitions from OI/MI
1232
1233   transition(MI, Fwd_GETS, OI) {
1234     q_sendDataFromTBEToCache;
1235     l_popForwardQueue;
1236   }
1237
1238   transition(MI, Fwd_DMA) {
1239     q_sendDataFromTBEToCache;
1240     ub_dmaUnblockL2Cache;
1241     l_popForwardQueue;
1242   }
1243
1244   transition(MI, Fwd_GETX, II) {
1245     q_sendExclusiveDataFromTBEToCache;
1246     l_popForwardQueue;
1247   }
1248
1249   transition({SI, OI}, Fwd_GETS) {
1250     q_sendDataFromTBEToCache;
1251     l_popForwardQueue;
1252   }
1253
1254   transition({SI, OI}, Fwd_DMA) {
1255     q_sendDataFromTBEToCache;
1256     ub_dmaUnblockL2Cache;
1257     l_popForwardQueue;
1258   }
1259
1260   transition(OI, Fwd_GETX, II) {
1261     q_sendExclusiveDataFromTBEToCache;
1262     l_popForwardQueue;
1263   }
1264
1265   transition({SI, OI, MI}, Writeback_Ack_Data, I) {
1266     qq_sendWBDataFromTBEToL2;  // always send data
1267     s_deallocateTBE;
1268     l_popForwardQueue;
1269   }
1270
1271   transition({SI, OI, MI}, Writeback_Ack, I) {
1272     g_sendUnblock;
1273     s_deallocateTBE;
1274     l_popForwardQueue;
1275   }
1276
1277   transition({MI, OI}, Writeback_Nack, OI) {
1278     // FIXME: This might cause deadlock by re-using the writeback
1279     // channel, we should handle this case differently.
1280     dd_issuePUTO;
1281     l_popForwardQueue;
1282   }
1283
1284   // Transitions from II
1285   transition(II, {Writeback_Ack, Writeback_Ack_Data}, I) {
1286     g_sendUnblock;
1287     s_deallocateTBE;
1288     l_popForwardQueue;
1289   }
1290
1291   // transition({II, SI}, Writeback_Nack, I) {
1292   transition(II, Writeback_Nack, I) {
1293     s_deallocateTBE;
1294     l_popForwardQueue;
1295   }
1296
1297   transition(SI, Writeback_Nack) {
1298     dd_issuePUTS;
1299     l_popForwardQueue;
1300   }
1301
1302   transition(II, Inv) {
1303     f_sendAck;
1304     l_popForwardQueue;
1305   }
1306
1307   transition(SI, Inv, II) {
1308     f_sendAck;
1309     l_popForwardQueue;
1310   }
1311 }