src/mem/protocol/MOESI_CMP_directory-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 machine(L1Cache, "Directory protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int request_latency = 2
  41 {
  42
  43   // NODE L1 CACHE
  44   // From this node's L1 cache TO the network
  45   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  46   MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
  47   MessageBuffer foo, network="To", virtual_network="1", ordered="false";
  48   // a local L1 -> this L2 bank
  49   MessageBuffer responseFromL1Cache, network="To", virtual_network="2", ordered="false";
  50 //  MessageBuffer writebackFromL1Cache, network="To", virtual_network="3", ordered="false";
  51
  52
  53   // To this node's L1 cache FROM the network
  54   // a L2 bank -> this L1
  55   MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
  56   MessageBuffer goo, network="From", virtual_network="1", ordered="false";
  57   // a L2 bank -> this L1
  58   MessageBuffer responseToL1Cache, network="From", virtual_network="2", ordered="false";
  59
  60
  61
  62   // STATES
  63   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  64     // Base states
  65     I, desc="Idle";
  66     S, desc="Shared";
  67     O, desc="Owned";
  68     M, desc="Modified (dirty)";
  69     M_W, desc="Modified (dirty)";
  70     MM, desc="Modified (dirty and locally modified)";
  71     MM_W, desc="Modified (dirty and locally modified)";
  72
  73     // Transient States
  74     IM, "IM", desc="Issued GetX";
  75     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  76     OM, "SM", desc="Issued GetX, received data";
  77     IS, "IS", desc="Issued GetS";
  78     SI, "OI", desc="Issued PutS, waiting for ack";
  79     OI, "OI", desc="Issued PutO, waiting for ack";
  80     MI, "MI", desc="Issued PutX, waiting for ack";
  81     II, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
  82   }
  83
  84   // EVENTS
  85   enumeration(Event, desc="Cache events") {
  86     Load,            desc="Load request from the processor";
  87     Ifetch,          desc="I-fetch request from the processor";
  88     Store,           desc="Store request from the processor";
  89     L1_Replacement,  desc="Replacement";
  90
  91     // Requests
  92     Own_GETX,      desc="We observe our own GetX forwarded back to us";
  93     Fwd_GETX,      desc="A GetX from another processor";
  94     Fwd_GETS,      desc="A GetS from another processor";
  95     Fwd_DMA,      desc="A GetS from another processor";
  96     Inv,           desc="Invalidations from the directory";
  97
  98     // Responses
  99     Ack,             desc="Received an ack message";
 100     Data,            desc="Received a data message, responder has a shared copy";
 101     Exclusive_Data,  desc="Received a data message";
 102
 103     Writeback_Ack,   desc="Writeback O.K. from directory";
 104     Writeback_Ack_Data,   desc="Writeback O.K. from directory";
 105     Writeback_Nack,  desc="Writeback not O.K. from directory";
 106
 107     // Triggers
 108     All_acks,                  desc="Received all required data and message acks";
 109
 110     // Timeouts
 111     Use_Timeout, desc="lockout period ended";
 112   }
 113
 114   // TYPES
 115
 116   // CacheEntry
 117   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 118     State CacheState,        desc="cache state";
 119     bool Dirty,              desc="Is the data dirty (different than memory)?";
 120     DataBlock DataBlk,       desc="data for the block";
 121   }
 122
 123   // TBE fields
 124   structure(TBE, desc="...") {
 125     Address Address,         desc="Physical address for this TBE";
 126     State TBEState,          desc="Transient state";
 127     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 128     bool Dirty,              desc="Is the data dirty (different than memory)?";
 129     int NumPendingMsgs, default="0",     desc="Number of acks/data messages that this processor is waiting for";
 130   }
 131
 132   external_type(TBETable) {
 133     TBE lookup(Address);
 134     void allocate(Address);
 135     void deallocate(Address);
 136     bool isPresent(Address);
 137   }
 138
 139
 140   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 141
 142   TBETable TBEs, template_hack="<L1Cache_TBE>";
 143   TimerTable useTimerTable;
 144   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 145
 146   Entry getCacheEntry(Address addr), return_by_ref="yes" {
 147     if (L1DcacheMemory.isTagPresent(addr)) {
 148       return static_cast(Entry, L1DcacheMemory[addr]);
 149     } else {
 150       return static_cast(Entry, L1IcacheMemory[addr]);
 151     }
 152   }
 153
 154   void changePermission(Address addr, AccessPermission permission) {
 155     if (L1DcacheMemory.isTagPresent(addr)) {
 156       return L1DcacheMemory.changePermission(addr, permission);
 157     } else {
 158       return L1IcacheMemory.changePermission(addr, permission);
 159     }
 160   }
 161
 162   bool isCacheTagPresent(Address addr) {
 163     return (L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
 164   }
 165
 166   State getState(Address addr) {
 167     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 168
 169     if(TBEs.isPresent(addr)) {
 170       return TBEs[addr].TBEState;
 171     } else if (isCacheTagPresent(addr)) {
 172       return getCacheEntry(addr).CacheState;
 173     }
 174     return State:I;
 175   }
 176
 177   void setState(Address addr, State state) {
 178     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 179
 180     if (TBEs.isPresent(addr)) {
 181       TBEs[addr].TBEState := state;
 182     }
 183
 184     if (isCacheTagPresent(addr)) {
 185       if ( ((getCacheEntry(addr).CacheState != State:M) && (state == State:M)) ||
 186          ((getCacheEntry(addr).CacheState != State:MM) && (state == State:MM)) ||
 187          ((getCacheEntry(addr).CacheState != State:S) && (state == State:S)) ||
 188          ((getCacheEntry(addr).CacheState != State:O) && (state == State:O)) ) {
 189
 190         getCacheEntry(addr).CacheState := state;
 191         sequencer.checkCoherence(addr);
 192       }
 193       else {
 194         getCacheEntry(addr).CacheState := state;
 195       }
 196
 197       // Set permission
 198       if (state == State:MM || state == State:MM_W) {
 199         changePermission(addr, AccessPermission:Read_Write);
 200       } else if ((state == State:S) ||
 201                  (state == State:O) ||
 202                  (state == State:M) ||
 203                  (state == State:M_W) ||
 204                  (state == State:SM) ||
 205                  (state == State:OM)) {
 206         changePermission(addr, AccessPermission:Read_Only);
 207       } else {
 208         changePermission(addr, AccessPermission:Invalid);
 209       }
 210     }
 211   }
 212
 213   bool isBlockExclusive(Address addr) {
 214
 215     if (isCacheTagPresent(addr)) {
 216       if ( (getCacheEntry(addr).CacheState == State:M) || (getCacheEntry(addr).CacheState == State:MM)
 217            || (getCacheEntry(addr).CacheState == State:MI) || (getCacheEntry(addr).CacheState == State:MM_W)
 218          ) {
 219         return true;
 220       }
 221     }
 222
 223     return false;
 224   }
 225
 226   bool isBlockShared(Address addr) {
 227     if (isCacheTagPresent(addr)) {
 228       if ( (getCacheEntry(addr).CacheState == State:S) || (getCacheEntry(addr).CacheState == State:O)
 229            || (getCacheEntry(addr).CacheState == State:SM)
 230            || (getCacheEntry(addr).CacheState == State:OI)
 231            || (getCacheEntry(addr).CacheState == State:SI)
 232            || (getCacheEntry(addr).CacheState == State:OM)
 233            ) {
 234         return true;
 235       }
 236     }
 237
 238     return false;
 239   }
 240
 241
 242   Event mandatory_request_type_to_event(CacheRequestType type) {
 243     if (type == CacheRequestType:LD) {
 244       return Event:Load;
 245     } else if (type == CacheRequestType:IFETCH) {
 246       return Event:Ifetch;
 247     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 248       return Event:Store;
 249     } else {
 250       error("Invalid CacheRequestType");
 251     }
 252   }
 253
 254   MessageBuffer triggerQueue, ordered="true";
 255
 256   // ** OUT_PORTS **
 257
 258   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 259   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 260   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 261   out_port(foo_out, ResponseMsg, foo);
 262
 263   // ** IN_PORTS **
 264
 265   // Use Timer
 266   in_port(useTimerTable_in, Address, useTimerTable) {
 267     if (useTimerTable_in.isReady()) {
 268         trigger(Event:Use_Timeout, useTimerTable.readyAddress());
 269     }
 270   }
 271
 272
 273   in_port(goo_in, RequestMsg, goo) {
 274     if (goo_in.isReady()) {
 275       peek(goo_in, RequestMsg) {
 276         assert(false);
 277       }
 278     }
 279   }
 280
 281   // Trigger Queue
 282   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 283     if (triggerQueue_in.isReady()) {
 284       peek(triggerQueue_in, TriggerMsg) {
 285         if (in_msg.Type == TriggerType:ALL_ACKS) {
 286           trigger(Event:All_acks, in_msg.Address);
 287         } else {
 288           error("Unexpected message");
 289         }
 290       }
 291     }
 292   }
 293
 294   // Nothing from the request network
 295
 296   // Request Network
 297   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 298     if (requestNetwork_in.isReady()) {
 299       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 300         assert(in_msg.Destination.isElement(machineID));
 301         DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 302 if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
 303           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
 304             trigger(Event:Own_GETX, in_msg.Address);
 305           } else {
 306             trigger(Event:Fwd_GETX, in_msg.Address);
 307           }
 308         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 309           trigger(Event:Fwd_GETS, in_msg.Address);
 310         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
 311           trigger(Event:Fwd_DMA, in_msg.Address);
 312         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 313           trigger(Event:Writeback_Ack, in_msg.Address);
 314         } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) {
 315           trigger(Event:Writeback_Ack_Data, in_msg.Address);
 316         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 317           trigger(Event:Writeback_Nack, in_msg.Address);
 318         } else if (in_msg.Type == CoherenceRequestType:INV) {
 319           trigger(Event:Inv, in_msg.Address);
 320         } else {
 321           error("Unexpected message");
 322         }
 323       }
 324     }
 325   }
 326
 327   // Response Network
 328   in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
 329     if (responseToL1Cache_in.isReady()) {
 330       peek(responseToL1Cache_in, ResponseMsg, block_on="Address") {
 331         if (in_msg.Type == CoherenceResponseType:ACK) {
 332           trigger(Event:Ack, in_msg.Address);
 333         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 334           trigger(Event:Data, in_msg.Address);
 335         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 336           trigger(Event:Exclusive_Data, in_msg.Address);
 337         } else {
 338           error("Unexpected message");
 339         }
 340       }
 341     }
 342   }
 343
 344   // Nothing from the unblock network
 345   // Mandatory Queue betweens Node's CPU and it's L1 caches
 346   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 347     if (mandatoryQueue_in.isReady()) {
 348       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 349
 350         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 351
 352         if (in_msg.Type == CacheRequestType:IFETCH) {
 353           // ** INSTRUCTION ACCESS ***
 354
 355           // Check to see if it is in the OTHER L1
 356           if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
 357             // The block is in the wrong L1, put the request on the queue to the shared L2
 358             trigger(Event:L1_Replacement, in_msg.LineAddress);
 359           }
 360           if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
 361             // The tag matches for the L1, so the L1 asks the L2 for it.
 362             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
 363           } else {
 364             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 365               // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
 366               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
 367             } else {
 368               // No room in the L1, so we need to make room in the L1
 369               trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress));
 370             }
 371           }
 372         } else {
 373           // *** DATA ACCESS ***
 374
 375           // Check to see if it is in the OTHER L1
 376           if (L1IcacheMemory.isTagPresent(in_msg.LineAddress)) {
 377             // The block is in the wrong L1, put the request on the queue to the shared L2
 378             trigger(Event:L1_Replacement, in_msg.LineAddress);
 379           }
 380           if (L1DcacheMemory.isTagPresent(in_msg.LineAddress)) {
 381             // The tag matches for the L1, so the L1 ask the L2 for it
 382             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
 383           } else {
 384             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 385               // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
 386               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
 387             } else {
 388               // No room in the L1, so we need to make room in the L1
 389               trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress));
 390             }
 391           }
 392         }
 393       }
 394     }
 395   }
 396
 397
 398   // ACTIONS
 399
 400   action(a_issueGETS, "a", desc="Issue GETS") {
 401     peek(mandatoryQueue_in, CacheMsg) {
 402       enqueue(requestNetwork_out, RequestMsg, latency= request_latency) {
 403         out_msg.Address := address;
 404         out_msg.Type := CoherenceRequestType:GETS;
 405         out_msg.Requestor := machineID;
 406         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 407                                                   l2_select_low_bit, l2_select_num_bits));
 408         out_msg.MessageSize := MessageSizeType:Request_Control;
 409         out_msg.AccessMode := in_msg.AccessMode;
 410         out_msg.Prefetch := in_msg.Prefetch;
 411       }
 412     }
 413   }
 414
 415   action(b_issueGETX, "b", desc="Issue GETX") {
 416     peek(mandatoryQueue_in, CacheMsg) {
 417       enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 418         out_msg.Address := address;
 419         out_msg.Type := CoherenceRequestType:GETX;
 420         out_msg.Requestor := machineID;
 421         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 422                                                   l2_select_low_bit, l2_select_num_bits));
 423         out_msg.MessageSize := MessageSizeType:Request_Control;
 424         out_msg.AccessMode := in_msg.AccessMode;
 425         out_msg.Prefetch := in_msg.Prefetch;
 426       }
 427     }
 428   }
 429
 430   action(d_issuePUTX, "d", desc="Issue PUTX") {
 431     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 432     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 433       out_msg.Address := address;
 434       out_msg.Type := CoherenceRequestType:PUTX;
 435       out_msg.Requestor := machineID;
 436       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 437                                                 l2_select_low_bit, l2_select_num_bits));
 438       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 439     }
 440   }
 441
 442   action(dd_issuePUTO, "\d", desc="Issue PUTO") {
 443     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 444     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 445       out_msg.Address := address;
 446       out_msg.Type := CoherenceRequestType:PUTO;
 447       out_msg.Requestor := machineID;
 448       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 449                                                 l2_select_low_bit, l2_select_num_bits));
 450       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 451     }
 452   }
 453
 454   action(dd_issuePUTS, "\ds", desc="Issue PUTS") {
 455     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 456     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 457       out_msg.Address := address;
 458       out_msg.Type := CoherenceRequestType:PUTS;
 459       out_msg.Requestor := machineID;
 460       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 461                                                 l2_select_low_bit, l2_select_num_bits));
 462       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 463     }
 464   }
 465
 466   action(e_sendData, "e", desc="Send data from cache to requestor") {
 467     peek(requestNetwork_in, RequestMsg) {
 468       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 469         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 470           out_msg.Address := address;
 471           out_msg.Type := CoherenceResponseType:DATA;
 472           out_msg.Sender := machineID;
 473           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 474                                                     l2_select_low_bit, l2_select_num_bits));
 475           out_msg.DataBlk := getCacheEntry(address).DataBlk;
 476           // out_msg.Dirty := getCacheEntry(address).Dirty;
 477           out_msg.Dirty := false;
 478           out_msg.Acks := in_msg.Acks;
 479           out_msg.MessageSize := MessageSizeType:Response_Data;
 480         }
 481         DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Address);
 482       }
 483       else {
 484         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 485           out_msg.Address := address;
 486           out_msg.Type := CoherenceResponseType:DATA;
 487           out_msg.Sender := machineID;
 488           out_msg.Destination.add(in_msg.Requestor);
 489           out_msg.DataBlk := getCacheEntry(address).DataBlk;
 490           // out_msg.Dirty := getCacheEntry(address).Dirty;
 491           out_msg.Dirty := false;
 492           out_msg.Acks := in_msg.Acks;
 493           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 494         }
 495         DPRINTF(RubySlicc, "Sending data to L1\n");
 496       }
 497     }
 498   }
 499
 500   action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
 501     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 502       out_msg.Address := address;
 503       out_msg.Type := CoherenceResponseType:DATA;
 504       out_msg.Sender := machineID;
 505       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 506                                                 l2_select_low_bit, l2_select_num_bits));
 507       out_msg.DataBlk := getCacheEntry(address).DataBlk;
 508       out_msg.Dirty := getCacheEntry(address).Dirty;
 509       out_msg.Acks := 0; // irrelevant
 510       out_msg.MessageSize := MessageSizeType:Response_Data;
 511     }
 512   }
 513
 514
 515   action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
 516     peek(requestNetwork_in, RequestMsg) {
 517       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 518         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 519           out_msg.Address := address;
 520           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 521           out_msg.Sender := machineID;
 522           out_msg.SenderMachine := MachineType:L1Cache;
 523           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 524                                                     l2_select_low_bit, l2_select_num_bits));
 525           out_msg.DataBlk := getCacheEntry(address).DataBlk;
 526           out_msg.Dirty := getCacheEntry(address).Dirty;
 527           out_msg.Acks := in_msg.Acks;
 528           out_msg.MessageSize := MessageSizeType:Response_Data;
 529         }
 530         DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
 531       }
 532       else {
 533         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 534           out_msg.Address := address;
 535           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 536           out_msg.Sender := machineID;
 537           out_msg.SenderMachine := MachineType:L1Cache;
 538           out_msg.Destination.add(in_msg.Requestor);
 539           out_msg.DataBlk := getCacheEntry(address).DataBlk;
 540           out_msg.Dirty := getCacheEntry(address).Dirty;
 541           out_msg.Acks := in_msg.Acks;
 542           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 543         }
 544         DPRINTF(RubySlicc, "Sending exclusive data to L1\n");
 545       }
 546     }
 547   }
 548
 549   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 550     peek(requestNetwork_in, RequestMsg) {
 551       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 552         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 553           out_msg.Address := address;
 554           out_msg.Type := CoherenceResponseType:ACK;
 555           out_msg.Sender := machineID;
 556           out_msg.SenderMachine := MachineType:L1Cache;
 557           out_msg.Destination.add(in_msg.Requestor);
 558           out_msg.Acks := 0 - 1; // -1
 559           out_msg.MessageSize := MessageSizeType:Response_Control;
 560         }
 561       }
 562       else {
 563         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 564           out_msg.Address := address;
 565           out_msg.Type := CoherenceResponseType:ACK;
 566           out_msg.Sender := machineID;
 567           out_msg.SenderMachine := MachineType:L1Cache;
 568           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 569                                                     l2_select_low_bit, l2_select_num_bits));
 570           out_msg.Acks := 0 - 1; // -1
 571           out_msg.MessageSize := MessageSizeType:Response_Control;
 572         }
 573       }
 574     }
 575   }
 576
 577   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 578     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 579       out_msg.Address := address;
 580       out_msg.Type := CoherenceResponseType:UNBLOCK;
 581       out_msg.Sender := machineID;
 582       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 583                                                 l2_select_low_bit, l2_select_num_bits));
 584       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 585     }
 586   }
 587
 588   action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
 589     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 590       out_msg.Address := address;
 591       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 592       out_msg.Sender := machineID;
 593       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 594                                                 l2_select_low_bit, l2_select_num_bits));
 595       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 596     }
 597   }
 598
 599   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 600     DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
 601     sequencer.readCallback(address, getCacheEntry(address).DataBlk);
 602   }
 603
 604   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 605     DPRINTF(RubySlicc, "%s\n", getCacheEntry(address).DataBlk);
 606     sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
 607     getCacheEntry(address).Dirty := true;
 608   }
 609
 610   action(i_allocateTBE, "i", desc="Allocate TBE") {
 611     check_allocate(TBEs);
 612     TBEs.allocate(address);
 613     TBEs[address].DataBlk := getCacheEntry(address).DataBlk; // Data only used for writebacks
 614     TBEs[address].Dirty := getCacheEntry(address).Dirty;
 615   }
 616
 617   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 618     triggerQueue_in.dequeue();
 619   }
 620
 621   action(jj_unsetUseTimer, "\jj", desc="Unset use timer.") {
 622     useTimerTable.unset(address);
 623   }
 624
 625   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 626     mandatoryQueue_in.dequeue();
 627   }
 628
 629   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 630     requestNetwork_in.dequeue();
 631   }
 632
 633   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 634     peek(responseToL1Cache_in, ResponseMsg) {
 635       DPRINTF(RubySlicc, "L1 decrementNumberOfMessages: %d\n", in_msg.Acks);
 636       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
 637     }
 638   }
 639
 640   action(mm_decrementNumberOfMessages, "\m", desc="Decrement the number of messages for which we're waiting") {
 641     peek(requestNetwork_in, RequestMsg) {
 642       TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
 643     }
 644   }
 645
 646   action(n_popResponseQueue, "n", desc="Pop response queue") {
 647     responseToL1Cache_in.dequeue();
 648   }
 649
 650   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 651     if (TBEs[address].NumPendingMsgs == 0) {
 652       enqueue(triggerQueue_out, TriggerMsg) {
 653         out_msg.Address := address;
 654         out_msg.Type := TriggerType:ALL_ACKS;
 655       }
 656     }
 657   }
 658
 659   action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") {
 660     useTimerTable.set(address, 50);
 661   }
 662
 663
 664   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 665     peek(requestNetwork_in, RequestMsg) {
 666       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 667         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 668           out_msg.Address := address;
 669           out_msg.Type := CoherenceResponseType:DATA;
 670           out_msg.Sender := machineID;
 671           out_msg.Destination.add(in_msg.Requestor);
 672           out_msg.DataBlk := TBEs[address].DataBlk;
 673           // out_msg.Dirty := TBEs[address].Dirty;
 674           out_msg.Dirty := false;
 675           out_msg.Acks := in_msg.Acks;
 676           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 677         }
 678       }
 679       else {
 680         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 681           out_msg.Address := address;
 682           out_msg.Type := CoherenceResponseType:DATA;
 683           out_msg.Sender := machineID;
 684           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 685                                                     l2_select_low_bit, l2_select_num_bits));
 686           out_msg.DataBlk := TBEs[address].DataBlk;
 687           // out_msg.Dirty := TBEs[address].Dirty;
 688           out_msg.Dirty := false;
 689           out_msg.Acks := in_msg.Acks;
 690           out_msg.MessageSize := MessageSizeType:Response_Data;
 691         }
 692       }
 693     }
 694   }
 695
 696   action(q_sendExclusiveDataFromTBEToCache, "qq", desc="Send data from TBE to cache") {
 697     peek(requestNetwork_in, RequestMsg) {
 698       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 699         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 700           out_msg.Address := address;
 701           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 702           out_msg.Sender := machineID;
 703           out_msg.Destination.add(in_msg.Requestor);
 704           out_msg.DataBlk := TBEs[address].DataBlk;
 705           out_msg.Dirty := TBEs[address].Dirty;
 706           out_msg.Acks := in_msg.Acks;
 707           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 708         }
 709       }
 710       else {
 711         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 712           out_msg.Address := address;
 713           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 714           out_msg.Sender := machineID;
 715           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 716                                                     l2_select_low_bit, l2_select_num_bits));
 717           out_msg.DataBlk := TBEs[address].DataBlk;
 718           out_msg.Dirty := TBEs[address].Dirty;
 719           out_msg.Acks := in_msg.Acks;
 720           out_msg.MessageSize := MessageSizeType:Response_Data;
 721         }
 722       }
 723     }
 724   }
 725
 726
 727   // L2 will usually request data for a writeback
 728   action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
 729     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 730       out_msg.Address := address;
 731       out_msg.Sender := machineID;
 732       out_msg.SenderMachine := MachineType:L1Cache;
 733       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 734                                                 l2_select_low_bit, l2_select_num_bits));
 735       out_msg.Dirty := TBEs[address].Dirty;
 736       if (TBEs[address].Dirty) {
 737         out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
 738       } else {
 739         out_msg.Type := CoherenceResponseType:WRITEBACK_CLEAN_DATA;
 740       }
 741       out_msg.DataBlk := TBEs[address].DataBlk;
 742       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 743     }
 744   }
 745
 746   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 747     TBEs.deallocate(address);
 748   }
 749
 750   action(u_writeDataToCache, "u", desc="Write data to cache") {
 751     peek(responseToL1Cache_in, ResponseMsg) {
 752       getCacheEntry(address).DataBlk := in_msg.DataBlk;
 753       getCacheEntry(address).Dirty := in_msg.Dirty;
 754
 755       if (in_msg.Type == CoherenceResponseType:DATA) {
 756         //assert(in_msg.Dirty == false);
 757       }
 758     }
 759
 760   }
 761
 762   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 763     peek(responseToL1Cache_in, ResponseMsg) {
 764       assert(getCacheEntry(address).DataBlk == in_msg.DataBlk);
 765       getCacheEntry(address).DataBlk := in_msg.DataBlk;
 766       getCacheEntry(address).Dirty := in_msg.Dirty;
 767     }
 768   }
 769
 770   action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 771     if (L1DcacheMemory.isTagPresent(address)) {
 772       L1DcacheMemory.deallocate(address);
 773     } else {
 774       L1IcacheMemory.deallocate(address);
 775     }
 776   }
 777
 778   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 779     if (L1DcacheMemory.isTagPresent(address) == false) {
 780       L1DcacheMemory.allocate(address, new Entry);
 781     }
 782   }
 783
 784   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 785     if (L1IcacheMemory.isTagPresent(address) == false) {
 786       L1IcacheMemory.allocate(address, new Entry);
 787     }
 788   }
 789
 790
 791
 792   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
 793     peek(mandatoryQueue_in, CacheMsg) {
 794       //      profile_miss(in_msg);
 795     }
 796   }
 797
 798   action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {
 799     requestNetwork_in.recycle();
 800   }
 801
 802   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
 803     mandatoryQueue_in.recycle();
 804   }
 805
 806   //*****************************************************
 807   // TRANSITIONS
 808   //*****************************************************
 809
 810   // Transitions for Load/Store/L2_Replacement from transient states
 811   transition({IM, SM, OM, IS, OI, SI, MI, II}, {Store, L1_Replacement}) {
 812     zz_recycleMandatoryQueue;
 813   }
 814
 815   transition({M_W, MM_W}, L1_Replacement) {
 816     zz_recycleMandatoryQueue;
 817   }
 818
 819   transition({M_W, MM_W}, {Fwd_GETS, Fwd_DMA, Fwd_GETX, Own_GETX, Inv}) {
 820     z_recycleRequestQueue;
 821   }
 822
 823   transition({IM, IS, OI, MI, SI, II}, {Load, Ifetch}) {
 824     zz_recycleMandatoryQueue;
 825   }
 826
 827   // Transitions from Idle
 828   transition(I, Load, IS) {
 829     ii_allocateL1DCacheBlock;
 830     i_allocateTBE;
 831     a_issueGETS;
 832     // uu_profileMiss;
 833     k_popMandatoryQueue;
 834   }
 835
 836   transition(I, Ifetch, IS) {
 837     jj_allocateL1ICacheBlock;
 838     i_allocateTBE;
 839     a_issueGETS;
 840     // uu_profileMiss;
 841     k_popMandatoryQueue;
 842   }
 843
 844   transition(I, Store, IM) {
 845     ii_allocateL1DCacheBlock;
 846     i_allocateTBE;
 847     b_issueGETX;
 848     // uu_profileMiss;
 849     k_popMandatoryQueue;
 850   }
 851
 852   transition(I, L1_Replacement) {
 853     kk_deallocateL1CacheBlock;
 854   }
 855
 856   transition(I, Inv) {
 857     f_sendAck;
 858     l_popForwardQueue;
 859   }
 860
 861   // Transitions from Shared
 862   transition({S, SM}, {Load, Ifetch}) {
 863     h_load_hit;
 864     k_popMandatoryQueue;
 865   }
 866
 867   transition(S, Store, SM) {
 868     i_allocateTBE;
 869     b_issueGETX;
 870     // uu_profileMiss;
 871     k_popMandatoryQueue;
 872   }
 873
 874   transition(S, L1_Replacement, SI) {
 875     i_allocateTBE;
 876     dd_issuePUTS;
 877     kk_deallocateL1CacheBlock;
 878   }
 879
 880   transition(S, Inv, I) {
 881     f_sendAck;
 882     l_popForwardQueue;
 883   }
 884
 885   transition(S, {Fwd_GETS, Fwd_DMA}) {
 886     e_sendData;
 887     l_popForwardQueue;
 888   }
 889
 890   // Transitions from Owned
 891   transition({O, OM}, {Load, Ifetch}) {
 892     h_load_hit;
 893     k_popMandatoryQueue;
 894   }
 895
 896   transition(O, Store, OM) {
 897     i_allocateTBE;
 898     b_issueGETX;
 899     // uu_profileMiss;
 900     k_popMandatoryQueue;
 901   }
 902
 903   transition(O, L1_Replacement, OI) {
 904     i_allocateTBE;
 905     dd_issuePUTO;
 906     kk_deallocateL1CacheBlock;
 907   }
 908
 909   transition(O, Fwd_GETX, I) {
 910     ee_sendDataExclusive;
 911     l_popForwardQueue;
 912   }
 913
 914   transition(O, {Fwd_GETS, Fwd_DMA}) {
 915     e_sendData;
 916     l_popForwardQueue;
 917   }
 918
 919   // Transitions from MM
 920   transition({MM, MM_W}, {Load, Ifetch}) {
 921     h_load_hit;
 922     k_popMandatoryQueue;
 923   }
 924
 925   transition({MM, MM_W}, Store) {
 926     hh_store_hit;
 927     k_popMandatoryQueue;
 928   }
 929
 930   transition(MM, L1_Replacement, MI) {
 931     i_allocateTBE;
 932     d_issuePUTX;
 933     kk_deallocateL1CacheBlock;
 934   }
 935
 936   transition(MM, Fwd_GETX, I) {
 937     ee_sendDataExclusive;
 938     l_popForwardQueue;
 939   }
 940
 941   transition(MM, Fwd_GETS, I) {
 942     ee_sendDataExclusive;
 943     l_popForwardQueue;
 944   }
 945
 946   transition(MM, Fwd_DMA, MM) {
 947     //ee_sendDataExclusive;
 948     e_sendData;
 949     l_popForwardQueue;
 950   }
 951
 952   // Transitions from M
 953   transition({M, M_W}, {Load, Ifetch}) {
 954     h_load_hit;
 955     k_popMandatoryQueue;
 956   }
 957
 958   transition(M, Store, MM) {
 959     hh_store_hit;
 960     k_popMandatoryQueue;
 961   }
 962
 963   transition(M_W, Store, MM_W) {
 964     hh_store_hit;
 965     k_popMandatoryQueue;
 966   }
 967
 968   transition(M, L1_Replacement, MI) {
 969     i_allocateTBE;
 970     d_issuePUTX;
 971     kk_deallocateL1CacheBlock;
 972   }
 973
 974   transition(M, Fwd_GETX, I) {
 975     // e_sendData;
 976     ee_sendDataExclusive;
 977     l_popForwardQueue;
 978   }
 979
 980   transition(M, Fwd_GETS, O) {
 981     e_sendData;
 982     l_popForwardQueue;
 983   }
 984
 985   transition(M, Fwd_DMA, M) {
 986     e_sendData;
 987     l_popForwardQueue;
 988   }
 989
 990   // Transitions from IM
 991
 992   transition(IM, Inv) {
 993     f_sendAck;
 994     l_popForwardQueue;
 995   }
 996
 997   transition(IM, Ack) {
 998     m_decrementNumberOfMessages;
 999     o_checkForCompletion;
1000     n_popResponseQueue;
1001   }
1002
1003   transition(IM, {Exclusive_Data, Data}, OM) {
1004     u_writeDataToCache;
1005     m_decrementNumberOfMessages;
1006     o_checkForCompletion;
1007     n_popResponseQueue;
1008   }
1009
1010   // Transitions from SM
1011   transition(SM, Inv, IM) {
1012     f_sendAck;
1013     l_popForwardQueue;
1014   }
1015
1016   transition(SM, Ack) {
1017     m_decrementNumberOfMessages;
1018     o_checkForCompletion;
1019     n_popResponseQueue;
1020   }
1021
1022   transition(SM, {Data, Exclusive_Data}, OM) {
1023     // v_writeDataToCacheVerify;
1024     m_decrementNumberOfMessages;
1025     o_checkForCompletion;
1026     n_popResponseQueue;
1027   }
1028
1029   transition(SM, {Fwd_DMA, Fwd_GETS}) {
1030     e_sendData;
1031     l_popForwardQueue;
1032   }
1033
1034   // Transitions from OM
1035   transition(OM, Own_GETX) {
1036     mm_decrementNumberOfMessages;
1037     o_checkForCompletion;
1038     l_popForwardQueue;
1039   }
1040
1041
1042   // transition(OM, Fwd_GETX, OMF) {
1043   transition(OM, Fwd_GETX, IM) {
1044     ee_sendDataExclusive;
1045     l_popForwardQueue;
1046   }
1047
1048   transition(OM, {Fwd_DMA, Fwd_GETS}, OM) {
1049     e_sendData;
1050     l_popForwardQueue;
1051   }
1052
1053   //transition({OM, OMF}, Ack) {
1054   transition(OM, Ack) {
1055     m_decrementNumberOfMessages;
1056     o_checkForCompletion;
1057     n_popResponseQueue;
1058   }
1059
1060   transition(OM, All_acks, MM_W) {
1061     hh_store_hit;
1062     gg_sendUnblockExclusive;
1063     s_deallocateTBE;
1064     o_scheduleUseTimeout;
1065     j_popTriggerQueue;
1066   }
1067
1068   transition(MM_W, Use_Timeout, MM) {
1069     jj_unsetUseTimer;
1070   }
1071
1072   // Transitions from IS
1073
1074   transition(IS, Inv) {
1075     f_sendAck;
1076     l_popForwardQueue;
1077   }
1078
1079   transition(IS, Data, S) {
1080     u_writeDataToCache;
1081     m_decrementNumberOfMessages;
1082     h_load_hit;
1083     g_sendUnblock;
1084     s_deallocateTBE;
1085     n_popResponseQueue;
1086   }
1087
1088   transition(IS, Exclusive_Data, M_W) {
1089     u_writeDataToCache;
1090     m_decrementNumberOfMessages;
1091     h_load_hit;
1092     gg_sendUnblockExclusive;
1093     o_scheduleUseTimeout;
1094     s_deallocateTBE;
1095     n_popResponseQueue;
1096   }
1097
1098   transition(M_W, Use_Timeout, M) {
1099     jj_unsetUseTimer;
1100   }
1101
1102   // Transitions from OI/MI
1103
1104   transition(MI, Fwd_GETS, OI) {
1105     q_sendDataFromTBEToCache;
1106     l_popForwardQueue;
1107   }
1108
1109   transition(MI, Fwd_DMA, MI) {
1110     q_sendDataFromTBEToCache;
1111     l_popForwardQueue;
1112   }
1113
1114   transition(MI, Fwd_GETX, II) {
1115     q_sendExclusiveDataFromTBEToCache;
1116     l_popForwardQueue;
1117   }
1118
1119   transition({SI, OI}, {Fwd_DMA, Fwd_GETS}) {
1120     q_sendDataFromTBEToCache;
1121     l_popForwardQueue;
1122   }
1123
1124   transition(OI, Fwd_GETX, II) {
1125     q_sendExclusiveDataFromTBEToCache;
1126     l_popForwardQueue;
1127   }
1128
1129   transition({SI, OI, MI}, Writeback_Ack_Data, I) {
1130     qq_sendWBDataFromTBEToL2;  // always send data
1131     s_deallocateTBE;
1132     l_popForwardQueue;
1133   }
1134
1135   transition({SI, OI, MI}, Writeback_Ack, I) {
1136     g_sendUnblock;
1137     s_deallocateTBE;
1138     l_popForwardQueue;
1139   }
1140
1141   transition({MI, OI}, Writeback_Nack, OI) {
1142     // FIXME: This might cause deadlock by re-using the writeback
1143     // channel, we should handle this case differently.
1144     dd_issuePUTO;
1145     l_popForwardQueue;
1146   }
1147
1148   // Transitions from II
1149   transition(II, {Writeback_Ack, Writeback_Ack_Data}, I) {
1150     g_sendUnblock;
1151     s_deallocateTBE;
1152     l_popForwardQueue;
1153   }
1154
1155   // transition({II, SI}, Writeback_Nack, I) {
1156   transition(II, Writeback_Nack, I) {
1157     s_deallocateTBE;
1158     l_popForwardQueue;
1159   }
1160
1161   transition(SI, Writeback_Nack) {
1162     dd_issuePUTS;
1163     l_popForwardQueue;
1164   }
1165
1166   transition(II, Inv) {
1167     f_sendAck;
1168     l_popForwardQueue;
1169   }
1170
1171   transition(SI, Inv, II) {
1172     f_sendAck;
1173     l_popForwardQueue;
1174   }
1175 }
1176