src/mem/protocol/MOESI_CMP_directory-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 machine(L1Cache, "Directory protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int request_latency = 2
  41 {
  42
  43   // NODE L1 CACHE
  44   // From this node's L1 cache TO the network
  45   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  46   MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
  47   MessageBuffer foo, network="To", virtual_network="1", ordered="false";
  48   // a local L1 -> this L2 bank
  49   MessageBuffer responseFromL1Cache, network="To", virtual_network="2", ordered="false";
  50 //  MessageBuffer writebackFromL1Cache, network="To", virtual_network="3", ordered="false";
  51
  52
  53   // To this node's L1 cache FROM the network
  54   // a L2 bank -> this L1
  55   MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
  56   MessageBuffer goo, network="From", virtual_network="1", ordered="false";
  57   // a L2 bank -> this L1
  58   MessageBuffer responseToL1Cache, network="From", virtual_network="2", ordered="false";
  59
  60
  61
  62   // STATES
  63   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  64     // Base states
  65     I, desc="Idle";
  66     S, desc="Shared";
  67     O, desc="Owned";
  68     M, desc="Modified (dirty)";
  69     M_W, desc="Modified (dirty)";
  70     MM, desc="Modified (dirty and locally modified)";
  71     MM_W, desc="Modified (dirty and locally modified)";
  72
  73     // Transient States
  74     IM, "IM", desc="Issued GetX";
  75     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  76     OM, "SM", desc="Issued GetX, received data";
  77     IS, "IS", desc="Issued GetS";
  78     SI, "OI", desc="Issued PutS, waiting for ack";
  79     OI, "OI", desc="Issued PutO, waiting for ack";
  80     MI, "MI", desc="Issued PutX, waiting for ack";
  81     II, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
  82   }
  83
  84   // EVENTS
  85   enumeration(Event, desc="Cache events") {
  86     Load,            desc="Load request from the processor";
  87     Ifetch,          desc="I-fetch request from the processor";
  88     Store,           desc="Store request from the processor";
  89     L1_Replacement,  desc="Replacement";
  90
  91     // Requests
  92     Own_GETX,      desc="We observe our own GetX forwarded back to us";
  93     Fwd_GETX,      desc="A GetX from another processor";
  94     Fwd_GETS,      desc="A GetS from another processor";
  95     Fwd_DMA,      desc="A GetS from another processor";
  96     Inv,           desc="Invalidations from the directory";
  97
  98     // Responses
  99     Ack,             desc="Received an ack message";
 100     Data,            desc="Received a data message, responder has a shared copy";
 101     Exclusive_Data,  desc="Received a data message";
 102
 103     Writeback_Ack,   desc="Writeback O.K. from directory";
 104     Writeback_Ack_Data,   desc="Writeback O.K. from directory";
 105     Writeback_Nack,  desc="Writeback not O.K. from directory";
 106
 107     // Triggers
 108     All_acks,                  desc="Received all required data and message acks";
 109
 110     // Timeouts
 111     Use_Timeout, desc="lockout period ended";
 112   }
 113
 114   // TYPES
 115
 116   // CacheEntry
 117   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 118     State CacheState,        desc="cache state";
 119     bool Dirty,              desc="Is the data dirty (different than memory)?";
 120     DataBlock DataBlk,       desc="data for the block";
 121   }
 122
 123   // TBE fields
 124   structure(TBE, desc="...") {
 125     Address Address,         desc="Physical address for this TBE";
 126     State TBEState,          desc="Transient state";
 127     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 128     bool Dirty,              desc="Is the data dirty (different than memory)?";
 129     int NumPendingMsgs, default="0",     desc="Number of acks/data messages that this processor is waiting for";
 130   }
 131
 132   external_type(TBETable) {
 133     TBE lookup(Address);
 134     void allocate(Address);
 135     void deallocate(Address);
 136     bool isPresent(Address);
 137   }
 138
 139   void set_cache_entry(AbstractCacheEntry b);
 140   void unset_cache_entry();
 141   void set_tbe(TBE b);
 142   void unset_tbe();
 143
 144   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 145
 146   TBETable TBEs, template_hack="<L1Cache_TBE>";
 147   TimerTable useTimerTable;
 148   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 149
 150   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 151     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 152     if(is_valid(L1Dcache_entry)) {
 153       return L1Dcache_entry;
 154     }
 155
 156     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 157     return L1Icache_entry;
 158   }
 159
 160   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 161     return static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 162   }
 163
 164   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 165     return static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 166   }
 167
 168   State getState(TBE tbe, Entry cache_entry, Address addr) {
 169     if(is_valid(tbe)) {
 170       return tbe.TBEState;
 171     } else if (is_valid(cache_entry)) {
 172       return cache_entry.CacheState;
 173     }
 174     return State:I;
 175   }
 176
 177   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 178     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 179
 180     if (is_valid(tbe)) {
 181       tbe.TBEState := state;
 182     }
 183
 184     if (is_valid(cache_entry)) {
 185       if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
 186          ((cache_entry.CacheState != State:MM) && (state == State:MM)) ||
 187          ((cache_entry.CacheState != State:S) && (state == State:S)) ||
 188          ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
 189
 190         cache_entry.CacheState := state;
 191         sequencer.checkCoherence(addr);
 192       }
 193       else {
 194         cache_entry.CacheState := state;
 195       }
 196
 197       // Set permission
 198       if (state == State:MM || state == State:MM_W) {
 199         cache_entry.changePermission(AccessPermission:Read_Write);
 200       } else if ((state == State:S) ||
 201                  (state == State:O) ||
 202                  (state == State:M) ||
 203                  (state == State:M_W) ||
 204                  (state == State:SM) ||
 205                  (state == State:OM)) {
 206         cache_entry.changePermission(AccessPermission:Read_Only);
 207       } else {
 208         cache_entry.changePermission(AccessPermission:Invalid);
 209       }
 210     }
 211   }
 212
 213   Event mandatory_request_type_to_event(CacheRequestType type) {
 214     if (type == CacheRequestType:LD) {
 215       return Event:Load;
 216     } else if (type == CacheRequestType:IFETCH) {
 217       return Event:Ifetch;
 218     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 219       return Event:Store;
 220     } else {
 221       error("Invalid CacheRequestType");
 222     }
 223   }
 224
 225   MessageBuffer triggerQueue, ordered="true";
 226
 227   // ** OUT_PORTS **
 228
 229   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 230   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 231   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 232   out_port(foo_out, ResponseMsg, foo);
 233
 234   // ** IN_PORTS **
 235
 236   // Use Timer
 237   in_port(useTimerTable_in, Address, useTimerTable) {
 238     if (useTimerTable_in.isReady()) {
 239         trigger(Event:Use_Timeout, useTimerTable.readyAddress(),
 240                 getCacheEntry(useTimerTable.readyAddress()),
 241                 TBEs[useTimerTable.readyAddress()]);
 242     }
 243   }
 244
 245
 246   in_port(goo_in, RequestMsg, goo) {
 247     if (goo_in.isReady()) {
 248       peek(goo_in, RequestMsg) {
 249         assert(false);
 250       }
 251     }
 252   }
 253
 254   // Trigger Queue
 255   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 256     if (triggerQueue_in.isReady()) {
 257       peek(triggerQueue_in, TriggerMsg) {
 258         if (in_msg.Type == TriggerType:ALL_ACKS) {
 259           trigger(Event:All_acks, in_msg.Address,
 260                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 261         } else {
 262           error("Unexpected message");
 263         }
 264       }
 265     }
 266   }
 267
 268   // Nothing from the request network
 269
 270   // Request Network
 271   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 272     if (requestNetwork_in.isReady()) {
 273       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 274         assert(in_msg.Destination.isElement(machineID));
 275         DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 276
 277         if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
 278           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
 279             trigger(Event:Own_GETX, in_msg.Address,
 280                     getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 281           } else {
 282             trigger(Event:Fwd_GETX, in_msg.Address,
 283                     getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 284           }
 285         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 286           trigger(Event:Fwd_GETS, in_msg.Address,
 287                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 288         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
 289           trigger(Event:Fwd_DMA, in_msg.Address,
 290                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 291         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 292           trigger(Event:Writeback_Ack, in_msg.Address,
 293                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 294         } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) {
 295           trigger(Event:Writeback_Ack_Data, in_msg.Address,
 296                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 297         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 298           trigger(Event:Writeback_Nack, in_msg.Address,
 299                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 300         } else if (in_msg.Type == CoherenceRequestType:INV) {
 301           trigger(Event:Inv, in_msg.Address,
 302                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 303         } else {
 304           error("Unexpected message");
 305         }
 306       }
 307     }
 308   }
 309
 310   // Response Network
 311   in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
 312     if (responseToL1Cache_in.isReady()) {
 313       peek(responseToL1Cache_in, ResponseMsg, block_on="Address") {
 314         if (in_msg.Type == CoherenceResponseType:ACK) {
 315           trigger(Event:Ack, in_msg.Address,
 316                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 317         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 318           trigger(Event:Data, in_msg.Address,
 319                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 320         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 321           trigger(Event:Exclusive_Data, in_msg.Address,
 322                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 323         } else {
 324           error("Unexpected message");
 325         }
 326       }
 327     }
 328   }
 329
 330   // Nothing from the unblock network
 331   // Mandatory Queue betweens Node's CPU and it's L1 caches
 332   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 333     if (mandatoryQueue_in.isReady()) {
 334       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 335
 336         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 337
 338         if (in_msg.Type == CacheRequestType:IFETCH) {
 339           // ** INSTRUCTION ACCESS ***
 340
 341           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 342           // Check to see if it is in the OTHER L1
 343           if (is_valid(L1Dcache_entry)) {
 344             // The block is in the wrong L1, put the request on the queue to the shared L2
 345             trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry,
 346                     TBEs[in_msg.LineAddress]);
 347           }
 348
 349           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 350           if (is_valid(L1Icache_entry)) {
 351             // The tag matches for the L1, so the L1 asks the L2 for it.
 352             trigger(mandatory_request_type_to_event(in_msg.Type),
 353                     in_msg.LineAddress, L1Icache_entry,
 354                     TBEs[in_msg.LineAddress]);
 355           } else {
 356             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 357               // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
 358               trigger(mandatory_request_type_to_event(in_msg.Type),
 359                       in_msg.LineAddress, L1Icache_entry,
 360                       TBEs[in_msg.LineAddress]);
 361             } else {
 362               // No room in the L1, so we need to make room in the L1
 363               trigger(Event:L1_Replacement,
 364                       L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 365                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 366                       TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 367             }
 368           }
 369         } else {
 370           // *** DATA ACCESS ***
 371
 372           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 373           // Check to see if it is in the OTHER L1
 374           if (is_valid(L1Icache_entry)) {
 375             // The block is in the wrong L1, put the request on the queue to the shared L2
 376             trigger(Event:L1_Replacement, in_msg.LineAddress,
 377                     L1Icache_entry, TBEs[in_msg.LineAddress]);
 378           }
 379
 380           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 381           if (is_valid(L1Dcache_entry)) {
 382             // The tag matches for the L1, so the L1 ask the L2 for it
 383             trigger(mandatory_request_type_to_event(in_msg.Type),
 384                     in_msg.LineAddress, L1Dcache_entry,
 385                     TBEs[in_msg.LineAddress]);
 386           } else {
 387             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 388               // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
 389               trigger(mandatory_request_type_to_event(in_msg.Type),
 390                       in_msg.LineAddress, L1Dcache_entry,
 391                       TBEs[in_msg.LineAddress]);
 392             } else {
 393               // No room in the L1, so we need to make room in the L1
 394               trigger(Event:L1_Replacement,
 395                       L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 396                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 397                       TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 398             }
 399           }
 400         }
 401       }
 402     }
 403   }
 404
 405
 406   // ACTIONS
 407
 408   action(a_issueGETS, "a", desc="Issue GETS") {
 409     peek(mandatoryQueue_in, CacheMsg) {
 410       enqueue(requestNetwork_out, RequestMsg, latency= request_latency) {
 411         out_msg.Address := address;
 412         out_msg.Type := CoherenceRequestType:GETS;
 413         out_msg.Requestor := machineID;
 414         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 415               l2_select_low_bit, l2_select_num_bits));
 416         out_msg.MessageSize := MessageSizeType:Request_Control;
 417         out_msg.AccessMode := in_msg.AccessMode;
 418         out_msg.Prefetch := in_msg.Prefetch;
 419       }
 420     }
 421   }
 422
 423   action(b_issueGETX, "b", desc="Issue GETX") {
 424     peek(mandatoryQueue_in, CacheMsg) {
 425       enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 426         out_msg.Address := address;
 427         out_msg.Type := CoherenceRequestType:GETX;
 428         out_msg.Requestor := machineID;
 429         out_msg.RequestorMachine := MachineType:L1Cache;
 430         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 431               l2_select_low_bit, l2_select_num_bits));
 432         out_msg.MessageSize := MessageSizeType:Request_Control;
 433         out_msg.AccessMode := in_msg.AccessMode;
 434         out_msg.Prefetch := in_msg.Prefetch;
 435       }
 436     }
 437   }
 438
 439   action(d_issuePUTX, "d", desc="Issue PUTX") {
 440     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 441     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 442       out_msg.Address := address;
 443       out_msg.Type := CoherenceRequestType:PUTX;
 444       out_msg.Requestor := machineID;
 445       out_msg.RequestorMachine := MachineType:L1Cache;
 446       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 447             l2_select_low_bit, l2_select_num_bits));
 448       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 449     }
 450   }
 451
 452   action(dd_issuePUTO, "\d", desc="Issue PUTO") {
 453     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 454     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 455       out_msg.Address := address;
 456       out_msg.Type := CoherenceRequestType:PUTO;
 457       out_msg.Requestor := machineID;
 458       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 459             l2_select_low_bit, l2_select_num_bits));
 460       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 461     }
 462   }
 463
 464   action(dd_issuePUTS, "\ds", desc="Issue PUTS") {
 465     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 466     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 467       out_msg.Address := address;
 468       out_msg.Type := CoherenceRequestType:PUTS;
 469       out_msg.Requestor := machineID;
 470       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 471             l2_select_low_bit, l2_select_num_bits));
 472       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 473     }
 474   }
 475
 476   action(e_sendData, "e", desc="Send data from cache to requestor") {
 477     peek(requestNetwork_in, RequestMsg) {
 478       assert(is_valid(cache_entry));
 479       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 480         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 481           out_msg.Address := address;
 482           out_msg.Type := CoherenceResponseType:DATA;
 483           out_msg.Sender := machineID;
 484           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 485                 l2_select_low_bit, l2_select_num_bits));
 486           out_msg.DataBlk := cache_entry.DataBlk;
 487           // out_msg.Dirty := cache_entry.Dirty;
 488           out_msg.Dirty := false;
 489           out_msg.Acks := in_msg.Acks;
 490           out_msg.MessageSize := MessageSizeType:Response_Data;
 491         }
 492         DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Address);
 493       }
 494       else {
 495         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 496           out_msg.Address := address;
 497           out_msg.Type := CoherenceResponseType:DATA;
 498           out_msg.Sender := machineID;
 499           out_msg.Destination.add(in_msg.Requestor);
 500           out_msg.DataBlk := cache_entry.DataBlk;
 501           // out_msg.Dirty := cache_entry.Dirty;
 502           out_msg.Dirty := false;
 503           out_msg.Acks := in_msg.Acks;
 504           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 505         }
 506         DPRINTF(RubySlicc, "Sending data to L1\n");
 507       }
 508     }
 509   }
 510
 511   action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
 512     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 513       assert(is_valid(cache_entry));
 514       out_msg.Address := address;
 515       out_msg.Type := CoherenceResponseType:DATA;
 516       out_msg.Sender := machineID;
 517       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 518             l2_select_low_bit, l2_select_num_bits));
 519       out_msg.DataBlk := cache_entry.DataBlk;
 520       out_msg.Dirty := cache_entry.Dirty;
 521       out_msg.Acks := 0; // irrelevant
 522       out_msg.MessageSize := MessageSizeType:Response_Data;
 523     }
 524   }
 525
 526
 527   action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
 528     peek(requestNetwork_in, RequestMsg) {
 529       assert(is_valid(cache_entry));
 530       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 531         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 532           out_msg.Address := address;
 533           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 534           out_msg.Sender := machineID;
 535           out_msg.SenderMachine := MachineType:L1Cache;
 536           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 537                 l2_select_low_bit, l2_select_num_bits));
 538           out_msg.DataBlk := cache_entry.DataBlk;
 539           out_msg.Dirty := cache_entry.Dirty;
 540           out_msg.Acks := in_msg.Acks;
 541           out_msg.MessageSize := MessageSizeType:Response_Data;
 542         }
 543         DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
 544       }
 545       else {
 546         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 547           out_msg.Address := address;
 548           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 549           out_msg.Sender := machineID;
 550           out_msg.SenderMachine := MachineType:L1Cache;
 551           out_msg.Destination.add(in_msg.Requestor);
 552           out_msg.DataBlk := cache_entry.DataBlk;
 553           out_msg.Dirty := cache_entry.Dirty;
 554           out_msg.Acks := in_msg.Acks;
 555           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 556         }
 557         DPRINTF(RubySlicc, "Sending exclusive data to L1\n");
 558       }
 559     }
 560   }
 561
 562   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 563     peek(requestNetwork_in, RequestMsg) {
 564       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 565         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 566           out_msg.Address := address;
 567           out_msg.Type := CoherenceResponseType:ACK;
 568           out_msg.Sender := machineID;
 569           out_msg.SenderMachine := MachineType:L1Cache;
 570           out_msg.Destination.add(in_msg.Requestor);
 571           out_msg.Acks := 0 - 1; // -1
 572           out_msg.MessageSize := MessageSizeType:Response_Control;
 573         }
 574       }
 575       else {
 576         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 577           out_msg.Address := address;
 578           out_msg.Type := CoherenceResponseType:ACK;
 579           out_msg.Sender := machineID;
 580           out_msg.SenderMachine := MachineType:L1Cache;
 581           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 582                 l2_select_low_bit, l2_select_num_bits));
 583           out_msg.Acks := 0 - 1; // -1
 584           out_msg.MessageSize := MessageSizeType:Response_Control;
 585         }
 586       }
 587     }
 588   }
 589
 590   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 591     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 592       out_msg.Address := address;
 593       out_msg.Type := CoherenceResponseType:UNBLOCK;
 594       out_msg.Sender := machineID;
 595       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 596             l2_select_low_bit, l2_select_num_bits));
 597       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 598     }
 599   }
 600
 601   action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
 602     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 603       out_msg.Address := address;
 604       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 605       out_msg.Sender := machineID;
 606       out_msg.SenderMachine := MachineType:L1Cache;
 607       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 608             l2_select_low_bit, l2_select_num_bits));
 609       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 610     }
 611   }
 612
 613   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 614     assert(is_valid(cache_entry));
 615     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 616     sequencer.readCallback(address, cache_entry.DataBlk);
 617   }
 618
 619   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 620     assert(is_valid(cache_entry));
 621     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 622     sequencer.writeCallback(address, cache_entry.DataBlk);
 623     cache_entry.Dirty := true;
 624   }
 625
 626   action(i_allocateTBE, "i", desc="Allocate TBE") {
 627     check_allocate(TBEs);
 628     TBEs.allocate(address);
 629     set_tbe(TBEs[address]);
 630     assert(is_valid(cache_entry));
 631     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 632     tbe.Dirty := cache_entry.Dirty;
 633   }
 634
 635   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 636     triggerQueue_in.dequeue();
 637   }
 638
 639   action(jj_unsetUseTimer, "\jj", desc="Unset use timer.") {
 640     useTimerTable.unset(address);
 641   }
 642
 643   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 644     mandatoryQueue_in.dequeue();
 645   }
 646
 647   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 648     requestNetwork_in.dequeue();
 649   }
 650
 651   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 652     peek(responseToL1Cache_in, ResponseMsg) {
 653       assert(is_valid(tbe));
 654       DPRINTF(RubySlicc, "L1 decrementNumberOfMessages: %d\n", in_msg.Acks);
 655       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 656     }
 657   }
 658
 659   action(mm_decrementNumberOfMessages, "\m", desc="Decrement the number of messages for which we're waiting") {
 660     peek(requestNetwork_in, RequestMsg) {
 661       assert(is_valid(tbe));
 662       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 663     }
 664   }
 665
 666   action(n_popResponseQueue, "n", desc="Pop response queue") {
 667     responseToL1Cache_in.dequeue();
 668   }
 669
 670   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 671     assert(is_valid(tbe));
 672     if (tbe.NumPendingMsgs == 0) {
 673       enqueue(triggerQueue_out, TriggerMsg) {
 674         out_msg.Address := address;
 675         out_msg.Type := TriggerType:ALL_ACKS;
 676       }
 677     }
 678   }
 679
 680   action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") {
 681     useTimerTable.set(address, 50);
 682   }
 683
 684
 685   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 686     peek(requestNetwork_in, RequestMsg) {
 687       assert(is_valid(tbe));
 688       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 689         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 690           out_msg.Address := address;
 691           out_msg.Type := CoherenceResponseType:DATA;
 692           out_msg.Sender := machineID;
 693           out_msg.Destination.add(in_msg.Requestor);
 694           out_msg.DataBlk := tbe.DataBlk;
 695           // out_msg.Dirty := tbe.Dirty;
 696           out_msg.Dirty := false;
 697           out_msg.Acks := in_msg.Acks;
 698           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 699         }
 700       }
 701       else {
 702         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 703           out_msg.Address := address;
 704           out_msg.Type := CoherenceResponseType:DATA;
 705           out_msg.Sender := machineID;
 706           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 707                 l2_select_low_bit, l2_select_num_bits));
 708           out_msg.DataBlk := tbe.DataBlk;
 709           // out_msg.Dirty := tbe.Dirty;
 710           out_msg.Dirty := false;
 711           out_msg.Acks := in_msg.Acks;
 712           out_msg.MessageSize := MessageSizeType:Response_Data;
 713         }
 714       }
 715     }
 716   }
 717
 718   action(q_sendExclusiveDataFromTBEToCache, "qq", desc="Send data from TBE to cache") {
 719     peek(requestNetwork_in, RequestMsg) {
 720       assert(is_valid(tbe));
 721       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 722         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 723           out_msg.Address := address;
 724           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 725           out_msg.Sender := machineID;
 726           out_msg.Destination.add(in_msg.Requestor);
 727           out_msg.DataBlk := tbe.DataBlk;
 728           out_msg.Dirty := tbe.Dirty;
 729           out_msg.Acks := in_msg.Acks;
 730           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 731         }
 732       }
 733       else {
 734         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 735           out_msg.Address := address;
 736           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 737           out_msg.Sender := machineID;
 738           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 739                 l2_select_low_bit, l2_select_num_bits));
 740           out_msg.DataBlk := tbe.DataBlk;
 741           out_msg.Dirty := tbe.Dirty;
 742           out_msg.Acks := in_msg.Acks;
 743           out_msg.MessageSize := MessageSizeType:Response_Data;
 744         }
 745       }
 746     }
 747   }
 748
 749
 750   // L2 will usually request data for a writeback
 751   action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
 752     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 753       assert(is_valid(tbe));
 754       out_msg.Address := address;
 755       out_msg.Sender := machineID;
 756       out_msg.SenderMachine := MachineType:L1Cache;
 757       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 758             l2_select_low_bit, l2_select_num_bits));
 759       out_msg.Dirty := tbe.Dirty;
 760       if (tbe.Dirty) {
 761         out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
 762       } else {
 763         out_msg.Type := CoherenceResponseType:WRITEBACK_CLEAN_DATA;
 764       }
 765       out_msg.DataBlk := tbe.DataBlk;
 766       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 767     }
 768   }
 769
 770   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 771     TBEs.deallocate(address);
 772     unset_tbe();
 773   }
 774
 775   action(u_writeDataToCache, "u", desc="Write data to cache") {
 776     peek(responseToL1Cache_in, ResponseMsg) {
 777       assert(is_valid(cache_entry));
 778       cache_entry.DataBlk := in_msg.DataBlk;
 779       cache_entry.Dirty := in_msg.Dirty;
 780
 781       if (in_msg.Type == CoherenceResponseType:DATA) {
 782         //assert(in_msg.Dirty == false);
 783       }
 784     }
 785
 786   }
 787
 788   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 789     peek(responseToL1Cache_in, ResponseMsg) {
 790       assert(is_valid(cache_entry));
 791       assert(cache_entry.DataBlk == in_msg.DataBlk);
 792       cache_entry.DataBlk := in_msg.DataBlk;
 793       cache_entry.Dirty := in_msg.Dirty;
 794     }
 795   }
 796
 797   action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 798     if (L1DcacheMemory.isTagPresent(address)) {
 799       L1DcacheMemory.deallocate(address);
 800     } else {
 801       L1IcacheMemory.deallocate(address);
 802     }
 803     unset_cache_entry();
 804   }
 805
 806   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 807     if ((is_invalid(cache_entry))) {
 808       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
 809     }
 810   }
 811
 812   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 813     if ((is_invalid(cache_entry))) {
 814       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
 815     }
 816   }
 817
 818
 819
 820   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
 821     peek(mandatoryQueue_in, CacheMsg) {
 822       //      profile_miss(in_msg);
 823     }
 824   }
 825
 826   action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {
 827     requestNetwork_in.recycle();
 828   }
 829
 830   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
 831     mandatoryQueue_in.recycle();
 832   }
 833
 834   //*****************************************************
 835   // TRANSITIONS
 836   //*****************************************************
 837
 838   // Transitions for Load/Store/L2_Replacement from transient states
 839   transition({IM, SM, OM, IS, OI, SI, MI, II}, {Store, L1_Replacement}) {
 840     zz_recycleMandatoryQueue;
 841   }
 842
 843   transition({M_W, MM_W}, L1_Replacement) {
 844     zz_recycleMandatoryQueue;
 845   }
 846
 847   transition({M_W, MM_W}, {Fwd_GETS, Fwd_DMA, Fwd_GETX, Own_GETX, Inv}) {
 848     z_recycleRequestQueue;
 849   }
 850
 851   transition({IM, IS, OI, MI, SI, II}, {Load, Ifetch}) {
 852     zz_recycleMandatoryQueue;
 853   }
 854
 855   // Transitions from Idle
 856   transition(I, Load, IS) {
 857     ii_allocateL1DCacheBlock;
 858     i_allocateTBE;
 859     a_issueGETS;
 860     // uu_profileMiss;
 861     k_popMandatoryQueue;
 862   }
 863
 864   transition(I, Ifetch, IS) {
 865     jj_allocateL1ICacheBlock;
 866     i_allocateTBE;
 867     a_issueGETS;
 868     // uu_profileMiss;
 869     k_popMandatoryQueue;
 870   }
 871
 872   transition(I, Store, IM) {
 873     ii_allocateL1DCacheBlock;
 874     i_allocateTBE;
 875     b_issueGETX;
 876     // uu_profileMiss;
 877     k_popMandatoryQueue;
 878   }
 879
 880   transition(I, L1_Replacement) {
 881     kk_deallocateL1CacheBlock;
 882   }
 883
 884   transition(I, Inv) {
 885     f_sendAck;
 886     l_popForwardQueue;
 887   }
 888
 889   // Transitions from Shared
 890   transition({S, SM}, {Load, Ifetch}) {
 891     h_load_hit;
 892     k_popMandatoryQueue;
 893   }
 894
 895   transition(S, Store, SM) {
 896     i_allocateTBE;
 897     b_issueGETX;
 898     // uu_profileMiss;
 899     k_popMandatoryQueue;
 900   }
 901
 902   transition(S, L1_Replacement, SI) {
 903     i_allocateTBE;
 904     dd_issuePUTS;
 905     kk_deallocateL1CacheBlock;
 906   }
 907
 908   transition(S, Inv, I) {
 909     f_sendAck;
 910     l_popForwardQueue;
 911   }
 912
 913   transition(S, {Fwd_GETS, Fwd_DMA}) {
 914     e_sendData;
 915     l_popForwardQueue;
 916   }
 917
 918   // Transitions from Owned
 919   transition({O, OM}, {Load, Ifetch}) {
 920     h_load_hit;
 921     k_popMandatoryQueue;
 922   }
 923
 924   transition(O, Store, OM) {
 925     i_allocateTBE;
 926     b_issueGETX;
 927     // uu_profileMiss;
 928     k_popMandatoryQueue;
 929   }
 930
 931   transition(O, L1_Replacement, OI) {
 932     i_allocateTBE;
 933     dd_issuePUTO;
 934     kk_deallocateL1CacheBlock;
 935   }
 936
 937   transition(O, Fwd_GETX, I) {
 938     ee_sendDataExclusive;
 939     l_popForwardQueue;
 940   }
 941
 942   transition(O, {Fwd_GETS, Fwd_DMA}) {
 943     e_sendData;
 944     l_popForwardQueue;
 945   }
 946
 947   // Transitions from MM
 948   transition({MM, MM_W}, {Load, Ifetch}) {
 949     h_load_hit;
 950     k_popMandatoryQueue;
 951   }
 952
 953   transition({MM, MM_W}, Store) {
 954     hh_store_hit;
 955     k_popMandatoryQueue;
 956   }
 957
 958   transition(MM, L1_Replacement, MI) {
 959     i_allocateTBE;
 960     d_issuePUTX;
 961     kk_deallocateL1CacheBlock;
 962   }
 963
 964   transition(MM, Fwd_GETX, I) {
 965     ee_sendDataExclusive;
 966     l_popForwardQueue;
 967   }
 968
 969   transition(MM, Fwd_GETS, I) {
 970     ee_sendDataExclusive;
 971     l_popForwardQueue;
 972   }
 973
 974   transition(MM, Fwd_DMA, MM) {
 975     //ee_sendDataExclusive;
 976     e_sendData;
 977     l_popForwardQueue;
 978   }
 979
 980   // Transitions from M
 981   transition({M, M_W}, {Load, Ifetch}) {
 982     h_load_hit;
 983     k_popMandatoryQueue;
 984   }
 985
 986   transition(M, Store, MM) {
 987     hh_store_hit;
 988     k_popMandatoryQueue;
 989   }
 990
 991   transition(M_W, Store, MM_W) {
 992     hh_store_hit;
 993     k_popMandatoryQueue;
 994   }
 995
 996   transition(M, L1_Replacement, MI) {
 997     i_allocateTBE;
 998     d_issuePUTX;
 999     kk_deallocateL1CacheBlock;
1000   }
1001
1002   transition(M, Fwd_GETX, I) {
1003     // e_sendData;
1004     ee_sendDataExclusive;
1005     l_popForwardQueue;
1006   }
1007
1008   transition(M, Fwd_GETS, O) {
1009     e_sendData;
1010     l_popForwardQueue;
1011   }
1012
1013   transition(M, Fwd_DMA, M) {
1014     e_sendData;
1015     l_popForwardQueue;
1016   }
1017
1018   // Transitions from IM
1019
1020   transition(IM, Inv) {
1021     f_sendAck;
1022     l_popForwardQueue;
1023   }
1024
1025   transition(IM, Ack) {
1026     m_decrementNumberOfMessages;
1027     o_checkForCompletion;
1028     n_popResponseQueue;
1029   }
1030
1031   transition(IM, {Exclusive_Data, Data}, OM) {
1032     u_writeDataToCache;
1033     m_decrementNumberOfMessages;
1034     o_checkForCompletion;
1035     n_popResponseQueue;
1036   }
1037
1038   // Transitions from SM
1039   transition(SM, Inv, IM) {
1040     f_sendAck;
1041     l_popForwardQueue;
1042   }
1043
1044   transition(SM, Ack) {
1045     m_decrementNumberOfMessages;
1046     o_checkForCompletion;
1047     n_popResponseQueue;
1048   }
1049
1050   transition(SM, {Data, Exclusive_Data}, OM) {
1051     // v_writeDataToCacheVerify;
1052     m_decrementNumberOfMessages;
1053     o_checkForCompletion;
1054     n_popResponseQueue;
1055   }
1056
1057   transition(SM, {Fwd_DMA, Fwd_GETS}) {
1058     e_sendData;
1059     l_popForwardQueue;
1060   }
1061
1062   // Transitions from OM
1063   transition(OM, Own_GETX) {
1064     mm_decrementNumberOfMessages;
1065     o_checkForCompletion;
1066     l_popForwardQueue;
1067   }
1068
1069
1070   // transition(OM, Fwd_GETX, OMF) {
1071   transition(OM, Fwd_GETX, IM) {
1072     ee_sendDataExclusive;
1073     l_popForwardQueue;
1074   }
1075
1076   transition(OM, {Fwd_DMA, Fwd_GETS}, OM) {
1077     e_sendData;
1078     l_popForwardQueue;
1079   }
1080
1081   //transition({OM, OMF}, Ack) {
1082   transition(OM, Ack) {
1083     m_decrementNumberOfMessages;
1084     o_checkForCompletion;
1085     n_popResponseQueue;
1086   }
1087
1088   transition(OM, All_acks, MM_W) {
1089     hh_store_hit;
1090     gg_sendUnblockExclusive;
1091     s_deallocateTBE;
1092     o_scheduleUseTimeout;
1093     j_popTriggerQueue;
1094   }
1095
1096   transition(MM_W, Use_Timeout, MM) {
1097     jj_unsetUseTimer;
1098   }
1099
1100   // Transitions from IS
1101
1102   transition(IS, Inv) {
1103     f_sendAck;
1104     l_popForwardQueue;
1105   }
1106
1107   transition(IS, Data, S) {
1108     u_writeDataToCache;
1109     m_decrementNumberOfMessages;
1110     h_load_hit;
1111     g_sendUnblock;
1112     s_deallocateTBE;
1113     n_popResponseQueue;
1114   }
1115
1116   transition(IS, Exclusive_Data, M_W) {
1117     u_writeDataToCache;
1118     m_decrementNumberOfMessages;
1119     h_load_hit;
1120     gg_sendUnblockExclusive;
1121     o_scheduleUseTimeout;
1122     s_deallocateTBE;
1123     n_popResponseQueue;
1124   }
1125
1126   transition(M_W, Use_Timeout, M) {
1127     jj_unsetUseTimer;
1128   }
1129
1130   // Transitions from OI/MI
1131
1132   transition(MI, Fwd_GETS, OI) {
1133     q_sendDataFromTBEToCache;
1134     l_popForwardQueue;
1135   }
1136
1137   transition(MI, Fwd_DMA, MI) {
1138     q_sendDataFromTBEToCache;
1139     l_popForwardQueue;
1140   }
1141
1142   transition(MI, Fwd_GETX, II) {
1143     q_sendExclusiveDataFromTBEToCache;
1144     l_popForwardQueue;
1145   }
1146
1147   transition({SI, OI}, {Fwd_DMA, Fwd_GETS}) {
1148     q_sendDataFromTBEToCache;
1149     l_popForwardQueue;
1150   }
1151
1152   transition(OI, Fwd_GETX, II) {
1153     q_sendExclusiveDataFromTBEToCache;
1154     l_popForwardQueue;
1155   }
1156
1157   transition({SI, OI, MI}, Writeback_Ack_Data, I) {
1158     qq_sendWBDataFromTBEToL2;  // always send data
1159     s_deallocateTBE;
1160     l_popForwardQueue;
1161   }
1162
1163   transition({SI, OI, MI}, Writeback_Ack, I) {
1164     g_sendUnblock;
1165     s_deallocateTBE;
1166     l_popForwardQueue;
1167   }
1168
1169   transition({MI, OI}, Writeback_Nack, OI) {
1170     // FIXME: This might cause deadlock by re-using the writeback
1171     // channel, we should handle this case differently.
1172     dd_issuePUTO;
1173     l_popForwardQueue;
1174   }
1175
1176   // Transitions from II
1177   transition(II, {Writeback_Ack, Writeback_Ack_Data}, I) {
1178     g_sendUnblock;
1179     s_deallocateTBE;
1180     l_popForwardQueue;
1181   }
1182
1183   // transition({II, SI}, Writeback_Nack, I) {
1184   transition(II, Writeback_Nack, I) {
1185     s_deallocateTBE;
1186     l_popForwardQueue;
1187   }
1188
1189   transition(SI, Writeback_Nack) {
1190     dd_issuePUTS;
1191     l_popForwardQueue;
1192   }
1193
1194   transition(II, Inv) {
1195     f_sendAck;
1196     l_popForwardQueue;
1197   }
1198
1199   transition(SI, Inv, II) {
1200     f_sendAck;
1201     l_popForwardQueue;
1202   }
1203 }