src/mem/protocol/MOESI_CMP_directory-L1cache.sm

   1
   2 /*
   3  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * $Id$
  32  *
  33  */
  34
  35 machine(L1Cache, "Directory protocol")
  36  : Sequencer * sequencer,
  37    CacheMemory * L1IcacheMemory,
  38    CacheMemory * L1DcacheMemory,
  39    int l2_select_num_bits,
  40    int request_latency = 2
  41 {
  42
  43   // NODE L1 CACHE
  44   // From this node's L1 cache TO the network
  45   // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
  46   MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
  47   // a local L1 -> this L2 bank
  48   MessageBuffer responseFromL1Cache, network="To", virtual_network="2", ordered="false";
  49 //  MessageBuffer writebackFromL1Cache, network="To", virtual_network="3", ordered="false";
  50
  51
  52   // To this node's L1 cache FROM the network
  53   // a L2 bank -> this L1
  54   MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
  55   // a L2 bank -> this L1
  56   MessageBuffer responseToL1Cache, network="From", virtual_network="2", ordered="false";
  57
  58
  59
  60   // STATES
  61   enumeration(State, desc="Cache states", default="L1Cache_State_I") {
  62     // Base states
  63     I, desc="Idle";
  64     S, desc="Shared";
  65     O, desc="Owned";
  66     M, desc="Modified (dirty)";
  67     M_W, desc="Modified (dirty)";
  68     MM, desc="Modified (dirty and locally modified)";
  69     MM_W, desc="Modified (dirty and locally modified)";
  70
  71     // Transient States
  72     IM, "IM", desc="Issued GetX";
  73     SM, "SM", desc="Issued GetX, we still have an old copy of the line";
  74     OM, "SM", desc="Issued GetX, received data";
  75     IS, "IS", desc="Issued GetS";
  76     SI, "OI", desc="Issued PutS, waiting for ack";
  77     OI, "OI", desc="Issued PutO, waiting for ack";
  78     MI, "MI", desc="Issued PutX, waiting for ack";
  79     II, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
  80   }
  81
  82   // EVENTS
  83   enumeration(Event, desc="Cache events") {
  84     Load,            desc="Load request from the processor";
  85     Ifetch,          desc="I-fetch request from the processor";
  86     Store,           desc="Store request from the processor";
  87     L1_Replacement,  desc="Replacement";
  88
  89     // Requests
  90     Own_GETX,      desc="We observe our own GetX forwarded back to us";
  91     Fwd_GETX,      desc="A GetX from another processor";
  92     Fwd_GETS,      desc="A GetS from another processor";
  93     Fwd_DMA,      desc="A GetS from another processor";
  94     Inv,           desc="Invalidations from the directory";
  95
  96     // Responses
  97     Ack,             desc="Received an ack message";
  98     Data,            desc="Received a data message, responder has a shared copy";
  99     Exclusive_Data,  desc="Received a data message";
 100
 101     Writeback_Ack,   desc="Writeback O.K. from directory";
 102     Writeback_Ack_Data,   desc="Writeback O.K. from directory";
 103     Writeback_Nack,  desc="Writeback not O.K. from directory";
 104
 105     // Triggers
 106     All_acks,                  desc="Received all required data and message acks";
 107
 108     // Timeouts
 109     Use_Timeout, desc="lockout period ended";
 110   }
 111
 112   // TYPES
 113
 114   // CacheEntry
 115   structure(Entry, desc="...", interface="AbstractCacheEntry") {
 116     State CacheState,        desc="cache state";
 117     bool Dirty,              desc="Is the data dirty (different than memory)?";
 118     DataBlock DataBlk,       desc="data for the block";
 119   }
 120
 121   // TBE fields
 122   structure(TBE, desc="...") {
 123     Address Address,         desc="Physical address for this TBE";
 124     State TBEState,          desc="Transient state";
 125     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
 126     bool Dirty,              desc="Is the data dirty (different than memory)?";
 127     int NumPendingMsgs, default="0",     desc="Number of acks/data messages that this processor is waiting for";
 128   }
 129
 130   external_type(TBETable) {
 131     TBE lookup(Address);
 132     void allocate(Address);
 133     void deallocate(Address);
 134     bool isPresent(Address);
 135   }
 136
 137   void set_cache_entry(AbstractCacheEntry b);
 138   void unset_cache_entry();
 139   void set_tbe(TBE b);
 140   void unset_tbe();
 141
 142   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 143
 144   TBETable TBEs, template_hack="<L1Cache_TBE>";
 145   TimerTable useTimerTable;
 146   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 147
 148   Entry getCacheEntry(Address addr), return_by_pointer="yes" {
 149     Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 150     if(is_valid(L1Dcache_entry)) {
 151       return L1Dcache_entry;
 152     }
 153
 154     Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 155     return L1Icache_entry;
 156   }
 157
 158   Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
 159     return static_cast(Entry, "pointer", L1DcacheMemory.lookup(addr));
 160   }
 161
 162   Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
 163     return static_cast(Entry, "pointer", L1IcacheMemory.lookup(addr));
 164   }
 165
 166   State getState(TBE tbe, Entry cache_entry, Address addr) {
 167     if(is_valid(tbe)) {
 168       return tbe.TBEState;
 169     } else if (is_valid(cache_entry)) {
 170       return cache_entry.CacheState;
 171     }
 172     return State:I;
 173   }
 174
 175   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 176     assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
 177
 178     if (is_valid(tbe)) {
 179       tbe.TBEState := state;
 180     }
 181
 182     if (is_valid(cache_entry)) {
 183       if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
 184          ((cache_entry.CacheState != State:MM) && (state == State:MM)) ||
 185          ((cache_entry.CacheState != State:S) && (state == State:S)) ||
 186          ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
 187
 188         cache_entry.CacheState := state;
 189         sequencer.checkCoherence(addr);
 190       }
 191       else {
 192         cache_entry.CacheState := state;
 193       }
 194
 195       // Set permission
 196       if (state == State:MM || state == State:MM_W) {
 197         cache_entry.changePermission(AccessPermission:Read_Write);
 198       } else if ((state == State:S) ||
 199                  (state == State:O) ||
 200                  (state == State:M) ||
 201                  (state == State:M_W) ||
 202                  (state == State:SM) ||
 203                  (state == State:OM)) {
 204         cache_entry.changePermission(AccessPermission:Read_Only);
 205       } else {
 206         cache_entry.changePermission(AccessPermission:Invalid);
 207       }
 208     }
 209   }
 210
 211   Event mandatory_request_type_to_event(CacheRequestType type) {
 212     if (type == CacheRequestType:LD) {
 213       return Event:Load;
 214     } else if (type == CacheRequestType:IFETCH) {
 215       return Event:Ifetch;
 216     } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
 217       return Event:Store;
 218     } else {
 219       error("Invalid CacheRequestType");
 220     }
 221   }
 222
 223   MessageBuffer triggerQueue, ordered="true";
 224
 225   // ** OUT_PORTS **
 226
 227   out_port(requestNetwork_out, RequestMsg, requestFromL1Cache);
 228   out_port(responseNetwork_out, ResponseMsg, responseFromL1Cache);
 229   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
 230
 231   // ** IN_PORTS **
 232
 233   // Use Timer
 234   in_port(useTimerTable_in, Address, useTimerTable) {
 235     if (useTimerTable_in.isReady()) {
 236         trigger(Event:Use_Timeout, useTimerTable.readyAddress(),
 237                 getCacheEntry(useTimerTable.readyAddress()),
 238                 TBEs[useTimerTable.readyAddress()]);
 239     }
 240   }
 241
 242   // Trigger Queue
 243   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 244     if (triggerQueue_in.isReady()) {
 245       peek(triggerQueue_in, TriggerMsg) {
 246         if (in_msg.Type == TriggerType:ALL_ACKS) {
 247           trigger(Event:All_acks, in_msg.Address,
 248                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 249         } else {
 250           error("Unexpected message");
 251         }
 252       }
 253     }
 254   }
 255
 256   // Nothing from the request network
 257
 258   // Request Network
 259   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
 260     if (requestNetwork_in.isReady()) {
 261       peek(requestNetwork_in, RequestMsg, block_on="Address") {
 262         assert(in_msg.Destination.isElement(machineID));
 263         DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 264
 265         if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
 266           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
 267             trigger(Event:Own_GETX, in_msg.Address,
 268                     getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 269           } else {
 270             trigger(Event:Fwd_GETX, in_msg.Address,
 271                     getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 272           }
 273         } else if (in_msg.Type == CoherenceRequestType:GETS) {
 274           trigger(Event:Fwd_GETS, in_msg.Address,
 275                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 276         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
 277           trigger(Event:Fwd_DMA, in_msg.Address,
 278                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 279         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
 280           trigger(Event:Writeback_Ack, in_msg.Address,
 281                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 282         } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) {
 283           trigger(Event:Writeback_Ack_Data, in_msg.Address,
 284                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 285         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
 286           trigger(Event:Writeback_Nack, in_msg.Address,
 287                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 288         } else if (in_msg.Type == CoherenceRequestType:INV) {
 289           trigger(Event:Inv, in_msg.Address,
 290                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 291         } else {
 292           error("Unexpected message");
 293         }
 294       }
 295     }
 296   }
 297
 298   // Response Network
 299   in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
 300     if (responseToL1Cache_in.isReady()) {
 301       peek(responseToL1Cache_in, ResponseMsg, block_on="Address") {
 302         if (in_msg.Type == CoherenceResponseType:ACK) {
 303           trigger(Event:Ack, in_msg.Address,
 304                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 305         } else if (in_msg.Type == CoherenceResponseType:DATA) {
 306           trigger(Event:Data, in_msg.Address,
 307                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 308         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
 309           trigger(Event:Exclusive_Data, in_msg.Address,
 310                   getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
 311         } else {
 312           error("Unexpected message");
 313         }
 314       }
 315     }
 316   }
 317
 318   // Nothing from the unblock network
 319   // Mandatory Queue betweens Node's CPU and it's L1 caches
 320   in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
 321     if (mandatoryQueue_in.isReady()) {
 322       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 323
 324         // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
 325
 326         if (in_msg.Type == CacheRequestType:IFETCH) {
 327           // ** INSTRUCTION ACCESS ***
 328
 329           Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 330           if (is_valid(L1Icache_entry)) {
 331             // The tag matches for the L1, so the L1 asks the L2 for it.
 332             trigger(mandatory_request_type_to_event(in_msg.Type),
 333                     in_msg.LineAddress, L1Icache_entry,
 334                     TBEs[in_msg.LineAddress]);
 335           } else {
 336
 337             Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 338             // Check to see if it is in the OTHER L1
 339             if (is_valid(L1Dcache_entry)) {
 340               // The block is in the wrong L1, put the request on the queue to the shared L2
 341               trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry,
 342                       TBEs[in_msg.LineAddress]);
 343             }
 344             if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
 345               // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
 346               trigger(mandatory_request_type_to_event(in_msg.Type),
 347                       in_msg.LineAddress, L1Icache_entry,
 348                       TBEs[in_msg.LineAddress]);
 349             } else {
 350               // No room in the L1, so we need to make room in the L1
 351               trigger(Event:L1_Replacement,
 352                       L1IcacheMemory.cacheProbe(in_msg.LineAddress),
 353                       getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
 354                       TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
 355             }
 356           }
 357         } else {
 358           // *** DATA ACCESS ***
 359
 360           Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
 361           if (is_valid(L1Dcache_entry)) {
 362             // The tag matches for the L1, so the L1 ask the L2 for it
 363             trigger(mandatory_request_type_to_event(in_msg.Type),
 364                     in_msg.LineAddress, L1Dcache_entry,
 365                     TBEs[in_msg.LineAddress]);
 366           } else {
 367
 368             Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
 369             // Check to see if it is in the OTHER L1
 370             if (is_valid(L1Icache_entry)) {
 371               // The block is in the wrong L1, put the request on the queue to the shared L2
 372               trigger(Event:L1_Replacement, in_msg.LineAddress,
 373                       L1Icache_entry, TBEs[in_msg.LineAddress]);
 374             }
 375             if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
 376               // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
 377               trigger(mandatory_request_type_to_event(in_msg.Type),
 378                       in_msg.LineAddress, L1Dcache_entry,
 379                       TBEs[in_msg.LineAddress]);
 380             } else {
 381               // No room in the L1, so we need to make room in the L1
 382               trigger(Event:L1_Replacement,
 383                       L1DcacheMemory.cacheProbe(in_msg.LineAddress),
 384                       getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
 385                       TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
 386             }
 387           }
 388         }
 389       }
 390     }
 391   }
 392
 393
 394   // ACTIONS
 395
 396   action(a_issueGETS, "a", desc="Issue GETS") {
 397     peek(mandatoryQueue_in, CacheMsg) {
 398       enqueue(requestNetwork_out, RequestMsg, latency= request_latency) {
 399         out_msg.Address := address;
 400         out_msg.Type := CoherenceRequestType:GETS;
 401         out_msg.Requestor := machineID;
 402         out_msg.RequestorMachine := MachineType:L1Cache;
 403         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 404               l2_select_low_bit, l2_select_num_bits));
 405         out_msg.MessageSize := MessageSizeType:Request_Control;
 406         out_msg.AccessMode := in_msg.AccessMode;
 407         out_msg.Prefetch := in_msg.Prefetch;
 408       }
 409     }
 410   }
 411
 412   action(b_issueGETX, "b", desc="Issue GETX") {
 413     peek(mandatoryQueue_in, CacheMsg) {
 414       enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 415         out_msg.Address := address;
 416         out_msg.Type := CoherenceRequestType:GETX;
 417         out_msg.Requestor := machineID;
 418         out_msg.RequestorMachine := MachineType:L1Cache;
 419         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 420               l2_select_low_bit, l2_select_num_bits));
 421         out_msg.MessageSize := MessageSizeType:Request_Control;
 422         out_msg.AccessMode := in_msg.AccessMode;
 423         out_msg.Prefetch := in_msg.Prefetch;
 424       }
 425     }
 426   }
 427
 428   action(d_issuePUTX, "d", desc="Issue PUTX") {
 429     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 430     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 431       out_msg.Address := address;
 432       out_msg.Type := CoherenceRequestType:PUTX;
 433       out_msg.Requestor := machineID;
 434       out_msg.RequestorMachine := MachineType:L1Cache;
 435       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 436             l2_select_low_bit, l2_select_num_bits));
 437       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 438     }
 439   }
 440
 441   action(dd_issuePUTO, "\d", desc="Issue PUTO") {
 442     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 443     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 444       out_msg.Address := address;
 445       out_msg.Type := CoherenceRequestType:PUTO;
 446       out_msg.Requestor := machineID;
 447       out_msg.RequestorMachine := MachineType:L1Cache;
 448       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 449             l2_select_low_bit, l2_select_num_bits));
 450       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 451     }
 452   }
 453
 454   action(dd_issuePUTS, "\ds", desc="Issue PUTS") {
 455     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
 456     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
 457       out_msg.Address := address;
 458       out_msg.Type := CoherenceRequestType:PUTS;
 459       out_msg.Requestor := machineID;
 460       out_msg.RequestorMachine := MachineType:L1Cache;
 461       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 462             l2_select_low_bit, l2_select_num_bits));
 463       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 464     }
 465   }
 466
 467   action(e_sendData, "e", desc="Send data from cache to requestor") {
 468     peek(requestNetwork_in, RequestMsg) {
 469       assert(is_valid(cache_entry));
 470       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 471         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 472           out_msg.Address := address;
 473           out_msg.Type := CoherenceResponseType:DATA;
 474           out_msg.Sender := machineID;
 475           out_msg.SenderMachine := MachineType:L1Cache;
 476           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 477                 l2_select_low_bit, l2_select_num_bits));
 478           out_msg.DataBlk := cache_entry.DataBlk;
 479           // out_msg.Dirty := cache_entry.Dirty;
 480           out_msg.Dirty := false;
 481           out_msg.Acks := in_msg.Acks;
 482           out_msg.MessageSize := MessageSizeType:Response_Data;
 483         }
 484         DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Address);
 485       }
 486       else {
 487         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 488           out_msg.Address := address;
 489           out_msg.Type := CoherenceResponseType:DATA;
 490           out_msg.Sender := machineID;
 491           out_msg.SenderMachine := MachineType:L1Cache;
 492           out_msg.Destination.add(in_msg.Requestor);
 493           out_msg.DataBlk := cache_entry.DataBlk;
 494           // out_msg.Dirty := cache_entry.Dirty;
 495           out_msg.Dirty := false;
 496           out_msg.Acks := in_msg.Acks;
 497           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 498         }
 499         DPRINTF(RubySlicc, "Sending data to L1\n");
 500       }
 501     }
 502   }
 503
 504   action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
 505     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 506       assert(is_valid(cache_entry));
 507       out_msg.Address := address;
 508       out_msg.Type := CoherenceResponseType:DATA;
 509       out_msg.Sender := machineID;
 510       out_msg.SenderMachine := MachineType:L1Cache;
 511       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 512             l2_select_low_bit, l2_select_num_bits));
 513       out_msg.DataBlk := cache_entry.DataBlk;
 514       out_msg.Dirty := cache_entry.Dirty;
 515       out_msg.Acks := 0; // irrelevant
 516       out_msg.MessageSize := MessageSizeType:Response_Data;
 517     }
 518   }
 519
 520
 521   action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
 522     peek(requestNetwork_in, RequestMsg) {
 523       assert(is_valid(cache_entry));
 524       if (in_msg.RequestorMachine == MachineType:L2Cache) {
 525         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 526           out_msg.Address := address;
 527           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 528           out_msg.Sender := machineID;
 529           out_msg.SenderMachine := MachineType:L1Cache;
 530           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 531                 l2_select_low_bit, l2_select_num_bits));
 532           out_msg.DataBlk := cache_entry.DataBlk;
 533           out_msg.Dirty := cache_entry.Dirty;
 534           out_msg.Acks := in_msg.Acks;
 535           out_msg.MessageSize := MessageSizeType:Response_Data;
 536         }
 537         DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
 538       }
 539       else {
 540         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 541           out_msg.Address := address;
 542           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 543           out_msg.Sender := machineID;
 544           out_msg.SenderMachine := MachineType:L1Cache;
 545           out_msg.Destination.add(in_msg.Requestor);
 546           out_msg.DataBlk := cache_entry.DataBlk;
 547           out_msg.Dirty := cache_entry.Dirty;
 548           out_msg.Acks := in_msg.Acks;
 549           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 550         }
 551         DPRINTF(RubySlicc, "Sending exclusive data to L1\n");
 552       }
 553     }
 554   }
 555
 556   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
 557     peek(requestNetwork_in, RequestMsg) {
 558       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 559         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 560           out_msg.Address := address;
 561           out_msg.Type := CoherenceResponseType:ACK;
 562           out_msg.Sender := machineID;
 563           out_msg.SenderMachine := MachineType:L1Cache;
 564           out_msg.Destination.add(in_msg.Requestor);
 565           out_msg.Acks := 0 - 1; // -1
 566           out_msg.MessageSize := MessageSizeType:Response_Control;
 567         }
 568       }
 569       else {
 570         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 571           out_msg.Address := address;
 572           out_msg.Type := CoherenceResponseType:ACK;
 573           out_msg.Sender := machineID;
 574           out_msg.SenderMachine := MachineType:L1Cache;
 575           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 576                 l2_select_low_bit, l2_select_num_bits));
 577           out_msg.Acks := 0 - 1; // -1
 578           out_msg.MessageSize := MessageSizeType:Response_Control;
 579         }
 580       }
 581     }
 582   }
 583
 584   action(g_sendUnblock, "g", desc="Send unblock to memory") {
 585     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 586       out_msg.Address := address;
 587       out_msg.Type := CoherenceResponseType:UNBLOCK;
 588       out_msg.Sender := machineID;
 589       out_msg.SenderMachine := MachineType:L1Cache;
 590       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 591             l2_select_low_bit, l2_select_num_bits));
 592       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 593     }
 594   }
 595
 596   action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
 597     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 598       out_msg.Address := address;
 599       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 600       out_msg.Sender := machineID;
 601       out_msg.SenderMachine := MachineType:L1Cache;
 602       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 603             l2_select_low_bit, l2_select_num_bits));
 604       out_msg.MessageSize := MessageSizeType:Unblock_Control;
 605     }
 606   }
 607
 608   action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
 609     assert(is_valid(cache_entry));
 610     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 611     sequencer.readCallback(address, cache_entry.DataBlk);
 612   }
 613
 614   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
 615     assert(is_valid(cache_entry));
 616     DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
 617     sequencer.writeCallback(address, cache_entry.DataBlk);
 618     cache_entry.Dirty := true;
 619   }
 620
 621   action(i_allocateTBE, "i", desc="Allocate TBE") {
 622     check_allocate(TBEs);
 623     TBEs.allocate(address);
 624     set_tbe(TBEs[address]);
 625     assert(is_valid(cache_entry));
 626     tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
 627     tbe.Dirty := cache_entry.Dirty;
 628   }
 629
 630   action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
 631     triggerQueue_in.dequeue();
 632   }
 633
 634   action(jj_unsetUseTimer, "\jj", desc="Unset use timer.") {
 635     useTimerTable.unset(address);
 636   }
 637
 638   action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
 639     mandatoryQueue_in.dequeue();
 640   }
 641
 642   action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
 643     requestNetwork_in.dequeue();
 644   }
 645
 646   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
 647     peek(responseToL1Cache_in, ResponseMsg) {
 648       assert(is_valid(tbe));
 649       DPRINTF(RubySlicc, "L1 decrementNumberOfMessages: %d\n", in_msg.Acks);
 650       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 651     }
 652   }
 653
 654   action(mm_decrementNumberOfMessages, "\m", desc="Decrement the number of messages for which we're waiting") {
 655     peek(requestNetwork_in, RequestMsg) {
 656       assert(is_valid(tbe));
 657       tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
 658     }
 659   }
 660
 661   action(n_popResponseQueue, "n", desc="Pop response queue") {
 662     responseToL1Cache_in.dequeue();
 663   }
 664
 665   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 666     assert(is_valid(tbe));
 667     if (tbe.NumPendingMsgs == 0) {
 668       enqueue(triggerQueue_out, TriggerMsg) {
 669         out_msg.Address := address;
 670         out_msg.Type := TriggerType:ALL_ACKS;
 671       }
 672     }
 673   }
 674
 675   action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") {
 676     useTimerTable.set(address, 50);
 677   }
 678
 679
 680   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 681     peek(requestNetwork_in, RequestMsg) {
 682       assert(is_valid(tbe));
 683       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 684         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 685           out_msg.Address := address;
 686           out_msg.Type := CoherenceResponseType:DATA;
 687           out_msg.Sender := machineID;
 688           out_msg.SenderMachine := MachineType:L1Cache;
 689           out_msg.Destination.add(in_msg.Requestor);
 690           out_msg.DataBlk := tbe.DataBlk;
 691           // out_msg.Dirty := tbe.Dirty;
 692           out_msg.Dirty := false;
 693           out_msg.Acks := in_msg.Acks;
 694           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 695         }
 696       }
 697       else {
 698         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 699           out_msg.Address := address;
 700           out_msg.Type := CoherenceResponseType:DATA;
 701           out_msg.Sender := machineID;
 702           out_msg.SenderMachine := MachineType:L1Cache;
 703           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 704                 l2_select_low_bit, l2_select_num_bits));
 705           out_msg.DataBlk := tbe.DataBlk;
 706           // out_msg.Dirty := tbe.Dirty;
 707           out_msg.Dirty := false;
 708           out_msg.Acks := in_msg.Acks;
 709           out_msg.MessageSize := MessageSizeType:Response_Data;
 710         }
 711       }
 712     }
 713   }
 714
 715   action(q_sendExclusiveDataFromTBEToCache, "qq", desc="Send data from TBE to cache") {
 716     peek(requestNetwork_in, RequestMsg) {
 717       assert(is_valid(tbe));
 718       if (in_msg.RequestorMachine == MachineType:L1Cache) {
 719         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 720           out_msg.Address := address;
 721           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 722           out_msg.Sender := machineID;
 723           out_msg.SenderMachine := MachineType:L1Cache;
 724           out_msg.Destination.add(in_msg.Requestor);
 725           out_msg.DataBlk := tbe.DataBlk;
 726           out_msg.Dirty := tbe.Dirty;
 727           out_msg.Acks := in_msg.Acks;
 728           out_msg.MessageSize := MessageSizeType:ResponseLocal_Data;
 729         }
 730       }
 731       else {
 732         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 733           out_msg.Address := address;
 734           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
 735           out_msg.Sender := machineID;
 736           out_msg.SenderMachine := MachineType:L1Cache;
 737           out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 738                 l2_select_low_bit, l2_select_num_bits));
 739           out_msg.DataBlk := tbe.DataBlk;
 740           out_msg.Dirty := tbe.Dirty;
 741           out_msg.Acks := in_msg.Acks;
 742           out_msg.MessageSize := MessageSizeType:Response_Data;
 743         }
 744       }
 745     }
 746   }
 747
 748
 749   // L2 will usually request data for a writeback
 750   action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
 751     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
 752       assert(is_valid(tbe));
 753       out_msg.Address := address;
 754       out_msg.Sender := machineID;
 755       out_msg.SenderMachine := MachineType:L1Cache;
 756       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
 757             l2_select_low_bit, l2_select_num_bits));
 758       out_msg.Dirty := tbe.Dirty;
 759       if (tbe.Dirty) {
 760         out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
 761       } else {
 762         out_msg.Type := CoherenceResponseType:WRITEBACK_CLEAN_DATA;
 763       }
 764       out_msg.DataBlk := tbe.DataBlk;
 765       out_msg.MessageSize := MessageSizeType:Writeback_Data;
 766     }
 767   }
 768
 769   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
 770     TBEs.deallocate(address);
 771     unset_tbe();
 772   }
 773
 774   action(u_writeDataToCache, "u", desc="Write data to cache") {
 775     peek(responseToL1Cache_in, ResponseMsg) {
 776       assert(is_valid(cache_entry));
 777       cache_entry.DataBlk := in_msg.DataBlk;
 778       cache_entry.Dirty := in_msg.Dirty;
 779
 780       if (in_msg.Type == CoherenceResponseType:DATA) {
 781         //assert(in_msg.Dirty == false);
 782       }
 783     }
 784
 785   }
 786
 787   action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
 788     peek(responseToL1Cache_in, ResponseMsg) {
 789       assert(is_valid(cache_entry));
 790       assert(cache_entry.DataBlk == in_msg.DataBlk);
 791       cache_entry.DataBlk := in_msg.DataBlk;
 792       cache_entry.Dirty := in_msg.Dirty;
 793     }
 794   }
 795
 796   action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block.  Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
 797     if (L1DcacheMemory.isTagPresent(address)) {
 798       L1DcacheMemory.deallocate(address);
 799     } else {
 800       L1IcacheMemory.deallocate(address);
 801     }
 802     unset_cache_entry();
 803   }
 804
 805   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
 806     if ((is_invalid(cache_entry))) {
 807       set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
 808     }
 809   }
 810
 811   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
 812     if ((is_invalid(cache_entry))) {
 813       set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
 814     }
 815   }
 816
 817
 818
 819   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
 820     peek(mandatoryQueue_in, CacheMsg) {
 821       //      profile_miss(in_msg);
 822     }
 823   }
 824
 825   action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {
 826     requestNetwork_in.recycle();
 827   }
 828
 829   action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
 830     mandatoryQueue_in.recycle();
 831   }
 832
 833   //*****************************************************
 834   // TRANSITIONS
 835   //*****************************************************
 836
 837   // Transitions for Load/Store/L2_Replacement from transient states
 838   transition({IM, SM, OM, IS, OI, SI, MI, II}, {Store, L1_Replacement}) {
 839     zz_recycleMandatoryQueue;
 840   }
 841
 842   transition({M_W, MM_W}, L1_Replacement) {
 843     zz_recycleMandatoryQueue;
 844   }
 845
 846   transition({M_W, MM_W}, {Fwd_GETS, Fwd_DMA, Fwd_GETX, Own_GETX, Inv}) {
 847     z_recycleRequestQueue;
 848   }
 849
 850   transition({IM, IS, OI, MI, SI, II}, {Load, Ifetch}) {
 851     zz_recycleMandatoryQueue;
 852   }
 853
 854   // Transitions from Idle
 855   transition(I, Load, IS) {
 856     ii_allocateL1DCacheBlock;
 857     i_allocateTBE;
 858     a_issueGETS;
 859     // uu_profileMiss;
 860     k_popMandatoryQueue;
 861   }
 862
 863   transition(I, Ifetch, IS) {
 864     jj_allocateL1ICacheBlock;
 865     i_allocateTBE;
 866     a_issueGETS;
 867     // uu_profileMiss;
 868     k_popMandatoryQueue;
 869   }
 870
 871   transition(I, Store, IM) {
 872     ii_allocateL1DCacheBlock;
 873     i_allocateTBE;
 874     b_issueGETX;
 875     // uu_profileMiss;
 876     k_popMandatoryQueue;
 877   }
 878
 879   transition(I, L1_Replacement) {
 880     kk_deallocateL1CacheBlock;
 881   }
 882
 883   transition(I, Inv) {
 884     f_sendAck;
 885     l_popForwardQueue;
 886   }
 887
 888   // Transitions from Shared
 889   transition({S, SM}, {Load, Ifetch}) {
 890     h_load_hit;
 891     k_popMandatoryQueue;
 892   }
 893
 894   transition(S, Store, SM) {
 895     i_allocateTBE;
 896     b_issueGETX;
 897     // uu_profileMiss;
 898     k_popMandatoryQueue;
 899   }
 900
 901   transition(S, L1_Replacement, SI) {
 902     i_allocateTBE;
 903     dd_issuePUTS;
 904     kk_deallocateL1CacheBlock;
 905   }
 906
 907   transition(S, Inv, I) {
 908     f_sendAck;
 909     l_popForwardQueue;
 910   }
 911
 912   transition(S, {Fwd_GETS, Fwd_DMA}) {
 913     e_sendData;
 914     l_popForwardQueue;
 915   }
 916
 917   // Transitions from Owned
 918   transition({O, OM}, {Load, Ifetch}) {
 919     h_load_hit;
 920     k_popMandatoryQueue;
 921   }
 922
 923   transition(O, Store, OM) {
 924     i_allocateTBE;
 925     b_issueGETX;
 926     // uu_profileMiss;
 927     k_popMandatoryQueue;
 928   }
 929
 930   transition(O, L1_Replacement, OI) {
 931     i_allocateTBE;
 932     dd_issuePUTO;
 933     kk_deallocateL1CacheBlock;
 934   }
 935
 936   transition(O, Fwd_GETX, I) {
 937     ee_sendDataExclusive;
 938     l_popForwardQueue;
 939   }
 940
 941   transition(O, {Fwd_GETS, Fwd_DMA}) {
 942     e_sendData;
 943     l_popForwardQueue;
 944   }
 945
 946   // Transitions from MM
 947   transition({MM, MM_W}, {Load, Ifetch}) {
 948     h_load_hit;
 949     k_popMandatoryQueue;
 950   }
 951
 952   transition({MM, MM_W}, Store) {
 953     hh_store_hit;
 954     k_popMandatoryQueue;
 955   }
 956
 957   transition(MM, L1_Replacement, MI) {
 958     i_allocateTBE;
 959     d_issuePUTX;
 960     kk_deallocateL1CacheBlock;
 961   }
 962
 963   transition(MM, Fwd_GETX, I) {
 964     ee_sendDataExclusive;
 965     l_popForwardQueue;
 966   }
 967
 968   transition(MM, Fwd_GETS, I) {
 969     ee_sendDataExclusive;
 970     l_popForwardQueue;
 971   }
 972
 973   transition(MM, Fwd_DMA, MM) {
 974     //ee_sendDataExclusive;
 975     e_sendData;
 976     l_popForwardQueue;
 977   }
 978
 979   // Transitions from M
 980   transition({M, M_W}, {Load, Ifetch}) {
 981     h_load_hit;
 982     k_popMandatoryQueue;
 983   }
 984
 985   transition(M, Store, MM) {
 986     hh_store_hit;
 987     k_popMandatoryQueue;
 988   }
 989
 990   transition(M_W, Store, MM_W) {
 991     hh_store_hit;
 992     k_popMandatoryQueue;
 993   }
 994
 995   transition(M, L1_Replacement, MI) {
 996     i_allocateTBE;
 997     d_issuePUTX;
 998     kk_deallocateL1CacheBlock;
 999   }
1000
1001   transition(M, Fwd_GETX, I) {
1002     // e_sendData;
1003     ee_sendDataExclusive;
1004     l_popForwardQueue;
1005   }
1006
1007   transition(M, Fwd_GETS, O) {
1008     e_sendData;
1009     l_popForwardQueue;
1010   }
1011
1012   transition(M, Fwd_DMA, M) {
1013     e_sendData;
1014     l_popForwardQueue;
1015   }
1016
1017   // Transitions from IM
1018
1019   transition(IM, Inv) {
1020     f_sendAck;
1021     l_popForwardQueue;
1022   }
1023
1024   transition(IM, Ack) {
1025     m_decrementNumberOfMessages;
1026     o_checkForCompletion;
1027     n_popResponseQueue;
1028   }
1029
1030   transition(IM, {Exclusive_Data, Data}, OM) {
1031     u_writeDataToCache;
1032     m_decrementNumberOfMessages;
1033     o_checkForCompletion;
1034     n_popResponseQueue;
1035   }
1036
1037   // Transitions from SM
1038   transition(SM, Inv, IM) {
1039     f_sendAck;
1040     l_popForwardQueue;
1041   }
1042
1043   transition(SM, Ack) {
1044     m_decrementNumberOfMessages;
1045     o_checkForCompletion;
1046     n_popResponseQueue;
1047   }
1048
1049   transition(SM, {Data, Exclusive_Data}, OM) {
1050     // v_writeDataToCacheVerify;
1051     m_decrementNumberOfMessages;
1052     o_checkForCompletion;
1053     n_popResponseQueue;
1054   }
1055
1056   transition(SM, {Fwd_DMA, Fwd_GETS}) {
1057     e_sendData;
1058     l_popForwardQueue;
1059   }
1060
1061   // Transitions from OM
1062   transition(OM, Own_GETX) {
1063     mm_decrementNumberOfMessages;
1064     o_checkForCompletion;
1065     l_popForwardQueue;
1066   }
1067
1068
1069   // transition(OM, Fwd_GETX, OMF) {
1070   transition(OM, Fwd_GETX, IM) {
1071     ee_sendDataExclusive;
1072     l_popForwardQueue;
1073   }
1074
1075   transition(OM, {Fwd_DMA, Fwd_GETS}, OM) {
1076     e_sendData;
1077     l_popForwardQueue;
1078   }
1079
1080   //transition({OM, OMF}, Ack) {
1081   transition(OM, Ack) {
1082     m_decrementNumberOfMessages;
1083     o_checkForCompletion;
1084     n_popResponseQueue;
1085   }
1086
1087   transition(OM, All_acks, MM_W) {
1088     hh_store_hit;
1089     gg_sendUnblockExclusive;
1090     s_deallocateTBE;
1091     o_scheduleUseTimeout;
1092     j_popTriggerQueue;
1093   }
1094
1095   transition(MM_W, Use_Timeout, MM) {
1096     jj_unsetUseTimer;
1097   }
1098
1099   // Transitions from IS
1100
1101   transition(IS, Inv) {
1102     f_sendAck;
1103     l_popForwardQueue;
1104   }
1105
1106   transition(IS, Data, S) {
1107     u_writeDataToCache;
1108     m_decrementNumberOfMessages;
1109     h_load_hit;
1110     g_sendUnblock;
1111     s_deallocateTBE;
1112     n_popResponseQueue;
1113   }
1114
1115   transition(IS, Exclusive_Data, M_W) {
1116     u_writeDataToCache;
1117     m_decrementNumberOfMessages;
1118     h_load_hit;
1119     gg_sendUnblockExclusive;
1120     o_scheduleUseTimeout;
1121     s_deallocateTBE;
1122     n_popResponseQueue;
1123   }
1124
1125   transition(M_W, Use_Timeout, M) {
1126     jj_unsetUseTimer;
1127   }
1128
1129   // Transitions from OI/MI
1130
1131   transition(MI, Fwd_GETS, OI) {
1132     q_sendDataFromTBEToCache;
1133     l_popForwardQueue;
1134   }
1135
1136   transition(MI, Fwd_DMA, MI) {
1137     q_sendDataFromTBEToCache;
1138     l_popForwardQueue;
1139   }
1140
1141   transition(MI, Fwd_GETX, II) {
1142     q_sendExclusiveDataFromTBEToCache;
1143     l_popForwardQueue;
1144   }
1145
1146   transition({SI, OI}, {Fwd_DMA, Fwd_GETS}) {
1147     q_sendDataFromTBEToCache;
1148     l_popForwardQueue;
1149   }
1150
1151   transition(OI, Fwd_GETX, II) {
1152     q_sendExclusiveDataFromTBEToCache;
1153     l_popForwardQueue;
1154   }
1155
1156   transition({SI, OI, MI}, Writeback_Ack_Data, I) {
1157     qq_sendWBDataFromTBEToL2;  // always send data
1158     s_deallocateTBE;
1159     l_popForwardQueue;
1160   }
1161
1162   transition({SI, OI, MI}, Writeback_Ack, I) {
1163     g_sendUnblock;
1164     s_deallocateTBE;
1165     l_popForwardQueue;
1166   }
1167
1168   transition({MI, OI}, Writeback_Nack, OI) {
1169     // FIXME: This might cause deadlock by re-using the writeback
1170     // channel, we should handle this case differently.
1171     dd_issuePUTO;
1172     l_popForwardQueue;
1173   }
1174
1175   // Transitions from II
1176   transition(II, {Writeback_Ack, Writeback_Ack_Data}, I) {
1177     g_sendUnblock;
1178     s_deallocateTBE;
1179     l_popForwardQueue;
1180   }
1181
1182   // transition({II, SI}, Writeback_Nack, I) {
1183   transition(II, Writeback_Nack, I) {
1184     s_deallocateTBE;
1185     l_popForwardQueue;
1186   }
1187
1188   transition(SI, Writeback_Nack) {
1189     dd_issuePUTS;
1190     l_popForwardQueue;
1191   }
1192
1193   transition(II, Inv) {
1194     f_sendAck;
1195     l_popForwardQueue;
1196   }
1197
1198   transition(SI, Inv, II) {
1199     f_sendAck;
1200     l_popForwardQueue;
1201   }
1202 }