src/mem/protocol/MOESI_CMP_directory-dma.sm

   1
   2 machine(DMA, "DMA Controller")
   3 : DMASequencer * dma_sequencer,
   4   int request_latency = 14,
   5   int response_latency = 14
   6 {
   7
   8   MessageBuffer goo1, network="From", virtual_network="0", ordered="false", vnet_type="goo";
   9   MessageBuffer goo2, network="From", virtual_network="1", ordered="false", vnet_type="goo";
  10   MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response";
  11
  12   MessageBuffer foo1, network="To", virtual_network="0", ordered="false", vnet_type="foo";
  13   MessageBuffer reqToDir, network="To", virtual_network="1", ordered="false", vnet_type="request";
  14   MessageBuffer respToDir, network="To", virtual_network="2", ordered="false", vnet_type="dmaresponse";
  15
  16   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  17     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  18     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  19     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  20   }
  21
  22   enumeration(Event, desc="DMA events") {
  23     ReadRequest,  desc="A new read request";
  24     WriteRequest, desc="A new write request";
  25     Data,         desc="Data from a DMA memory read";
  26     DMA_Ack,      desc="DMA write to memory completed";
  27     Inv_Ack,      desc="Invalidation Ack from a sharer";
  28     All_Acks,     desc="All acks received";
  29   }
  30
  31   structure(TBE, desc="...") {
  32     Address address, desc="Physical address";
  33     int NumAcks, default="0", desc="Number of Acks pending";
  34     DataBlock DataBlk, desc="Data";
  35   }
  36
  37   structure(DMASequencer, external = "yes") {
  38     void ackCallback();
  39     void dataCallback(DataBlock);
  40   }
  41
  42   structure(TBETable, external = "yes") {
  43     TBE lookup(Address);
  44     void allocate(Address);
  45     void deallocate(Address);
  46     bool isPresent(Address);
  47   }
  48
  49   MessageBuffer mandatoryQueue, ordered="false";
  50   MessageBuffer triggerQueue, ordered="true";
  51   TBETable TBEs, template_hack="<DMA_TBE>";
  52   State cur_state;
  53
  54   void set_tbe(TBE b);
  55   void unset_tbe();
  56
  57   State getState(TBE tbe, Address addr) {
  58     return cur_state;
  59   }
  60   void setState(TBE tbe, Address addr, State state) {
  61   cur_state := state;
  62   }
  63
  64   AccessPermission getAccessPermission(Address addr) {
  65     return AccessPermission:NotPresent;
  66   }
  67
  68   void setAccessPermission(Address addr, State state) {
  69   }
  70
  71   out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
  72   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
  73   out_port(foo1_out, ResponseMsg, foo1, desc="...");
  74   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
  75
  76   in_port(goo1_in, RequestMsg, goo1) {
  77     if (goo1_in.isReady()) {
  78       peek(goo1_in, RequestMsg) {
  79         assert(false);
  80       }
  81     }
  82   }
  83
  84   in_port(goo2_in, RequestMsg, goo2) {
  85     if (goo2_in.isReady()) {
  86       peek(goo2_in, RequestMsg) {
  87         assert(false);
  88       }
  89     }
  90   }
  91
  92   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  93     if (dmaRequestQueue_in.isReady()) {
  94       peek(dmaRequestQueue_in, SequencerMsg) {
  95         if (in_msg.Type == SequencerRequestType:LD ) {
  96           trigger(Event:ReadRequest, in_msg.LineAddress,
  97                   TBEs[in_msg.LineAddress]);
  98         } else if (in_msg.Type == SequencerRequestType:ST) {
  99           trigger(Event:WriteRequest, in_msg.LineAddress,
 100                   TBEs[in_msg.LineAddress]);
 101         } else {
 102           error("Invalid request type");
 103         }
 104       }
 105     }
 106   }
 107
 108   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 109     if (dmaResponseQueue_in.isReady()) {
 110       peek( dmaResponseQueue_in, ResponseMsg) {
 111         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
 112           trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address),
 113                   TBEs[makeLineAddress(in_msg.Address)]);
 114         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
 115        in_msg.Type == CoherenceResponseType:DATA) {
 116           trigger(Event:Data, makeLineAddress(in_msg.Address),
 117                   TBEs[makeLineAddress(in_msg.Address)]);
 118         } else if (in_msg.Type == CoherenceResponseType:ACK) {
 119           trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address),
 120                   TBEs[makeLineAddress(in_msg.Address)]);
 121         } else {
 122           error("Invalid response type");
 123         }
 124       }
 125     }
 126   }
 127
 128   // Trigger Queue
 129   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 130     if (triggerQueue_in.isReady()) {
 131       peek(triggerQueue_in, TriggerMsg) {
 132         if (in_msg.Type == TriggerType:ALL_ACKS) {
 133           trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]);
 134         } else {
 135           error("Unexpected message");
 136         }
 137       }
 138     }
 139   }
 140
 141   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 142     peek(dmaRequestQueue_in, SequencerMsg) {
 143       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 144         out_msg.Address := in_msg.PhysicalAddress;
 145         out_msg.Type := CoherenceRequestType:DMA_READ;
 146         out_msg.DataBlk := in_msg.DataBlk;
 147         out_msg.Len := in_msg.Len;
 148         out_msg.Destination.add(map_Address_to_Directory(address));
 149         out_msg.Requestor := machineID;
 150         out_msg.RequestorMachine := MachineType:DMA;
 151         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 152       }
 153     }
 154   }
 155
 156   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 157     peek(dmaRequestQueue_in, SequencerMsg) {
 158       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 159           out_msg.Address := in_msg.PhysicalAddress;
 160           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 161           out_msg.DataBlk := in_msg.DataBlk;
 162           out_msg.Len := in_msg.Len;
 163           out_msg.Destination.add(map_Address_to_Directory(address));
 164           out_msg.Requestor := machineID;
 165           out_msg.RequestorMachine := MachineType:DMA;
 166           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 167         }
 168       }
 169   }
 170
 171   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 172       dma_sequencer.ackCallback();
 173   }
 174
 175   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 176     assert(is_valid(tbe));
 177     if (tbe.NumAcks == 0) {
 178       enqueue(triggerQueue_out, TriggerMsg) {
 179         out_msg.Address := address;
 180         out_msg.Type := TriggerType:ALL_ACKS;
 181       }
 182     }
 183   }
 184
 185   action(u_updateAckCount, "u", desc="Update ack count") {
 186     peek(dmaResponseQueue_in, ResponseMsg) {
 187       assert(is_valid(tbe));
 188       tbe.NumAcks := tbe.NumAcks - in_msg.Acks;
 189     }
 190   }
 191
 192   action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
 193     enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) {
 194       out_msg.Address := address;
 195       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 196       out_msg.Destination.add(map_Address_to_Directory(address));
 197       out_msg.Sender := machineID;
 198       out_msg.SenderMachine := MachineType:DMA;
 199       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 200     }
 201   }
 202
 203   action(p_popRequestQueue, "p", desc="Pop request queue") {
 204     dmaRequestQueue_in.dequeue();
 205   }
 206
 207   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 208     dmaResponseQueue_in.dequeue();
 209   }
 210
 211   action(p_popTriggerQueue, "pp", desc="Pop trigger queue") {
 212     triggerQueue_in.dequeue();
 213   }
 214
 215   action(t_updateTBEData, "t", desc="Update TBE Data") {
 216     peek(dmaResponseQueue_in, ResponseMsg) {
 217       assert(is_valid(tbe));
 218       tbe.DataBlk := in_msg.DataBlk;
 219     }
 220   }
 221
 222   action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
 223     assert(is_valid(tbe));
 224     dma_sequencer.dataCallback(tbe.DataBlk);
 225   }
 226
 227   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
 228     TBEs.allocate(address);
 229     set_tbe(TBEs[address]);
 230   }
 231
 232   action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
 233     TBEs.deallocate(address);
 234     unset_tbe();
 235   }
 236
 237   action(z_stall, "z", desc="dma is busy..stall") {
 238     // do nothing
 239   }
 240
 241
 242
 243   transition(READY, ReadRequest, BUSY_RD) {
 244     s_sendReadRequest;
 245     v_allocateTBE;
 246     p_popRequestQueue;
 247   }
 248
 249   transition(BUSY_RD, Inv_Ack) {
 250     u_updateAckCount;
 251     o_checkForCompletion;
 252     p_popResponseQueue;
 253   }
 254
 255   transition(BUSY_RD, Data, READY) {
 256     t_updateTBEData;
 257     d_dataCallbackFromTBE;
 258     w_deallocateTBE;
 259     //u_updateAckCount;
 260     //o_checkForCompletion;
 261     p_popResponseQueue;
 262   }
 263
 264   transition(BUSY_RD, All_Acks, READY) {
 265     d_dataCallbackFromTBE;
 266     //u_sendExclusiveUnblockToDir;
 267     w_deallocateTBE;
 268     p_popTriggerQueue;
 269   }
 270
 271   transition(READY, WriteRequest, BUSY_WR) {
 272     s_sendWriteRequest;
 273     v_allocateTBE;
 274     p_popRequestQueue;
 275   }
 276
 277   transition(BUSY_WR, Inv_Ack) {
 278     u_updateAckCount;
 279     o_checkForCompletion;
 280     p_popResponseQueue;
 281   }
 282
 283   transition(BUSY_WR, DMA_Ack) {
 284     u_updateAckCount; // actually increases
 285     o_checkForCompletion;
 286     p_popResponseQueue;
 287   }
 288
 289   transition(BUSY_WR, All_Acks, READY) {
 290     a_ackCallback;
 291     u_sendExclusiveUnblockToDir;
 292     w_deallocateTBE;
 293     p_popTriggerQueue;
 294   }
 295 }