src/mem/protocol/MOESI_CMP_directory-dma.sm

   1
   2 machine(DMA, "DMA Controller")
   3 : DMASequencer * dma_sequencer,
   4   int request_latency = 14,
   5   int response_latency = 14
   6 {
   7
   8   MessageBuffer goo1, network="From", virtual_network="0", ordered="false";
   9   MessageBuffer goo2, network="From", virtual_network="1", ordered="false";
  10   MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false";
  11
  12   MessageBuffer foo1, network="To", virtual_network="0", ordered="false";
  13   MessageBuffer reqToDir, network="To", virtual_network="1", ordered="false";
  14   MessageBuffer respToDir, network="To", virtual_network="2", ordered="false";
  15
  16   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  17     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  18     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  19     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  20   }
  21
  22   enumeration(Event, desc="DMA events") {
  23     ReadRequest,  desc="A new read request";
  24     WriteRequest, desc="A new write request";
  25     Data,         desc="Data from a DMA memory read";
  26     DMA_Ack,      desc="DMA write to memory completed";
  27     Inv_Ack,      desc="Invalidation Ack from a sharer";
  28     All_Acks,     desc="All acks received";
  29   }
  30
  31   structure(TBE, desc="...") {
  32     Address address, desc="Physical address";
  33     int NumAcks, default="0", desc="Number of Acks pending";
  34     DataBlock DataBlk, desc="Data";
  35   }
  36
  37   structure(DMASequencer, external = "yes") {
  38     void ackCallback();
  39     void dataCallback(DataBlock);
  40   }
  41
  42   structure(TBETable, external = "yes") {
  43     TBE lookup(Address);
  44     void allocate(Address);
  45     void deallocate(Address);
  46     bool isPresent(Address);
  47   }
  48
  49   MessageBuffer mandatoryQueue, ordered="false";
  50   MessageBuffer triggerQueue, ordered="true";
  51   TBETable TBEs, template_hack="<DMA_TBE>";
  52   State cur_state;
  53
  54   void set_tbe(TBE b);
  55   void unset_tbe();
  56
  57   State getState(TBE tbe, Address addr) {
  58     return cur_state;
  59   }
  60   void setState(TBE tbe, Address addr, State state) {
  61   cur_state := state;
  62   }
  63
  64   out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
  65   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
  66   out_port(foo1_out, ResponseMsg, foo1, desc="...");
  67   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
  68
  69   in_port(goo1_in, RequestMsg, goo1) {
  70     if (goo1_in.isReady()) {
  71       peek(goo1_in, RequestMsg) {
  72         assert(false);
  73       }
  74     }
  75   }
  76
  77   in_port(goo2_in, RequestMsg, goo2) {
  78     if (goo2_in.isReady()) {
  79       peek(goo2_in, RequestMsg) {
  80         assert(false);
  81       }
  82     }
  83   }
  84
  85   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  86     if (dmaRequestQueue_in.isReady()) {
  87       peek(dmaRequestQueue_in, SequencerMsg) {
  88         if (in_msg.Type == SequencerRequestType:LD ) {
  89           trigger(Event:ReadRequest, in_msg.LineAddress,
  90                   TBEs[in_msg.LineAddress]);
  91         } else if (in_msg.Type == SequencerRequestType:ST) {
  92           trigger(Event:WriteRequest, in_msg.LineAddress,
  93                   TBEs[in_msg.LineAddress]);
  94         } else {
  95           error("Invalid request type");
  96         }
  97       }
  98     }
  99   }
 100
 101   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 102     if (dmaResponseQueue_in.isReady()) {
 103       peek( dmaResponseQueue_in, ResponseMsg) {
 104         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
 105           trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address),
 106                   TBEs[makeLineAddress(in_msg.Address)]);
 107         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
 108        in_msg.Type == CoherenceResponseType:DATA) {
 109           trigger(Event:Data, makeLineAddress(in_msg.Address),
 110                   TBEs[makeLineAddress(in_msg.Address)]);
 111         } else if (in_msg.Type == CoherenceResponseType:ACK) {
 112           trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address),
 113                   TBEs[makeLineAddress(in_msg.Address)]);
 114         } else {
 115           error("Invalid response type");
 116         }
 117       }
 118     }
 119   }
 120
 121   // Trigger Queue
 122   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 123     if (triggerQueue_in.isReady()) {
 124       peek(triggerQueue_in, TriggerMsg) {
 125         if (in_msg.Type == TriggerType:ALL_ACKS) {
 126           trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]);
 127         } else {
 128           error("Unexpected message");
 129         }
 130       }
 131     }
 132   }
 133
 134   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 135     peek(dmaRequestQueue_in, SequencerMsg) {
 136       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 137         out_msg.Address := in_msg.PhysicalAddress;
 138         out_msg.Type := CoherenceRequestType:DMA_READ;
 139         out_msg.DataBlk := in_msg.DataBlk;
 140         out_msg.Len := in_msg.Len;
 141         out_msg.Destination.add(map_Address_to_Directory(address));
 142         out_msg.Requestor := machineID;
 143         out_msg.RequestorMachine := MachineType:DMA;
 144         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 145       }
 146     }
 147   }
 148
 149   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 150     peek(dmaRequestQueue_in, SequencerMsg) {
 151       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 152           out_msg.Address := in_msg.PhysicalAddress;
 153           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 154           out_msg.DataBlk := in_msg.DataBlk;
 155           out_msg.Len := in_msg.Len;
 156           out_msg.Destination.add(map_Address_to_Directory(address));
 157           out_msg.Requestor := machineID;
 158           out_msg.RequestorMachine := MachineType:DMA;
 159           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 160         }
 161       }
 162   }
 163
 164   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 165       dma_sequencer.ackCallback();
 166   }
 167
 168   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 169     assert(is_valid(tbe));
 170     if (tbe.NumAcks == 0) {
 171       enqueue(triggerQueue_out, TriggerMsg) {
 172         out_msg.Address := address;
 173         out_msg.Type := TriggerType:ALL_ACKS;
 174       }
 175     }
 176   }
 177
 178   action(u_updateAckCount, "u", desc="Update ack count") {
 179     peek(dmaResponseQueue_in, ResponseMsg) {
 180       assert(is_valid(tbe));
 181       tbe.NumAcks := tbe.NumAcks - in_msg.Acks;
 182     }
 183   }
 184
 185   action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
 186     enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) {
 187       out_msg.Address := address;
 188       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 189       out_msg.Destination.add(map_Address_to_Directory(address));
 190       out_msg.Sender := machineID;
 191       out_msg.SenderMachine := MachineType:DMA;
 192       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 193     }
 194   }
 195
 196   action(p_popRequestQueue, "p", desc="Pop request queue") {
 197     dmaRequestQueue_in.dequeue();
 198   }
 199
 200   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 201     dmaResponseQueue_in.dequeue();
 202   }
 203
 204   action(p_popTriggerQueue, "pp", desc="Pop trigger queue") {
 205     triggerQueue_in.dequeue();
 206   }
 207
 208   action(t_updateTBEData, "t", desc="Update TBE Data") {
 209     peek(dmaResponseQueue_in, ResponseMsg) {
 210       assert(is_valid(tbe));
 211       tbe.DataBlk := in_msg.DataBlk;
 212     }
 213   }
 214
 215   action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
 216     assert(is_valid(tbe));
 217     dma_sequencer.dataCallback(tbe.DataBlk);
 218   }
 219
 220   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
 221     TBEs.allocate(address);
 222     set_tbe(TBEs[address]);
 223   }
 224
 225   action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
 226     TBEs.deallocate(address);
 227     unset_tbe();
 228   }
 229
 230   action(z_stall, "z", desc="dma is busy..stall") {
 231     // do nothing
 232   }
 233
 234
 235
 236   transition(READY, ReadRequest, BUSY_RD) {
 237     s_sendReadRequest;
 238     v_allocateTBE;
 239     p_popRequestQueue;
 240   }
 241
 242   transition(BUSY_RD, Inv_Ack) {
 243     u_updateAckCount;
 244     o_checkForCompletion;
 245     p_popResponseQueue;
 246   }
 247
 248   transition(BUSY_RD, Data, READY) {
 249     t_updateTBEData;
 250     d_dataCallbackFromTBE;
 251     w_deallocateTBE;
 252     //u_updateAckCount;
 253     //o_checkForCompletion;
 254     p_popResponseQueue;
 255   }
 256
 257   transition(BUSY_RD, All_Acks, READY) {
 258     d_dataCallbackFromTBE;
 259     //u_sendExclusiveUnblockToDir;
 260     w_deallocateTBE;
 261     p_popTriggerQueue;
 262   }
 263
 264   transition(READY, WriteRequest, BUSY_WR) {
 265     s_sendWriteRequest;
 266     v_allocateTBE;
 267     p_popRequestQueue;
 268   }
 269
 270   transition(BUSY_WR, Inv_Ack) {
 271     u_updateAckCount;
 272     o_checkForCompletion;
 273     p_popResponseQueue;
 274   }
 275
 276   transition(BUSY_WR, DMA_Ack) {
 277     u_updateAckCount; // actually increases
 278     o_checkForCompletion;
 279     p_popResponseQueue;
 280   }
 281
 282   transition(BUSY_WR, All_Acks, READY) {
 283     a_ackCallback;
 284     u_sendExclusiveUnblockToDir;
 285     w_deallocateTBE;
 286     p_popTriggerQueue;
 287   }
 288 }