src/mem/protocol/MOESI_CMP_directory-dma.sm

   1 /*
   2  * Copyright (c) 2009-2013 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 machine(DMA, "DMA Controller")
  31     : DMASequencer * dma_sequencer;
  32       Cycles request_latency := 14;
  33       Cycles response_latency := 14;
  34
  35       MessageBuffer * responseFromDir, network="From", virtual_network="2",
  36             vnet_type="response";
  37
  38       MessageBuffer * reqToDir, network="To", virtual_network="1",
  39             vnet_type="request";
  40       MessageBuffer * respToDir, network="To", virtual_network="2",
  41             vnet_type="dmaresponse";
  42
  43       MessageBuffer * mandatoryQueue;
  44       MessageBuffer * triggerQueue;
  45 {
  46   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  47     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  48     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  49     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  50   }
  51
  52   enumeration(Event, desc="DMA events") {
  53     ReadRequest,  desc="A new read request";
  54     WriteRequest, desc="A new write request";
  55     Data,         desc="Data from a DMA memory read";
  56     DMA_Ack,      desc="DMA write to memory completed";
  57     Inv_Ack,      desc="Invalidation Ack from a sharer";
  58     All_Acks,     desc="All acks received";
  59   }
  60
  61   structure(TBE, desc="...") {
  62     Addr address, desc="Physical address";
  63     int NumAcks, default="0", desc="Number of Acks pending";
  64     DataBlock DataBlk, desc="Data";
  65   }
  66
  67   structure(TBETable, external = "yes") {
  68     TBE lookup(Addr);
  69     void allocate(Addr);
  70     void deallocate(Addr);
  71     bool isPresent(Addr);
  72   }
  73
  74   TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
  75   State cur_state;
  76
  77   Tick clockEdge();
  78   void set_tbe(TBE b);
  79   void unset_tbe();
  80
  81   State getState(TBE tbe, Addr addr) {
  82     return cur_state;
  83   }
  84   void setState(TBE tbe, Addr addr, State state) {
  85   cur_state := state;
  86   }
  87
  88   AccessPermission getAccessPermission(Addr addr) {
  89     return AccessPermission:NotPresent;
  90   }
  91
  92   void setAccessPermission(Addr addr, State state) {
  93   }
  94
  95   void functionalRead(Addr addr, Packet *pkt) {
  96     error("DMA does not support functional read.");
  97   }
  98
  99   int functionalWrite(Addr addr, Packet *pkt) {
 100     error("DMA does not support functional write.");
 101   }
 102
 103   out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
 104   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
 105   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
 106
 107   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
 108     if (dmaRequestQueue_in.isReady(clockEdge())) {
 109       peek(dmaRequestQueue_in, SequencerMsg) {
 110         if (in_msg.Type == SequencerRequestType:LD ) {
 111           trigger(Event:ReadRequest, in_msg.LineAddress,
 112                   TBEs[in_msg.LineAddress]);
 113         } else if (in_msg.Type == SequencerRequestType:ST) {
 114           trigger(Event:WriteRequest, in_msg.LineAddress,
 115                   TBEs[in_msg.LineAddress]);
 116         } else {
 117           error("Invalid request type");
 118         }
 119       }
 120     }
 121   }
 122
 123   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 124     if (dmaResponseQueue_in.isReady(clockEdge())) {
 125       peek( dmaResponseQueue_in, ResponseMsg) {
 126         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
 127           trigger(Event:DMA_Ack, makeLineAddress(in_msg.addr),
 128                   TBEs[makeLineAddress(in_msg.addr)]);
 129         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
 130        in_msg.Type == CoherenceResponseType:DATA) {
 131           trigger(Event:Data, makeLineAddress(in_msg.addr),
 132                   TBEs[makeLineAddress(in_msg.addr)]);
 133         } else if (in_msg.Type == CoherenceResponseType:ACK) {
 134           trigger(Event:Inv_Ack, makeLineAddress(in_msg.addr),
 135                   TBEs[makeLineAddress(in_msg.addr)]);
 136         } else {
 137           error("Invalid response type");
 138         }
 139       }
 140     }
 141   }
 142
 143   // Trigger Queue
 144   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 145     if (triggerQueue_in.isReady(clockEdge())) {
 146       peek(triggerQueue_in, TriggerMsg) {
 147         if (in_msg.Type == TriggerType:ALL_ACKS) {
 148           trigger(Event:All_Acks, in_msg.addr, TBEs[in_msg.addr]);
 149         } else {
 150           error("Unexpected message");
 151         }
 152       }
 153     }
 154   }
 155
 156   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 157     peek(dmaRequestQueue_in, SequencerMsg) {
 158       enqueue(reqToDirectory_out, RequestMsg, request_latency) {
 159         out_msg.addr := in_msg.PhysicalAddress;
 160         out_msg.Type := CoherenceRequestType:DMA_READ;
 161         out_msg.DataBlk := in_msg.DataBlk;
 162         out_msg.Len := in_msg.Len;
 163         out_msg.Destination.add(map_Address_to_Directory(address));
 164         out_msg.Requestor := machineID;
 165         out_msg.RequestorMachine := MachineType:DMA;
 166         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 167       }
 168     }
 169   }
 170
 171   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 172     peek(dmaRequestQueue_in, SequencerMsg) {
 173       enqueue(reqToDirectory_out, RequestMsg, request_latency) {
 174           out_msg.addr := in_msg.PhysicalAddress;
 175           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 176           out_msg.DataBlk := in_msg.DataBlk;
 177           out_msg.Len := in_msg.Len;
 178           out_msg.Destination.add(map_Address_to_Directory(address));
 179           out_msg.Requestor := machineID;
 180           out_msg.RequestorMachine := MachineType:DMA;
 181           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 182         }
 183       }
 184   }
 185
 186   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 187       dma_sequencer.ackCallback();
 188   }
 189
 190   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 191     assert(is_valid(tbe));
 192     if (tbe.NumAcks == 0) {
 193       enqueue(triggerQueue_out, TriggerMsg) {
 194         out_msg.addr := address;
 195         out_msg.Type := TriggerType:ALL_ACKS;
 196       }
 197     }
 198   }
 199
 200   action(u_updateAckCount, "u", desc="Update ack count") {
 201     peek(dmaResponseQueue_in, ResponseMsg) {
 202       assert(is_valid(tbe));
 203       tbe.NumAcks := tbe.NumAcks - in_msg.Acks;
 204     }
 205   }
 206
 207   action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
 208     enqueue(respToDirectory_out, ResponseMsg, response_latency) {
 209       out_msg.addr := address;
 210       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 211       out_msg.Destination.add(map_Address_to_Directory(address));
 212       out_msg.Sender := machineID;
 213       out_msg.SenderMachine := MachineType:DMA;
 214       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 215     }
 216   }
 217
 218   action(p_popRequestQueue, "p", desc="Pop request queue") {
 219     dmaRequestQueue_in.dequeue(clockEdge());
 220   }
 221
 222   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 223     dmaResponseQueue_in.dequeue(clockEdge());
 224   }
 225
 226   action(p_popTriggerQueue, "pp", desc="Pop trigger queue") {
 227     triggerQueue_in.dequeue(clockEdge());
 228   }
 229
 230   action(t_updateTBEData, "t", desc="Update TBE Data") {
 231     peek(dmaResponseQueue_in, ResponseMsg) {
 232       assert(is_valid(tbe));
 233       tbe.DataBlk := in_msg.DataBlk;
 234     }
 235   }
 236
 237   action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
 238     assert(is_valid(tbe));
 239     dma_sequencer.dataCallback(tbe.DataBlk);
 240   }
 241
 242   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
 243     TBEs.allocate(address);
 244     set_tbe(TBEs[address]);
 245   }
 246
 247   action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
 248     TBEs.deallocate(address);
 249     unset_tbe();
 250   }
 251
 252
 253   transition(READY, ReadRequest, BUSY_RD) {
 254     s_sendReadRequest;
 255     v_allocateTBE;
 256     p_popRequestQueue;
 257   }
 258
 259   transition(BUSY_RD, Inv_Ack) {
 260     u_updateAckCount;
 261     o_checkForCompletion;
 262     p_popResponseQueue;
 263   }
 264
 265   transition(BUSY_RD, Data, READY) {
 266     t_updateTBEData;
 267     d_dataCallbackFromTBE;
 268     w_deallocateTBE;
 269     //u_updateAckCount;
 270     //o_checkForCompletion;
 271     p_popResponseQueue;
 272   }
 273
 274   transition(BUSY_RD, All_Acks, READY) {
 275     d_dataCallbackFromTBE;
 276     //u_sendExclusiveUnblockToDir;
 277     w_deallocateTBE;
 278     p_popTriggerQueue;
 279   }
 280
 281   transition(READY, WriteRequest, BUSY_WR) {
 282     s_sendWriteRequest;
 283     v_allocateTBE;
 284     p_popRequestQueue;
 285   }
 286
 287   transition(BUSY_WR, Inv_Ack) {
 288     u_updateAckCount;
 289     o_checkForCompletion;
 290     p_popResponseQueue;
 291   }
 292
 293   transition(BUSY_WR, DMA_Ack) {
 294     u_updateAckCount; // actually increases
 295     o_checkForCompletion;
 296     p_popResponseQueue;
 297   }
 298
 299   transition(BUSY_WR, All_Acks, READY) {
 300     a_ackCallback;
 301     u_sendExclusiveUnblockToDir;
 302     w_deallocateTBE;
 303     p_popTriggerQueue;
 304   }
 305 }