src/mem/protocol/MOESI_CMP_directory-dma.sm

   1
   2 machine(DMA, "DMA Controller")
   3 : DMASequencer * dma_sequencer,
   4   int request_latency = 14,
   5   int response_latency = 14
   6 {
   7
   8   MessageBuffer goo1, network="From", virtual_network="0", ordered="false", vnet_type="goo";
   9   MessageBuffer goo2, network="From", virtual_network="1", ordered="false", vnet_type="goo";
  10   MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response";
  11
  12   MessageBuffer foo1, network="To", virtual_network="0", ordered="false", vnet_type="foo";
  13   MessageBuffer reqToDir, network="To", virtual_network="1", ordered="false", vnet_type="request";
  14   MessageBuffer respToDir, network="To", virtual_network="2", ordered="false", vnet_type="dmaresponse";
  15
  16   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
  17     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
  18     BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
  19     BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
  20   }
  21
  22   enumeration(Event, desc="DMA events") {
  23     ReadRequest,  desc="A new read request";
  24     WriteRequest, desc="A new write request";
  25     Data,         desc="Data from a DMA memory read";
  26     DMA_Ack,      desc="DMA write to memory completed";
  27     Inv_Ack,      desc="Invalidation Ack from a sharer";
  28     All_Acks,     desc="All acks received";
  29   }
  30
  31   structure(TBE, desc="...") {
  32     Address address, desc="Physical address";
  33     int NumAcks, default="0", desc="Number of Acks pending";
  34     DataBlock DataBlk, desc="Data";
  35   }
  36
  37   structure(DMASequencer, external = "yes") {
  38     void ackCallback();
  39     void dataCallback(DataBlock);
  40   }
  41
  42   structure(TBETable, external = "yes") {
  43     TBE lookup(Address);
  44     void allocate(Address);
  45     void deallocate(Address);
  46     bool isPresent(Address);
  47   }
  48
  49   MessageBuffer mandatoryQueue, ordered="false";
  50   MessageBuffer triggerQueue, ordered="true";
  51   TBETable TBEs, template_hack="<DMA_TBE>";
  52   State cur_state;
  53
  54   void set_tbe(TBE b);
  55   void unset_tbe();
  56
  57   State getState(TBE tbe, Address addr) {
  58     return cur_state;
  59   }
  60   void setState(TBE tbe, Address addr, State state) {
  61   cur_state := state;
  62   }
  63
  64   AccessPermission getAccessPermission(Address addr) {
  65     return AccessPermission:NotPresent;
  66   }
  67
  68   void setAccessPermission(Address addr, State state) {
  69   }
  70
  71   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
  72      error("DMA Controller does not support getDataBlock().\n");
  73   }
  74
  75   out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
  76   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
  77   out_port(foo1_out, ResponseMsg, foo1, desc="...");
  78   out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
  79
  80   in_port(goo1_in, RequestMsg, goo1) {
  81     if (goo1_in.isReady()) {
  82       peek(goo1_in, RequestMsg) {
  83         assert(false);
  84       }
  85     }
  86   }
  87
  88   in_port(goo2_in, RequestMsg, goo2) {
  89     if (goo2_in.isReady()) {
  90       peek(goo2_in, RequestMsg) {
  91         assert(false);
  92       }
  93     }
  94   }
  95
  96   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
  97     if (dmaRequestQueue_in.isReady()) {
  98       peek(dmaRequestQueue_in, SequencerMsg) {
  99         if (in_msg.Type == SequencerRequestType:LD ) {
 100           trigger(Event:ReadRequest, in_msg.LineAddress,
 101                   TBEs[in_msg.LineAddress]);
 102         } else if (in_msg.Type == SequencerRequestType:ST) {
 103           trigger(Event:WriteRequest, in_msg.LineAddress,
 104                   TBEs[in_msg.LineAddress]);
 105         } else {
 106           error("Invalid request type");
 107         }
 108       }
 109     }
 110   }
 111
 112   in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
 113     if (dmaResponseQueue_in.isReady()) {
 114       peek( dmaResponseQueue_in, ResponseMsg) {
 115         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
 116           trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address),
 117                   TBEs[makeLineAddress(in_msg.Address)]);
 118         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
 119        in_msg.Type == CoherenceResponseType:DATA) {
 120           trigger(Event:Data, makeLineAddress(in_msg.Address),
 121                   TBEs[makeLineAddress(in_msg.Address)]);
 122         } else if (in_msg.Type == CoherenceResponseType:ACK) {
 123           trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address),
 124                   TBEs[makeLineAddress(in_msg.Address)]);
 125         } else {
 126           error("Invalid response type");
 127         }
 128       }
 129     }
 130   }
 131
 132   // Trigger Queue
 133   in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 134     if (triggerQueue_in.isReady()) {
 135       peek(triggerQueue_in, TriggerMsg) {
 136         if (in_msg.Type == TriggerType:ALL_ACKS) {
 137           trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]);
 138         } else {
 139           error("Unexpected message");
 140         }
 141       }
 142     }
 143   }
 144
 145   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
 146     peek(dmaRequestQueue_in, SequencerMsg) {
 147       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 148         out_msg.Address := in_msg.PhysicalAddress;
 149         out_msg.Type := CoherenceRequestType:DMA_READ;
 150         out_msg.DataBlk := in_msg.DataBlk;
 151         out_msg.Len := in_msg.Len;
 152         out_msg.Destination.add(map_Address_to_Directory(address));
 153         out_msg.Requestor := machineID;
 154         out_msg.RequestorMachine := MachineType:DMA;
 155         out_msg.MessageSize := MessageSizeType:Writeback_Control;
 156       }
 157     }
 158   }
 159
 160   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
 161     peek(dmaRequestQueue_in, SequencerMsg) {
 162       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
 163           out_msg.Address := in_msg.PhysicalAddress;
 164           out_msg.Type := CoherenceRequestType:DMA_WRITE;
 165           out_msg.DataBlk := in_msg.DataBlk;
 166           out_msg.Len := in_msg.Len;
 167           out_msg.Destination.add(map_Address_to_Directory(address));
 168           out_msg.Requestor := machineID;
 169           out_msg.RequestorMachine := MachineType:DMA;
 170           out_msg.MessageSize := MessageSizeType:Writeback_Control;
 171         }
 172       }
 173   }
 174
 175   action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
 176       dma_sequencer.ackCallback();
 177   }
 178
 179   action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
 180     assert(is_valid(tbe));
 181     if (tbe.NumAcks == 0) {
 182       enqueue(triggerQueue_out, TriggerMsg) {
 183         out_msg.Address := address;
 184         out_msg.Type := TriggerType:ALL_ACKS;
 185       }
 186     }
 187   }
 188
 189   action(u_updateAckCount, "u", desc="Update ack count") {
 190     peek(dmaResponseQueue_in, ResponseMsg) {
 191       assert(is_valid(tbe));
 192       tbe.NumAcks := tbe.NumAcks - in_msg.Acks;
 193     }
 194   }
 195
 196   action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
 197     enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) {
 198       out_msg.Address := address;
 199       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
 200       out_msg.Destination.add(map_Address_to_Directory(address));
 201       out_msg.Sender := machineID;
 202       out_msg.SenderMachine := MachineType:DMA;
 203       out_msg.MessageSize := MessageSizeType:Writeback_Control;
 204     }
 205   }
 206
 207   action(p_popRequestQueue, "p", desc="Pop request queue") {
 208     dmaRequestQueue_in.dequeue();
 209   }
 210
 211   action(p_popResponseQueue, "\p", desc="Pop request queue") {
 212     dmaResponseQueue_in.dequeue();
 213   }
 214
 215   action(p_popTriggerQueue, "pp", desc="Pop trigger queue") {
 216     triggerQueue_in.dequeue();
 217   }
 218
 219   action(t_updateTBEData, "t", desc="Update TBE Data") {
 220     peek(dmaResponseQueue_in, ResponseMsg) {
 221       assert(is_valid(tbe));
 222       tbe.DataBlk := in_msg.DataBlk;
 223     }
 224   }
 225
 226   action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
 227     assert(is_valid(tbe));
 228     dma_sequencer.dataCallback(tbe.DataBlk);
 229   }
 230
 231   action(v_allocateTBE, "v", desc="Allocate TBE entry") {
 232     TBEs.allocate(address);
 233     set_tbe(TBEs[address]);
 234   }
 235
 236   action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
 237     TBEs.deallocate(address);
 238     unset_tbe();
 239   }
 240
 241   action(z_stall, "z", desc="dma is busy..stall") {
 242     // do nothing
 243   }
 244
 245
 246
 247   transition(READY, ReadRequest, BUSY_RD) {
 248     s_sendReadRequest;
 249     v_allocateTBE;
 250     p_popRequestQueue;
 251   }
 252
 253   transition(BUSY_RD, Inv_Ack) {
 254     u_updateAckCount;
 255     o_checkForCompletion;
 256     p_popResponseQueue;
 257   }
 258
 259   transition(BUSY_RD, Data, READY) {
 260     t_updateTBEData;
 261     d_dataCallbackFromTBE;
 262     w_deallocateTBE;
 263     //u_updateAckCount;
 264     //o_checkForCompletion;
 265     p_popResponseQueue;
 266   }
 267
 268   transition(BUSY_RD, All_Acks, READY) {
 269     d_dataCallbackFromTBE;
 270     //u_sendExclusiveUnblockToDir;
 271     w_deallocateTBE;
 272     p_popTriggerQueue;
 273   }
 274
 275   transition(READY, WriteRequest, BUSY_WR) {
 276     s_sendWriteRequest;
 277     v_allocateTBE;
 278     p_popRequestQueue;
 279   }
 280
 281   transition(BUSY_WR, Inv_Ack) {
 282     u_updateAckCount;
 283     o_checkForCompletion;
 284     p_popResponseQueue;
 285   }
 286
 287   transition(BUSY_WR, DMA_Ack) {
 288     u_updateAckCount; // actually increases
 289     o_checkForCompletion;
 290     p_popResponseQueue;
 291   }
 292
 293   transition(BUSY_WR, All_Acks, READY) {
 294     a_ackCallback;
 295     u_sendExclusiveUnblockToDir;
 296     w_deallocateTBE;
 297     p_popTriggerQueue;
 298   }
 299 }